[coreboot-gerrit] New patch to review for coreboot: d93fe33 superio/intel/i3100: Avoid .c includes
Edward O'Callaghan (eocallaghan@alterapraxis.com)
gerrit at coreboot.org
Sat May 24 05:27:53 CEST 2014
Edward O'Callaghan (eocallaghan at alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5840
-gerrit
commit d93fe33322c7dd969a527a2affbd8bc5eb4d1245
Author: Edward O'Callaghan <eocallaghan at alterapraxis.com>
Date: Mon Mar 31 21:30:11 2014 +1100
superio/intel/i3100: Avoid .c includes
Following the same reasoning as commit:
d304331 superio/fintek/f81865f: Avoid .c includes
Change-Id: I0339d6f188c3e9e2ad5bbef116599a52453b0a19
Signed-off-by: Edward O'Callaghan <eocallaghan at alterapraxis.com>
---
src/mainboard/intel/eagleheights/romstage.c | 2 +-
src/mainboard/intel/mtarvon/romstage.c | 3 +--
src/mainboard/intel/truxton/romstage.c | 3 +--
src/superio/intel/i3100/Makefile.inc | 2 +-
src/superio/intel/i3100/early_serial.c | 8 ++++++--
src/superio/intel/i3100/i3100.h | 16 +++++++++-------
6 files changed, 19 insertions(+), 15 deletions(-)
diff --git a/src/mainboard/intel/eagleheights/romstage.c b/src/mainboard/intel/eagleheights/romstage.c
index 3aeb71c..e2273c2 100644
--- a/src/mainboard/intel/eagleheights/romstage.c
+++ b/src/mainboard/intel/eagleheights/romstage.c
@@ -33,7 +33,7 @@
#include "southbridge/intel/i3100/early_smbus.c"
#include "southbridge/intel/i3100/early_lpc.c"
#include "southbridge/intel/i3100/reset.c"
-#include "superio/intel/i3100/early_serial.c"
+#include <superio/intel/i3100/i3100.h>
#include "superio/smsc/smscsuperio/early_serial.c"
#include "northbridge/intel/i3100/i3100.h"
#include "southbridge/intel/i3100/i3100.h"
diff --git a/src/mainboard/intel/mtarvon/romstage.c b/src/mainboard/intel/mtarvon/romstage.c
index 0cab9bd..eb2af1b 100644
--- a/src/mainboard/intel/mtarvon/romstage.c
+++ b/src/mainboard/intel/mtarvon/romstage.c
@@ -29,8 +29,7 @@
#include "southbridge/intel/i3100/early_smbus.c"
#include "southbridge/intel/i3100/early_lpc.c"
#include "northbridge/intel/i3100/raminit.h"
-#include "superio/intel/i3100/i3100.h"
-#include "superio/intel/i3100/early_serial.c"
+#include <superio/intel/i3100/i3100.h>
#include "northbridge/intel/i3100/memory_initialized.c"
#include "cpu/x86/bist.h"
#include <spd.h>
diff --git a/src/mainboard/intel/truxton/romstage.c b/src/mainboard/intel/truxton/romstage.c
index 71c5f38..08b1a18 100644
--- a/src/mainboard/intel/truxton/romstage.c
+++ b/src/mainboard/intel/truxton/romstage.c
@@ -30,10 +30,9 @@
#include "southbridge/intel/i3100/early_smbus.c"
#include "southbridge/intel/i3100/early_lpc.c"
#include "northbridge/intel/i3100/raminit_ep80579.h"
-#include "superio/intel/i3100/i3100.h"
#include "cpu/x86/lapic/boot_cpu.c"
#include "cpu/x86/mtrr/earlymtrr.c"
-#include "superio/intel/i3100/early_serial.c"
+#include <superio/intel/i3100/i3100.h>
#include "cpu/x86/bist.h"
#include <spd.h>
diff --git a/src/superio/intel/i3100/Makefile.inc b/src/superio/intel/i3100/Makefile.inc
index bc3329e..2284398 100644
--- a/src/superio/intel/i3100/Makefile.inc
+++ b/src/superio/intel/i3100/Makefile.inc
@@ -18,5 +18,5 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
+romstage-$(CONFIG_SUPERIO_INTEL_I3100) += early_serial.c
ramstage-$(CONFIG_SUPERIO_INTEL_I3100) += superio.c
-
diff --git a/src/superio/intel/i3100/early_serial.c b/src/superio/intel/i3100/early_serial.c
index f95cf8a..4f61339 100644
--- a/src/superio/intel/i3100/early_serial.c
+++ b/src/superio/intel/i3100/early_serial.c
@@ -19,8 +19,12 @@
*/
#include <arch/io.h>
+#include <device/pnp_def.h>
#include "i3100.h"
+/* Registers and bit definitions: */
+#define I3100_SIW_CONFIGURATION 0x29
+
static void pnp_enter_ext_func_mode(device_t dev)
{
u16 port = dev >> 8;
@@ -38,14 +42,14 @@ static void pnp_exit_ext_func_mode(device_t dev)
}
/* Enable device interrupts, set UART_CLK predivide. */
-static void i3100_configure_uart_clk(device_t dev, u8 predivide)
+void i3100_configure_uart_clk(device_t dev, u8 predivide)
{
pnp_enter_ext_func_mode(dev);
pnp_write_config(dev, I3100_SIW_CONFIGURATION, (predivide << 2) | 1);
pnp_exit_ext_func_mode(dev);
}
-static void i3100_enable_serial(device_t dev, u16 iobase)
+void i3100_enable_serial(device_t dev, u16 iobase)
{
pnp_enter_ext_func_mode(dev);
pnp_set_logical_device(dev);
diff --git a/src/superio/intel/i3100/i3100.h b/src/superio/intel/i3100/i3100.h
index 4b8bf27..8468f95 100644
--- a/src/superio/intel/i3100/i3100.h
+++ b/src/superio/intel/i3100/i3100.h
@@ -18,8 +18,8 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-#ifndef SUPERIO_INTEL_I3100_I3100_H
-#define SUPERIO_INTEL_I3100_I3100_H
+#ifndef SUPERIO_INTEL_I3100_H
+#define SUPERIO_INTEL_I3100_H
/*
* Datasheet:
@@ -46,10 +46,6 @@
#define I3100_SP2 0x05 /* Com2 */
#define I3100_WDT 0x06 /* Watchdog timer */
-/* Registers and bit definitions: */
-
-#define I3100_SIW_CONFIGURATION 0x29
-
/*
* SIW_CONFIGURATION[3:2] = UART_CLK predivide
* 00: divide by 1
@@ -61,4 +57,10 @@
#define I3100_UART_CLK_PREDIVIDE_8 0x01
#define I3100_UART_CLK_PREDIVIDE_26 0x02
-#endif
+#include <arch/io.h>
+#include <stdint.h>
+
+void i3100_configure_uart_clk(device_t dev, u8 predivide);
+void i3100_enable_serial(device_t dev, u16 iobase);
+
+#endif /* SUPERIO_INTEL_I3100_H */
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