[coreboot-gerrit] Patch merged into coreboot/master: c6313db baytrail: Enable PCIe common clock and ASPM
gerrit at coreboot.org
gerrit at coreboot.org
Thu May 15 05:07:10 CEST 2014
the following patch was just integrated into master:
commit c6313db34f26bcb8bdbb5ff04ebc9c9e7193cf0f
Author: Duncan Laurie <dlaurie at chromium.org>
Date: Thu Jan 16 11:18:36 2014 -0800
baytrail: Enable PCIe common clock and ASPM
Enable the config options to have the device enumeration layer configure
common clock and ASPM for endpoints.
BUG=chrome-os-partner:23629
BRANCH=baytrail
TEST=build and boot on rambi, check PCIe for ASPM and common clock:
lspci -vv -s 0:1c.0 | grep LnkCtl:
LnkCtl: ASPM L0s L1 Enabled; RCB 64 bytes Disabled- Retrain- CommClk+
lspci -vv -s 1:00.0 | grep LnkCtl:
LnkCtl: ASPM L0s L1 Enabled; RCB 64 bytes Disabled- Retrain- CommClk+
Change-Id: I2477e3cada0732dc71db0d6692ff5b6159ed269f
Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/182860
Reviewed-by: Aaron Durbin <adurbin at chromium.org>
Signed-off-by: Aaron Durbin <adurbin at chromium.org>
Reviewed-on: http://review.coreboot.org/5051
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter at users.sourceforge.net>
Reviewed-by: Patrick Georgi <patrick at georgi-clan.de>
See http://review.coreboot.org/5051 for details.
-gerrit
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