[coreboot-gerrit] New patch to review for coreboot: e61acff Drop useless mainboard-romstage defines
Patrick Georgi (patrick@georgi-clan.de)
gerrit at coreboot.org
Sat May 3 09:15:14 CEST 2014
Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5639
-gerrit
commit e61acff7500accfe2f5e20b5f7cc418e3c7ac8f6
Author: Patrick Georgi <patrick at georgi-clan.de>
Date: Sat May 3 09:12:55 2014 +0200
Drop useless mainboard-romstage defines
Some src/mainboard/*/*/romstage.c files use defines which later
modify the behaviour of included .c files.
Since it's a pain to work out what is affected by these, drop
values that are only defined in the board but never used, or
defined to identical values as in spd.h (and use that one instead).
Change-Id: I8143b26fddc32a40ac4e611a6287bf7f144267dc
Signed-off-by: Patrick Georgi <patrick at georgi-clan.de>
---
src/mainboard/amd/bimini_fam10/romstage.c | 3 ---
src/mainboard/amd/dbm690t/romstage.c | 5 -----
src/mainboard/amd/mahogany/romstage.c | 5 -----
src/mainboard/asrock/939a785gmh/romstage.c | 5 -----
src/mainboard/kontron/kt690/romstage.c | 5 -----
src/mainboard/siemens/sitemp_g1p1/romstage.c | 10 +---------
src/mainboard/supermicro/h8scm_fam10/romstage.c | 9 ---------
src/mainboard/technexion/tim5690/romstage.c | 5 -----
src/mainboard/technexion/tim8690/romstage.c | 5 -----
9 files changed, 1 insertion(+), 51 deletions(-)
diff --git a/src/mainboard/amd/bimini_fam10/romstage.c b/src/mainboard/amd/bimini_fam10/romstage.c
index 9f930e8..5c5b44f 100644
--- a/src/mainboard/amd/bimini_fam10/romstage.c
+++ b/src/mainboard/amd/bimini_fam10/romstage.c
@@ -67,9 +67,6 @@ static int spd_read_byte(u32 device, u32 address)
#include "cpu/amd/model_10xxx/init_cpus.c"
#include "northbridge/amd/amdfam10/early_ht.c"
-#define RC00 0
-#define RC01 1
-
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
struct sys_info *sysinfo = &sysinfo_car;
diff --git a/src/mainboard/amd/dbm690t/romstage.c b/src/mainboard/amd/dbm690t/romstage.c
index 74b6d1b..7a0c8f9 100644
--- a/src/mainboard/amd/dbm690t/romstage.c
+++ b/src/mainboard/amd/dbm690t/romstage.c
@@ -17,11 +17,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-#define RC0 (6<<8)
-#define RC1 (7<<8)
-
-#define SMBUS_HUB 0x71
-
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>
diff --git a/src/mainboard/amd/mahogany/romstage.c b/src/mainboard/amd/mahogany/romstage.c
index b77d4b5..93870c5 100644
--- a/src/mainboard/amd/mahogany/romstage.c
+++ b/src/mainboard/amd/mahogany/romstage.c
@@ -17,11 +17,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-#define RC0 (6<<8)
-#define RC1 (7<<8)
-
-#define SMBUS_HUB 0x71
-
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>
diff --git a/src/mainboard/asrock/939a785gmh/romstage.c b/src/mainboard/asrock/939a785gmh/romstage.c
index ce0a6ac..417f9a7 100644
--- a/src/mainboard/asrock/939a785gmh/romstage.c
+++ b/src/mainboard/asrock/939a785gmh/romstage.c
@@ -18,11 +18,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-#define RC0 (6<<8)
-#define RC1 (7<<8)
-
-#define SMBUS_HUB 0x71
-
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>
diff --git a/src/mainboard/kontron/kt690/romstage.c b/src/mainboard/kontron/kt690/romstage.c
index 4e45dc4..24cae41 100644
--- a/src/mainboard/kontron/kt690/romstage.c
+++ b/src/mainboard/kontron/kt690/romstage.c
@@ -18,11 +18,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-#define RC0 (6<<8)
-#define RC1 (7<<8)
-
-#define SMBUS_HUB 0x71
-
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>
diff --git a/src/mainboard/siemens/sitemp_g1p1/romstage.c b/src/mainboard/siemens/sitemp_g1p1/romstage.c
index 6d36524..6ae4989 100644
--- a/src/mainboard/siemens/sitemp_g1p1/romstage.c
+++ b/src/mainboard/siemens/sitemp_g1p1/romstage.c
@@ -19,15 +19,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-#define RC0 (6<<8)
-#define RC1 (7<<8)
-
-#define DIMM0 0x50
-#define DIMM1 0x51
-
-#define ICS951462_ADDRESS 0x69
-#define SMBUS_HUB 0x71
-
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>
@@ -36,6 +27,7 @@
#include <cpu/x86/lapic.h>
#include <pc80/mc146818rtc.h>
#include <console/console.h>
+#include <spd.h>
#include <cpu/amd/model_fxx_rev.h>
#include "northbridge/amd/amdk8/raminit.h"
diff --git a/src/mainboard/supermicro/h8scm_fam10/romstage.c b/src/mainboard/supermicro/h8scm_fam10/romstage.c
index e6ce5a8..216e5df 100644
--- a/src/mainboard/supermicro/h8scm_fam10/romstage.c
+++ b/src/mainboard/supermicro/h8scm_fam10/romstage.c
@@ -68,15 +68,6 @@ static int spd_read_byte(u32 device, u32 address)
#include "northbridge/amd/amdfam10/early_ht.c"
#include <spd.h>
-//#include "spd_addr.h"
-
-#define RC00 0
-
-#define DIMM0 0x50
-#define DIMM1 0x51
-#define DIMM2 0x52
-#define DIMM3 0x53
-
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
struct sys_info *sysinfo = &sysinfo_car;
diff --git a/src/mainboard/technexion/tim5690/romstage.c b/src/mainboard/technexion/tim5690/romstage.c
index 42c2599..e6483c0 100644
--- a/src/mainboard/technexion/tim5690/romstage.c
+++ b/src/mainboard/technexion/tim5690/romstage.c
@@ -17,11 +17,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-#define RC0 (6<<8)
-#define RC1 (7<<8)
-
-#define SMBUS_HUB 0x71
-
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>
diff --git a/src/mainboard/technexion/tim8690/romstage.c b/src/mainboard/technexion/tim8690/romstage.c
index 22a1212..2f3ad71 100644
--- a/src/mainboard/technexion/tim8690/romstage.c
+++ b/src/mainboard/technexion/tim8690/romstage.c
@@ -17,11 +17,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-#define RC0 (6<<8)
-#define RC1 (7<<8)
-
-#define SMBUS_HUB 0x71
-
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>
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