[coreboot-gerrit] New patch to review for coreboot: ecd1c55 superio/fintek/f71869ad: Setup SMBus correctly.
Edward O'Callaghan (eocallaghan@alterapraxis.com)
gerrit at coreboot.org
Sun Mar 23 10:44:37 CET 2014
Edward O'Callaghan (eocallaghan at alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5400
-gerrit
commit ecd1c558558fb08633fb4654313d891da9ee4df7
Author: Edward O'Callaghan <eocallaghan at alterapraxis.com>
Date: Sun Mar 23 20:37:09 2014 +1100
superio/fintek/f71869ad: Setup SMBus correctly.
Fintek superio has "mutli-function selection registers" that need
weaking before the Super I/O will talk to SB.
Change-Id: I28489c183d9d2c379a0488ec5709bbf184ba6853
Signed-off-by: Edward O'Callaghan <eocallaghan at alterapraxis.com>
---
src/superio/fintek/f71869ad/superio.c | 57 ++++++++++++++++++++++++++++++++++-
1 file changed, 56 insertions(+), 1 deletion(-)
diff --git a/src/superio/fintek/f71869ad/superio.c b/src/superio/fintek/f71869ad/superio.c
index c71298c..750ba82 100644
--- a/src/superio/fintek/f71869ad/superio.c
+++ b/src/superio/fintek/f71869ad/superio.c
@@ -28,6 +28,61 @@
#include "chip.h"
#include "f71869ad.h"
+static void toggle_clk_tune_en(device_t dev, int state)
+{
+ u8 reg8;
+
+ reg8 = pnp_read_config(dev, 0x26);
+
+ switch(state) {
+ case 1:
+ reg8 ^= 0x08; /* CLK_TUNE_EN=1 */
+ break;
+ case 0:
+ reg8 &= 0xF7; /* CLK_TUNE_EN=0 */
+ break;
+ }
+
+ pnp_write_config(dev, 0x26, reg8);
+}
+
+static void enable_hwm_smbus(device_t dev)
+{
+ pnp_write_config(dev, 0x25, 0x09); // powerdown FDC & PP
+ pnp_write_config(dev, 0x27, 0xa1); // debug+timing_gpio
+ pnp_write_config(dev, 0x28, 0x01); // multi-func select reg1
+
+ /* CLK_TUNE_EN switch index 0x29 ~ 0x2C to WDT fine tune registers */
+ toggle_clk_tune_en(dev, 1); /* CLK_TUNE_EN=1 */
+ pnp_write_config(dev, 0x29, 0x6f); // WDT clock divisor high byte (CLK_TUNE_EN=1)
+ pnp_write_config(dev, 0x2a, 0x24); // WDT clock divisor low byte (CLK_TUNE_EN=1)
+ pnp_write_config(dev, 0x2b, 0x00); // WDT clock fine tune count (CLK_TUNE_EN=1)
+ pnp_write_config(dev, 0x2b, 0x60); // WDT clock fine tune count (CLK_TUNE_EN=1)
+ /* CLK_TUNE_EN switch index 0x29 ~ 0x2C from WDT fine tune registers */
+ toggle_clk_tune_en(dev, 0); /* CLK_TUNE_EN=0 */
+
+ pnp_write_config(dev, 0x29, 0x6f); // multi-func select reg2 (CLK_TUNE_EN=0)
+ pnp_write_config(dev, 0x2a, 0x24); // multi-func select reg3 (CLK_TUNE_EN=0)
+ pnp_write_config(dev, 0x2b, 0x00); // multi-func select reg4 (CLK_TUNE_EN=0)
+ /* multi-func sel reg5 - Configure pins 57/58 as SCL/SDA (AMD TSI bus). */
+ pnp_write_config(dev, 0x2c, 0x60); // multi-func select reg5 (CLK_TUNE_EN=0)
+ pnp_write_config(dev, 0x2f, 0x2f); // wakeup control register
+}
+
+static void f71869ad_pnp_enable_resources(device_t dev)
+{
+ pnp_enable_resources(dev);
+
+ pnp_enter_conf_mode(dev);
+ switch(dev->path.pnp.device) {
+ case F71869AD_HWM:
+ printk(BIOS_DEBUG, "F71869AD HWM SMBus enabled\n");
+ enable_hwm_smbus(dev);
+ break;
+ }
+ pnp_exit_conf_mode(dev);
+}
+
static void f71869ad_init(device_t dev)
{
struct superio_fintek_f71869ad_config *conf = dev->chip_info;
@@ -49,7 +104,7 @@ static void f71869ad_init(device_t dev)
static struct device_operations ops = {
.read_resources = pnp_read_resources,
.set_resources = pnp_set_resources,
- .enable_resources = pnp_enable_resources,
+ .enable_resources = f71869ad_pnp_enable_resources,
.enable = pnp_alt_enable,
.init = f71869ad_init,
.ops_pnp_mode = &pnp_conf_mode_8787_aa,
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