[coreboot-gerrit] New patch to review for coreboot: 31b31f9 mainboard/jetway/nf81-t56n-lf: Fix GPP missing CLK on PCI bridge.

[Edward O'Callaghan (eocallaghan@alterapraxis.com)]

Edward O'Callaghan (eocallaghan at alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5355

-gerrit

commit 31b31f9680c900286914b5b9168a56c63a2cc8fb
Author: Edward O'Callaghan <eocallaghan at alterapraxis.com>
Date:   Sun Mar 9 17:46:39 2014 +1100

    mainboard/jetway/nf81-t56n-lf: Fix GPP missing CLK on PCI bridge.
    
    The platform dependant mainboard.c was incorrectly disabling the
    second clock signal feeding the GPP ports. This results in
    spurious hangs by calling the set_pcie_dereset() SB CIMx callback
    many times. This also stops CB from finding the second NIC behind
    the pci 15.0 bridge.
    
    Change-Id: I9f2370f6e05d1c5532fbca8203e32ab1ff15266a
    Signed-off-by: Edward O'Callaghan <eocallaghan at alterapraxis.com>
---
 src/mainboard/jetway/nf81-t56n-lf/mainboard.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/jetway/nf81-t56n-lf/mainboard.c b/src/mainboard/jetway/nf81-t56n-lf/mainboard.c
index b17bc6a..97f9417 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/mainboard.c
+++ b/src/mainboard/jetway/nf81-t56n-lf/mainboard.c
@@ -69,7 +69,7 @@ static void mainboard_enable(device_t dev)
 	/* disable GPP CLK2 thru SLT_GFX_CLK */
 	u8 *misc_mem_clk_cntrl = (u8 *)(ACPI_MMIO_BASE + MISC_BASE);
 	*(misc_mem_clk_cntrl + 0) = 0xFF;
-	*(misc_mem_clk_cntrl + 1) = 0x00;
+	*(misc_mem_clk_cntrl + 1) = 0xFF;
 	*(misc_mem_clk_cntrl + 2) = 0x00;
 	*(misc_mem_clk_cntrl + 3) = 0x00;
 	*(misc_mem_clk_cntrl + 4) = 0x00;