[coreboot-gerrit] Patch set updated for coreboot: 6d70a37 src/vendorcode/amd: correct spelling of MTRR
Idwer Vollering (vidwer@gmail.com)
gerrit at coreboot.org
Sat Mar 8 13:15:30 CET 2014
Idwer Vollering (vidwer at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4806
-gerrit
commit 6d70a37f26622969de554647f9de4561ace4491c
Author: Paul Menzel <paulepanter at users.sourceforge.net>
Date: Sat Jan 25 15:59:31 2014 +0100
src/vendorcode/amd: correct spelling of MTRR
Change-Id: I7576591b42fa62da2b3bd74f961fb297b85e250d
Signed-off-by: Paul Menzel <paulepanter at users.sourceforge.net>
Signed-off-by: Idwer Vollering <vidwer at gmail.com>
---
src/vendorcode/amd/agesa/f10/Legacy/Proc/hobTransfer.c | 4 ++--
src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuCacheInit.c | 12 ++++++------
src/vendorcode/amd/agesa/f10/Proc/CPU/cahalt.asm | 2 +-
src/vendorcode/amd/agesa/f10/Proc/CPU/cahalt.c | 2 +-
src/vendorcode/amd/agesa/f10/Proc/CPU/heapManager.c | 2 +-
src/vendorcode/amd/agesa/f10/cpcarmac.inc | 6 +++---
src/vendorcode/amd/agesa/f10/gcccar.inc | 2 +-
src/vendorcode/amd/agesa/f12/Legacy/Proc/hobTransfer.c | 6 +++---
src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuCacheInit.c | 6 +++---
src/vendorcode/amd/agesa/f12/Proc/CPU/cahalt.c | 2 +-
src/vendorcode/amd/agesa/f12/Proc/CPU/heapManager.c | 2 +-
src/vendorcode/amd/agesa/f12/cpcarmac.inc | 2 +-
src/vendorcode/amd/agesa/f12/gcccar.inc | 2 +-
src/vendorcode/amd/agesa/f14/Legacy/Proc/hobTransfer.c | 6 +++---
src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuCacheInit.c | 6 +++---
src/vendorcode/amd/agesa/f14/Proc/CPU/cahalt.asm | 2 +-
src/vendorcode/amd/agesa/f14/Proc/CPU/cahaltasm.S | 2 +-
src/vendorcode/amd/agesa/f14/Proc/CPU/heapManager.c | 2 +-
src/vendorcode/amd/agesa/f14/cpcarmac.inc | 2 +-
src/vendorcode/amd/agesa/f14/gcccar.inc | 2 +-
src/vendorcode/amd/agesa/f15/Legacy/Proc/hobTransfer.c | 6 +++---
src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuCacheInit.c | 6 +++---
src/vendorcode/amd/agesa/f15/Proc/CPU/cahaltasm.S | 2 +-
src/vendorcode/amd/agesa/f15/Proc/CPU/heapManager.c | 2 +-
src/vendorcode/amd/agesa/f15/cpcarmac.inc | 2 +-
src/vendorcode/amd/agesa/f15/gcccar.inc | 2 +-
src/vendorcode/amd/agesa/f15tn/Legacy/Proc/hobTransfer.c | 6 +++---
.../amd/agesa/f15tn/Proc/CPU/Feature/cpuCacheInit.c | 6 +++---
src/vendorcode/amd/agesa/f15tn/Proc/CPU/cahaltasm.S | 2 +-
src/vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.c | 2 +-
src/vendorcode/amd/agesa/f15tn/cpcarmac.inc | 2 +-
src/vendorcode/amd/agesa/f15tn/gcccar.inc | 2 +-
src/vendorcode/amd/agesa/f16kb/Include/Filecode.h | 4 ++--
src/vendorcode/amd/agesa/f16kb/Legacy/Proc/hobTransfer.c | 6 +++---
.../amd/agesa/f16kb/Proc/CPU/Feature/cpuCacheInit.c | 6 +++---
src/vendorcode/amd/agesa/f16kb/Proc/CPU/cahaltasm.S | 2 +-
src/vendorcode/amd/agesa/f16kb/Proc/CPU/heapManager.c | 2 +-
.../amd/agesa/f16kb/Proc/Mem/Tech/mttRdDqs2DEyeRimSearch.c | 2 +-
.../amd/agesa/f16kb/Proc/Mem/Tech/mttRdDqs2DTraining.c | 2 +-
src/vendorcode/amd/agesa/f16kb/gcccar.inc | 2 +-
40 files changed, 69 insertions(+), 69 deletions(-)
diff --git a/src/vendorcode/amd/agesa/f10/Legacy/Proc/hobTransfer.c b/src/vendorcode/amd/agesa/f10/Legacy/Proc/hobTransfer.c
index 1dbe440..3a3be35 100644
--- a/src/vendorcode/amd/agesa/f10/Legacy/Proc/hobTransfer.c
+++ b/src/vendorcode/amd/agesa/f10/Legacy/Proc/hobTransfer.c
@@ -120,7 +120,7 @@ CopyHeapToTempRamAtPost (
//
if (AmdHeapRamAddress < 0x100000) {
// Region below 1MB
- // Fixed MTTR region
+ // Fixed MTRR region
// turn on modification bit
LibAmdMsrRead (MSR_SYS_CFG, &MsrData, StdHeader);
MsrData |= 0x80000;
@@ -151,7 +151,7 @@ CopyHeapToTempRamAtPost (
LibAmdMsrWrite (AMD_MTRR_FIX64k_00000, &MsrData, StdHeader);
}
- // Turn on MTTR enable bit and turn off modification bit
+ // Turn on MTRR enable bit and turn off modification bit
LibAmdMsrRead (MSR_SYS_CFG, &MsrData, StdHeader);
MsrData &= 0xFFFFFFFFFFF7FFFFull;
LibAmdMsrWrite (MSR_SYS_CFG, &MsrData, StdHeader);
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuCacheInit.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuCacheInit.c
index 10f4f5c..87dda2a 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuCacheInit.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuCacheInit.c
@@ -208,7 +208,7 @@ AllocateExecutionCache (
GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader);
FamilySpecificServices->GetCacheInfo (FamilySpecificServices, (CONST VOID **)&CacheInfoPtr, &Ignored, StdHeader);
- // Setup MTTRs for region 0 to region 2
+ // Setup MTRRs for region 0 to region 2
VariableMttrBase = AMD_MTRR_VARIABLE_BASE6;
for (i = 0; i < 3; i++) {
// Exit if no more cache available
@@ -265,7 +265,7 @@ AllocateExecutionCache (
if (StartAddr < 0x100000) {
// Region below 1MB
- // Fixed MTTR region
+ // Fixed MTRR region
if ((StartAddr + ExeCacheSize) > 0xFFFFF) {
ExeCacheSize = 0xFFFFF - StartAddr;
AgesaStatus = AGESA_WARNING;
@@ -276,7 +276,7 @@ AllocateExecutionCache (
i, StartAddr, ExeCacheSize, 0, StdHeader);
}
- // Find start and end of MTTR
+ // Find start and end of MTRR
StartFixMtrr = AMD_MTRR_FIX4K_BASE + ((StartAddr >> 15) & 0x7);
EndFixMtrr = AMD_MTRR_FIX4K_BASE + (((StartAddr + ExeCacheSize) >> 15) & 0x7);
@@ -290,14 +290,14 @@ AllocateExecutionCache (
}
}
- // Setup MTTRs
+ // Setup MTRRs
MsrData = WP_IO;
for (CurrentMtrr = StartFixMtrr; CurrentMtrr <= EndFixMtrr; CurrentMtrr++) {
LibAmdMsrWrite (CurrentMtrr, &MsrData, StdHeader);
}
} else {
// Region above 1MB
- // Variable MTTR region
+ // Variable MTRR region
if (VariableMttrBase > AMD_MTRR_VARIABLE_BASE7) {
AgesaStatus = AGESA_ERROR;
AgesaInfo = AGESA_THREE_CACHE_REGIONS_ABOVE_1MB;
@@ -373,7 +373,7 @@ AllocateExecutionCache (
}
}
- // Turn on MTTR enable bit and turn off modification bit
+ // Turn on MTRR enable bit and turn off modification bit
LibAmdMsrRead (MSR_SYS_CFG, &MsrData, StdHeader);
MsrData &= 0xFFFFFFFFFFF7FFFFull;
LibAmdMsrWrite (MSR_SYS_CFG, &MsrData, StdHeader);
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/cahalt.asm b/src/vendorcode/amd/agesa/f10/Proc/CPU/cahalt.asm
index 0b796c8..e92c945 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/CPU/cahalt.asm
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/cahalt.asm
@@ -147,7 +147,7 @@ EFLoop:
.endw
.endif
- ; restore variable MTTR6 and MTTR7 to default states
+ ; restore variable MTRR6 and MTRR7 to default states
mov ecx, AMD_MTRR_VARIABLE_BASE6 ; clear MTRRPhysBase6 MTRRPhysMask6
xor eax, eax ; and MTRRPhysBase7 MTRRPhysMask7
xor edx, edx
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/cahalt.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/cahalt.c
index 2421bb9..789a6bd 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/CPU/cahalt.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/cahalt.c
@@ -156,7 +156,7 @@ PrimaryCoreFunctions (AP_MTRR_SETTINGS *ApMtrrSettingsList)
__writemsr (ApMtrrSettingsList [index].MsrAddr, ApMtrrSettingsList [index].MsrData);
}
- // restore variable MTTR6 and MTTR7 to default states
+ // restore variable MTRR6 and MTRR7 to default states
for (msrno = 0x20F; msrno <= 0x20C; msrno--) // decrement so that the pair is disable before the base is cleared
__writemsr (msrno, 0);
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/heapManager.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/heapManager.c
index b5be972..aa79b16 100644
--- a/src/vendorcode/amd/agesa/f10/Proc/CPU/heapManager.c
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/heapManager.c
@@ -153,7 +153,7 @@ HeapManagerInit (
MsrData = (UINT64) (AMD_TEMP_TOM);
LibAmdMsrWrite (TOP_MEM, &MsrData, StdHeader);
- // Enable variable MTTRs
+ // Enable variable MTRRs
LibAmdMsrRead (SYS_CFG, &MsrData, StdHeader);
MsrData |= AMD_VAR_MTRR_ENABLE_BIT;
LibAmdMsrWrite (SYS_CFG, &MsrData, StdHeader);
diff --git a/src/vendorcode/amd/agesa/f10/cpcarmac.inc b/src/vendorcode/amd/agesa/f10/cpcarmac.inc
index f7119d1..e893d1e 100644
--- a/src/vendorcode/amd/agesa/f10/cpcarmac.inc
+++ b/src/vendorcode/amd/agesa/f10/cpcarmac.inc
@@ -187,7 +187,7 @@ SetupDramMap:
inc cl
.endw
- ; setup MTTR for stacks
+ ; setup MTRR for stacks
mov ebx, WB_DRAM_TYPE
.if (di == 0) ;core 0
.if (si > 3) ; node 0 to 3 located at 40000h, node 4 to 7 located at 50000h
@@ -198,7 +198,7 @@ SetupDramMap:
or edx, ebx
_WRMSR
.else ;core 1 to core 7 start at 60000h
- .if (si < 4) ; node 0 to 3 using AMD_MTRR_FIX64K_6000 and AMD_MTRR_FIX64K_7000 MTTR
+ .if (si < 4) ; node 0 to 3 using AMD_MTRR_FIX64K_6000 and AMD_MTRR_FIX64K_7000 MTRR
shl ebx, 16
.if (si > 1)
shl ebx, 8
@@ -207,7 +207,7 @@ SetupDramMap:
_RDMSR
or edx, ebx
_WRMSR
- .else ; node 4 to 7 uses AMD_MTRR_FIX16K_80000 and AMD_MTRR_FIX16K_9000 MTTR
+ .else ; node 4 to 7 uses AMD_MTRR_FIX16K_80000 and AMD_MTRR_FIX16K_9000 MTRR
mov ecx, AMD_MTRR_FIX16k_80000
_RDMSR
.if (si < 6) ; node 4 and node 5
diff --git a/src/vendorcode/amd/agesa/f10/gcccar.inc b/src/vendorcode/amd/agesa/f10/gcccar.inc
index 11f50db..62957e4 100644
--- a/src/vendorcode/amd/agesa/f10/gcccar.inc
+++ b/src/vendorcode/amd/agesa/f10/gcccar.inc
@@ -1353,7 +1353,7 @@ SetupStack:
mov $TOP_MEM2, %ecx # MSR:C001_001D
_WRMSR
- # setup MTTRs for stacks
+ # setup MTRRs for stacks
# A speculative read can be generated by a speculative fetch mis-aligned in a code zone
# or due to a data zone being interpreted as code. When a speculative read occurs outside a
# controlled region (intentionally used by software), it could cause an unwanted cache eviction.
diff --git a/src/vendorcode/amd/agesa/f12/Legacy/Proc/hobTransfer.c b/src/vendorcode/amd/agesa/f12/Legacy/Proc/hobTransfer.c
index bf8e6d2..eac7c2a 100644
--- a/src/vendorcode/amd/agesa/f12/Legacy/Proc/hobTransfer.c
+++ b/src/vendorcode/amd/agesa/f12/Legacy/Proc/hobTransfer.c
@@ -137,7 +137,7 @@ CopyHeapToTempRamAtPost (
//
if (AmdHeapRamAddress < 0x100000) {
// Region below 1MB
- // Fixed MTTR region
+ // Fixed MTRR region
// turn on modification bit
LibAmdMsrRead (MSR_SYS_CFG, &MsrData, StdHeader);
MsrData |= 0x80000;
@@ -168,14 +168,14 @@ CopyHeapToTempRamAtPost (
LibAmdMsrWrite (AMD_MTRR_FIX64k_00000, &MsrData, StdHeader);
}
- // Turn on MTTR enable bit and turn off modification bit
+ // Turn on MTRR enable bit and turn off modification bit
LibAmdMsrRead (MSR_SYS_CFG, &MsrData, StdHeader);
MsrData |= 0x40000;
MsrData &= 0xFFFFFFFFFFF7FFFFull;
LibAmdMsrWrite (MSR_SYS_CFG, &MsrData, StdHeader);
} else {
// Region above 1MB
- // Variable MTTR region
+ // Variable MTRR region
// Get family specific cache Info
GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
FamilySpecificServices->GetCacheInfo (FamilySpecificServices, (const VOID **) &CacheInfoPtr, &Ignored, StdHeader);
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuCacheInit.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuCacheInit.c
index fbc1b5e..d84e689 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuCacheInit.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuCacheInit.c
@@ -281,7 +281,7 @@ AllocateExecutionCache (
RequestSize = AmdExeAddrMapPtr[i].ExeCacheSize;
if (RequestStartAddr < 0x100000) {
- // Region starts below 1MB - Fixed MTTR region,
+ // Region starts below 1MB - Fixed MTRR region,
// turn on modification bit: MtrrFixDramModEn
LibAmdMsrRead (MSR_SYS_CFG, &MsrData, StdHeader);
MsrData |= 0x80000;
@@ -299,7 +299,7 @@ AllocateExecutionCache (
i, RequestStartAddr, RequestSize, 0, StdHeader);
}
- // Find start MTTR and end MTTR for the requested region
+ // Find start MTRR and end MTRR for the requested region
StartFixMtrr = AMD_MTRR_FIX4K_BASE + ((RequestStartAddr >> 15) & 0x7);
EndFixMtrr = AMD_MTRR_FIX4K_BASE + ((((RequestStartAddr + RequestSize) - 1) >> 15) & 0x7);
@@ -325,7 +325,7 @@ AllocateExecutionCache (
} else {
- // Region above 1MB - Variable MTTR region
+ // Region above 1MB - Variable MTRR region
// Need to check both VarMTRRs for each requested region for match or overlap
//
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/cahalt.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/cahalt.c
index 1bad891..57483a9 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/cahalt.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/cahalt.c
@@ -148,7 +148,7 @@ PrimaryCoreFunctions (AP_MTRR_SETTINGS *ApMtrrSettingsList)
__writemsr (ApMtrrSettingsList [index].MsrAddr, ApMtrrSettingsList [index].MsrData);
}
- // restore variable MTTR6 and MTTR7 to default states
+ // restore variable MTRR6 and MTRR7 to default states
for (msrno = 0x20F; msrno <= 0x20C; msrno--) // decrement so that the pair is disable before the base is cleared
__writemsr (msrno, 0);
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/heapManager.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/heapManager.c
index dacaded..e9e41cb 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/heapManager.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/heapManager.c
@@ -188,7 +188,7 @@ HeapManagerInit (
MsrData = (UINT64) (AMD_TEMP_TOM);
LibAmdMsrWrite (TOP_MEM, &MsrData, StdHeader);
- // Enable variable MTTRs
+ // Enable variable MTRRs
LibAmdMsrRead (SYS_CFG, &MsrData, StdHeader);
MsrData |= AMD_VAR_MTRR_ENABLE_BIT;
LibAmdMsrWrite (SYS_CFG, &MsrData, StdHeader);
diff --git a/src/vendorcode/amd/agesa/f12/cpcarmac.inc b/src/vendorcode/amd/agesa/f12/cpcarmac.inc
index b4add85..5bd41d0 100644
--- a/src/vendorcode/amd/agesa/f12/cpcarmac.inc
+++ b/src/vendorcode/amd/agesa/f12/cpcarmac.inc
@@ -220,7 +220,7 @@ AMD_ENABLE_STACK MACRO
mov ecx, TOP_MEM2 ; MSR:C001_001D
_WRMSR
- ; setup MTTRs for stacks
+ ; setup MTRRs for stacks
; A speculative read can be generated by a speculative fetch mis-aligned in a code zone
; or due to a data zone being interpreted as code. When a speculative read occurs outside a
; controlled region (intentionally used by software), it could cause an unwanted cache eviction.
diff --git a/src/vendorcode/amd/agesa/f12/gcccar.inc b/src/vendorcode/amd/agesa/f12/gcccar.inc
index 22564cb..3b360a4 100644
--- a/src/vendorcode/amd/agesa/f12/gcccar.inc
+++ b/src/vendorcode/amd/agesa/f12/gcccar.inc
@@ -1347,7 +1347,7 @@ SetupStack:
mov $TOP_MEM2, %ecx # MSR:C001_001D
_WRMSR
- # setup MTTRs for stacks
+ # setup MTRRs for stacks
# A speculative read can be generated by a speculative fetch mis-aligned in a code zone
# or due to a data zone being interpreted as code. When a speculative read occurs outside a
# controlled region (intentionally used by software), it could cause an unwanted cache eviction.
diff --git a/src/vendorcode/amd/agesa/f14/Legacy/Proc/hobTransfer.c b/src/vendorcode/amd/agesa/f14/Legacy/Proc/hobTransfer.c
index bb23204..3e97fe6 100644
--- a/src/vendorcode/amd/agesa/f14/Legacy/Proc/hobTransfer.c
+++ b/src/vendorcode/amd/agesa/f14/Legacy/Proc/hobTransfer.c
@@ -140,7 +140,7 @@ CopyHeapToTempRamAtPost (
//
if (AmdHeapRamAddress < 0x100000) {
// Region below 1MB
- // Fixed MTTR region
+ // Fixed MTRR region
// turn on modification bit
LibAmdMsrRead (MSR_SYS_CFG, &MsrData, StdHeader);
MsrData |= 0x80000;
@@ -171,14 +171,14 @@ CopyHeapToTempRamAtPost (
LibAmdMsrWrite (AMD_MTRR_FIX64k_00000, &MsrData, StdHeader);
}
- // Turn on MTTR enable bit and turn off modification bit
+ // Turn on MTRR enable bit and turn off modification bit
LibAmdMsrRead (MSR_SYS_CFG, &MsrData, StdHeader);
MsrData |= 0x40000;
MsrData &= 0xFFFFFFFFFFF7FFFF;
LibAmdMsrWrite (MSR_SYS_CFG, &MsrData, StdHeader);
} else {
// Region above 1MB
- // Variable MTTR region
+ // Variable MTRR region
// Get family specific cache Info
GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
FamilySpecificServices->GetCacheInfo (FamilySpecificServices, (const VOID **)&CacheInfoPtr, &Ignored, StdHeader);
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuCacheInit.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuCacheInit.c
index 6d06745..dbe4717 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuCacheInit.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuCacheInit.c
@@ -280,7 +280,7 @@ AllocateExecutionCache (
RequestSize = AmdExeAddrMapPtr[i].ExeCacheSize;
if (RequestStartAddr < 0x100000) {
- // Region starts below 1MB - Fixed MTTR region,
+ // Region starts below 1MB - Fixed MTRR region,
// turn on modification bit: MtrrFixDramModEn
LibAmdMsrRead (MSR_SYS_CFG, &MsrData, StdHeader);
MsrData |= 0x80000;
@@ -298,7 +298,7 @@ AllocateExecutionCache (
i, RequestStartAddr, RequestSize, 0, StdHeader);
}
- // Find start MTTR and end MTTR for the requested region
+ // Find start MTRR and end MTRR for the requested region
StartFixMtrr = AMD_MTRR_FIX4K_BASE + ((RequestStartAddr >> 15) & 0x7);
EndFixMtrr = AMD_MTRR_FIX4K_BASE + ((((RequestStartAddr + RequestSize) - 1) >> 15) & 0x7);
@@ -324,7 +324,7 @@ AllocateExecutionCache (
} else {
- // Region above 1MB - Variable MTTR region
+ // Region above 1MB - Variable MTRR region
// Need to check both VarMTRRs for each requested region for match or overlap
//
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/cahalt.asm b/src/vendorcode/amd/agesa/f14/Proc/CPU/cahalt.asm
index 3ffe146..de5201d 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/cahalt.asm
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/cahalt.asm
@@ -173,7 +173,7 @@ EFLoop:
.endw
.endif
- ; restore variable MTTR6 and MTTR7 to default states
+ ; restore variable MTRR6 and MTRR7 to default states
mov ecx, AMD_MTRR_VARIABLE_BASE6 ; clear MTRRPhysBase6 MTRRPhysMask6
xor eax, eax ; and MTRRPhysBase7 MTRRPhysMask7
xor edx, edx
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/cahaltasm.S b/src/vendorcode/amd/agesa/f14/Proc/CPU/cahaltasm.S
index 48ee5d0..137261c 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/cahaltasm.S
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/cahaltasm.S
@@ -157,7 +157,7 @@ EFLoop:
jmp 5b /* .endw */
4: /* .endif */
- /* restore variable MTTR6 and MTTR7 to default states */
+ /* restore variable MTRR6 and MTRR7 to default states */
movl $AMD_MTRR_VARIABLE_BASE6, %ecx /* clear MTRRPhysBase6 MTRRPhysMask6 */
xor %eax, %eax /* and MTRRPhysBase7 MTRRPhysMask7 */
xor %edx, %edx
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/heapManager.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/heapManager.c
index f6b409f..0e4bce9 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/heapManager.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/heapManager.c
@@ -192,7 +192,7 @@ HeapManagerInit (
MsrData = (UINT64) (AMD_TEMP_TOM);
LibAmdMsrWrite (TOP_MEM, &MsrData, StdHeader);
- // Enable variable MTTRs
+ // Enable variable MTRRs
LibAmdMsrRead (SYS_CFG, &MsrData, StdHeader);
MsrData |= AMD_VAR_MTRR_ENABLE_BIT;
LibAmdMsrWrite (SYS_CFG, &MsrData, StdHeader);
diff --git a/src/vendorcode/amd/agesa/f14/cpcarmac.inc b/src/vendorcode/amd/agesa/f14/cpcarmac.inc
index b703b7f..54e7f95 100644
--- a/src/vendorcode/amd/agesa/f14/cpcarmac.inc
+++ b/src/vendorcode/amd/agesa/f14/cpcarmac.inc
@@ -215,7 +215,7 @@ AMD_ENABLE_STACK MACRO
mov ecx, TOP_MEM2 ; MSR:C001_001D
_WRMSR
- ; setup MTTRs for stacks
+ ; setup MTRRs for stacks
; A speculative read can be generated by a speculative fetch mis-aligned in a code zone
; or due to a data zone being interpreted as code. When a speculative read occurs outside a
; controlled region (intentionally used by software), it could cause an unwanted cache eviction.
diff --git a/src/vendorcode/amd/agesa/f14/gcccar.inc b/src/vendorcode/amd/agesa/f14/gcccar.inc
index 40e0e31..5088008 100644
--- a/src/vendorcode/amd/agesa/f14/gcccar.inc
+++ b/src/vendorcode/amd/agesa/f14/gcccar.inc
@@ -1361,7 +1361,7 @@ SetupStack:
mov $TOP_MEM2, %ecx # MSR:C001_001D
_WRMSR
- # setup MTTRs for stacks
+ # setup MTRRs for stacks
# A speculative read can be generated by a speculative fetch mis-aligned in a code zone
# or due to a data zone being interpreted as code. When a speculative read occurs outside a
# controlled region (intentionally used by software), it could cause an unwanted cache eviction.
diff --git a/src/vendorcode/amd/agesa/f15/Legacy/Proc/hobTransfer.c b/src/vendorcode/amd/agesa/f15/Legacy/Proc/hobTransfer.c
index b2accb2..3eb908e 100644
--- a/src/vendorcode/amd/agesa/f15/Legacy/Proc/hobTransfer.c
+++ b/src/vendorcode/amd/agesa/f15/Legacy/Proc/hobTransfer.c
@@ -138,7 +138,7 @@ CopyHeapToTempRamAtPost (
//
if (AmdHeapRamAddress < 0x100000) {
// Region below 1MB
- // Fixed MTTR region
+ // Fixed MTRR region
// turn on modification bit
LibAmdMsrRead (MSR_SYS_CFG, &MsrData, StdHeader);
MsrData |= 0x80000;
@@ -169,14 +169,14 @@ CopyHeapToTempRamAtPost (
LibAmdMsrWrite (AMD_MTRR_FIX64k_00000, &MsrData, StdHeader);
}
- // Turn on MTTR enable bit and turn off modification bit
+ // Turn on MTRR enable bit and turn off modification bit
LibAmdMsrRead (MSR_SYS_CFG, &MsrData, StdHeader);
MsrData |= 0x40000;
MsrData &= 0xFFFFFFFFFFF7FFFF;
LibAmdMsrWrite (MSR_SYS_CFG, &MsrData, StdHeader);
} else {
// Region above 1MB
- // Variable MTTR region
+ // Variable MTRR region
// Get family specific cache Info
GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
FamilySpecificServices->GetCacheInfo (FamilySpecificServices, (CONST VOID **) &CacheInfoPtr, &Ignored, StdHeader);
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuCacheInit.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuCacheInit.c
index ca60b2b..274844b 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuCacheInit.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuCacheInit.c
@@ -282,7 +282,7 @@ AllocateExecutionCache (
RequestSize = AmdExeAddrMapPtr[i].ExeCacheSize;
if (RequestStartAddr < 0x100000) {
- // Region starts below 1MB - Fixed MTTR region,
+ // Region starts below 1MB - Fixed MTRR region,
// turn on modification bit: MtrrFixDramModEn
LibAmdMsrRead (MSR_SYS_CFG, &MsrData, StdHeader);
MsrData |= 0x80000;
@@ -300,7 +300,7 @@ AllocateExecutionCache (
i, RequestStartAddr, RequestSize, 0, StdHeader);
}
- // Find start MTTR and end MTTR for the requested region
+ // Find start MTRR and end MTRR for the requested region
StartFixMtrr = AMD_MTRR_FIX4K_BASE + ((RequestStartAddr >> 15) & 0x7);
EndFixMtrr = AMD_MTRR_FIX4K_BASE + ((((RequestStartAddr + RequestSize) - 1) >> 15) & 0x7);
@@ -326,7 +326,7 @@ AllocateExecutionCache (
} else {
- // Region above 1MB - Variable MTTR region
+ // Region above 1MB - Variable MTRR region
// Need to check both VarMTRRs for each requested region for match or overlap
//
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/cahaltasm.S b/src/vendorcode/amd/agesa/f15/Proc/CPU/cahaltasm.S
index 221805a..012c4f7 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/cahaltasm.S
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/cahaltasm.S
@@ -187,7 +187,7 @@ EFLoop:
AMD_DISABLE_STACK_FAMILY_HOOK
- /* restore variable MTTR6 and MTTR7 to default states */
+ /* restore variable MTRR6 and MTRR7 to default states */
bt $FLAG_IS_PRIMARY, %esi /* .if (esi & 1h) */
jz 6f
movl $AMD_MTRR_VARIABLE_MASK7, %ecx /* clear MTRRPhysBase6 MTRRPhysMask6 */
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/heapManager.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/heapManager.c
index f42c35d..e1fc324 100644
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/heapManager.c
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/heapManager.c
@@ -189,7 +189,7 @@ HeapManagerInit (
MsrData = (UINT64) (AMD_TEMP_TOM);
LibAmdMsrWrite (TOP_MEM, &MsrData, StdHeader);
- // Enable variable MTTRs
+ // Enable variable MTRRs
LibAmdMsrRead (SYS_CFG, &MsrData, StdHeader);
MsrData |= AMD_VAR_MTRR_ENABLE_BIT;
LibAmdMsrWrite (SYS_CFG, &MsrData, StdHeader);
diff --git a/src/vendorcode/amd/agesa/f15/cpcarmac.inc b/src/vendorcode/amd/agesa/f15/cpcarmac.inc
index 24a6073..8947491 100644
--- a/src/vendorcode/amd/agesa/f15/cpcarmac.inc
+++ b/src/vendorcode/amd/agesa/f15/cpcarmac.inc
@@ -221,7 +221,7 @@ AMD_ENABLE_STACK MACRO
mov ecx, TOP_MEM2 ; MSR:C001_001D
_WRMSR
- ; setup MTTRs for stacks
+ ; setup MTRRs for stacks
; A speculative read can be generated by a speculative fetch mis-aligned in a code zone
; or due to a data zone being interpreted as code. When a speculative read occurs outside a
; controlled region (intentionally used by software), it could cause an unwanted cache eviction.
diff --git a/src/vendorcode/amd/agesa/f15/gcccar.inc b/src/vendorcode/amd/agesa/f15/gcccar.inc
index c88709c..521851e 100644
--- a/src/vendorcode/amd/agesa/f15/gcccar.inc
+++ b/src/vendorcode/amd/agesa/f15/gcccar.inc
@@ -1368,7 +1368,7 @@ SetupStack:
mov $TOP_MEM2, %ecx # MSR:C001_001D
_WRMSR
- # setup MTTRs for stacks
+ # setup MTRRs for stacks
# A speculative read can be generated by a speculative fetch mis-aligned in a code zone
# or due to a data zone being interpreted as code. When a speculative read occurs outside a
# controlled region (intentionally used by software), it could cause an unwanted cache eviction.
diff --git a/src/vendorcode/amd/agesa/f15tn/Legacy/Proc/hobTransfer.c b/src/vendorcode/amd/agesa/f15tn/Legacy/Proc/hobTransfer.c
index 7ed5f16..9f5243f 100644
--- a/src/vendorcode/amd/agesa/f15tn/Legacy/Proc/hobTransfer.c
+++ b/src/vendorcode/amd/agesa/f15tn/Legacy/Proc/hobTransfer.c
@@ -137,7 +137,7 @@ CopyHeapToTempRamAtPost (
//
if (AmdHeapRamAddress < 0x100000) {
// Region below 1MB
- // Fixed MTTR region
+ // Fixed MTRR region
// turn on modification bit
LibAmdMsrRead (MSR_SYS_CFG, &MsrData, StdHeader);
MsrData |= 0x80000;
@@ -168,14 +168,14 @@ CopyHeapToTempRamAtPost (
LibAmdMsrWrite (AMD_MTRR_FIX64k_00000, &MsrData, StdHeader);
}
- // Turn on MTTR enable bit and turn off modification bit
+ // Turn on MTRR enable bit and turn off modification bit
LibAmdMsrRead (MSR_SYS_CFG, &MsrData, StdHeader);
MsrData |= 0x40000;
MsrData &= 0xFFFFFFFFFFF7FFFF;
LibAmdMsrWrite (MSR_SYS_CFG, &MsrData, StdHeader);
} else {
// Region above 1MB
- // Variable MTTR region
+ // Variable MTRR region
// Get family specific cache Info
GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
FamilySpecificServices->GetCacheInfo (FamilySpecificServices, (CONST VOID **) &CacheInfoPtr, &Ignored, StdHeader);
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuCacheInit.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuCacheInit.c
index fcd7bf4..e9c8922 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuCacheInit.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuCacheInit.c
@@ -281,7 +281,7 @@ AllocateExecutionCache (
RequestSize = AmdExeAddrMapPtr[i].ExeCacheSize;
if (RequestStartAddr < 0x100000) {
- // Region starts below 1MB - Fixed MTTR region,
+ // Region starts below 1MB - Fixed MTRR region,
// turn on modification bit: MtrrFixDramModEn
LibAmdMsrRead (MSR_SYS_CFG, &MsrData, StdHeader);
MsrData |= 0x80000;
@@ -299,7 +299,7 @@ AllocateExecutionCache (
i, RequestStartAddr, RequestSize, 0, StdHeader);
}
- // Find start MTTR and end MTTR for the requested region
+ // Find start MTRR and end MTRR for the requested region
StartFixMtrr = AMD_MTRR_FIX4K_BASE + ((RequestStartAddr >> 15) & 0x7);
EndFixMtrr = AMD_MTRR_FIX4K_BASE + ((((RequestStartAddr + RequestSize) - 1) >> 15) & 0x7);
@@ -325,7 +325,7 @@ AllocateExecutionCache (
} else {
- // Region above 1MB - Variable MTTR region
+ // Region above 1MB - Variable MTRR region
// Need to check both VarMTRRs for each requested region for match or overlap
//
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cahaltasm.S b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cahaltasm.S
index 4ab535a..c1e7ab7 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cahaltasm.S
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cahaltasm.S
@@ -187,7 +187,7 @@ EFLoop:
AMD_DISABLE_STACK_FAMILY_HOOK
- /* restore variable MTTR6 and MTTR7 to default states */
+ /* restore variable MTRR6 and MTRR7 to default states */
bt $FLAG_IS_PRIMARY, %esi /* .if (esi & 1h) */
jz 6f
movl $AMD_MTRR_VARIABLE_MASK7, %ecx /* clear MTRRPhysBase6 MTRRPhysMask6 */
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.c
index 2e45471..fdf2581 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.c
@@ -188,7 +188,7 @@ HeapManagerInit (
MsrData = (UINT64) (AMD_TEMP_TOM);
LibAmdMsrWrite (TOP_MEM, &MsrData, StdHeader);
- // Enable variable MTTRs
+ // Enable variable MTRRs
LibAmdMsrRead (SYS_CFG, &MsrData, StdHeader);
MsrData |= AMD_VAR_MTRR_ENABLE_BIT;
LibAmdMsrWrite (SYS_CFG, &MsrData, StdHeader);
diff --git a/src/vendorcode/amd/agesa/f15tn/cpcarmac.inc b/src/vendorcode/amd/agesa/f15tn/cpcarmac.inc
index 98c7696..19044bd 100644
--- a/src/vendorcode/amd/agesa/f15tn/cpcarmac.inc
+++ b/src/vendorcode/amd/agesa/f15tn/cpcarmac.inc
@@ -220,7 +220,7 @@ AMD_ENABLE_STACK MACRO
mov ecx, TOP_MEM2 ; MSR:C001_001D
_WRMSR
- ; setup MTTRs for stacks
+ ; setup MTRRs for stacks
; A speculative read can be generated by a speculative fetch mis-aligned in a code zone
; or due to a data zone being interpreted as code. When a speculative read occurs outside a
; controlled region (intentionally used by software), it could cause an unwanted cache eviction.
diff --git a/src/vendorcode/amd/agesa/f15tn/gcccar.inc b/src/vendorcode/amd/agesa/f15tn/gcccar.inc
index d6dd49a..ba04027 100644
--- a/src/vendorcode/amd/agesa/f15tn/gcccar.inc
+++ b/src/vendorcode/amd/agesa/f15tn/gcccar.inc
@@ -1677,7 +1677,7 @@ SetupStack:
mov $TOP_MEM2, %ecx # MSR:C001_001D
_WRMSR
- # setup MTTRs for stacks
+ # setup MTRRs for stacks
# A speculative read can be generated by a speculative fetch mis-aligned in a code zone
# or due to a data zone being interpreted as code. When a speculative read occurs outside a
# controlled region (intentionally used by software), it could cause an unwanted cache eviction.
diff --git a/src/vendorcode/amd/agesa/f16kb/Include/Filecode.h b/src/vendorcode/amd/agesa/f16kb/Include/Filecode.h
index a3b3472..dcec443 100644
--- a/src/vendorcode/amd/agesa/f16kb/Include/Filecode.h
+++ b/src/vendorcode/amd/agesa/f16kb/Include/Filecode.h
@@ -575,7 +575,7 @@
#define PROC_MEM_TECH_DDR3_MTTECC3_FILECODE (0XF588)
#define PROC_MEM_TECH_DDR3_MTLRDIMM3_FILECODE (0XF589)
#define PROC_MEM_TECH_MTTHRCSEEDTRAIN_FILECODE (0XF58A)
-#define PROC_MEM_TECH_MTTRDDQS2DTRAINING_FILECODE (0XF58B)
-#define PROC_MEM_TECH_MTTRDDQS2DEYERIMSEARCH_FILECODE (0XF58C)
+#define PROC_MEM_TECH_MTRRDDQS2DTRAINING_FILECODE (0XF58B)
+#define PROC_MEM_TECH_MTRRDDQS2DEYERIMSEARCH_FILECODE (0XF58C)
#endif // _FILECODE_H_
diff --git a/src/vendorcode/amd/agesa/f16kb/Legacy/Proc/hobTransfer.c b/src/vendorcode/amd/agesa/f16kb/Legacy/Proc/hobTransfer.c
index 7f03e13..a795b2e 100644
--- a/src/vendorcode/amd/agesa/f16kb/Legacy/Proc/hobTransfer.c
+++ b/src/vendorcode/amd/agesa/f16kb/Legacy/Proc/hobTransfer.c
@@ -141,7 +141,7 @@ CopyHeapToTempRamAtPost (
//
if (AmdHeapRamAddress < 0x100000) {
// Region below 1MB
- // Fixed MTTR region
+ // Fixed MTRR region
// turn on modification bit
LibAmdMsrRead (MSR_SYS_CFG, &MsrData, StdHeader);
MsrData |= 0x80000;
@@ -172,14 +172,14 @@ CopyHeapToTempRamAtPost (
LibAmdMsrWrite (AMD_MTRR_FIX64k_00000, &MsrData, StdHeader);
}
- // Turn on MTTR enable bit and turn off modification bit
+ // Turn on MTRR enable bit and turn off modification bit
LibAmdMsrRead (MSR_SYS_CFG, &MsrData, StdHeader);
MsrData |= 0x40000;
MsrData &= 0xFFFFFFFFFFF7FFFF;
LibAmdMsrWrite (MSR_SYS_CFG, &MsrData, StdHeader);
} else {
// Region above 1MB
- // Variable MTTR region
+ // Variable MTRR region
// Get family specific cache Info
GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
FamilySpecificServices->GetCacheInfo (FamilySpecificServices, (CONST VOID **) &CacheInfoPtr, &Ignored, StdHeader);
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuCacheInit.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuCacheInit.c
index b5a38b8..d8243ad 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuCacheInit.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuCacheInit.c
@@ -281,7 +281,7 @@ AllocateExecutionCache (
RequestSize = AmdExeAddrMapPtr[i].ExeCacheSize;
if (RequestStartAddr < 0x100000) {
- // Region starts below 1MB - Fixed MTTR region,
+ // Region starts below 1MB - Fixed MTRR region,
// turn on modification bit: MtrrFixDramModEn
LibAmdMsrRead (MSR_SYS_CFG, &MsrData, StdHeader);
MsrData |= 0x80000;
@@ -299,7 +299,7 @@ AllocateExecutionCache (
i, RequestStartAddr, RequestSize, 0, StdHeader);
}
- // Find start MTTR and end MTTR for the requested region
+ // Find start MTRR and end MTRR for the requested region
StartFixMtrr = AMD_MTRR_FIX4K_BASE + ((RequestStartAddr >> 15) & 0x7);
EndFixMtrr = AMD_MTRR_FIX4K_BASE + ((((RequestStartAddr + RequestSize) - 1) >> 15) & 0x7);
@@ -325,7 +325,7 @@ AllocateExecutionCache (
} else {
- // Region above 1MB - Variable MTTR region
+ // Region above 1MB - Variable MTRR region
// Need to check both VarMTRRs for each requested region for match or overlap
//
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cahaltasm.S b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cahaltasm.S
index 97f6f16..5803c26 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cahaltasm.S
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cahaltasm.S
@@ -179,7 +179,7 @@ EFLoop:
AMD_DISABLE_STACK_FAMILY_HOOK
- /* restore variable MTTR6 and MTTR7 to default states */
+ /* restore variable MTRR6 and MTRR7 to default states */
bt $FLAG_IS_PRIMARY, %esi /* .if (esi & 1h) */
jz 6f
movl $AMD_MTRR_VARIABLE_MASK7, %ecx /* clear MTRRPhysBase6 MTRRPhysMask6 */
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/heapManager.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/heapManager.c
index 42a6afa..3f3dbda 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/heapManager.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/heapManager.c
@@ -191,7 +191,7 @@ HeapManagerInit (
MsrData = (UINT64) (AMD_TEMP_TOM);
LibAmdMsrWrite (TOP_MEM, &MsrData, StdHeader);
- // Enable variable MTTRs
+ // Enable variable MTRRs
LibAmdMsrRead (SYS_CFG, &MsrData, StdHeader);
MsrData |= AMD_VAR_MTRR_ENABLE_BIT;
LibAmdMsrWrite (SYS_CFG, &MsrData, StdHeader);
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mttRdDqs2DEyeRimSearch.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mttRdDqs2DEyeRimSearch.c
index a568f9e..832e807 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mttRdDqs2DEyeRimSearch.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mttRdDqs2DEyeRimSearch.c
@@ -64,7 +64,7 @@
CODE_GROUP (G1_PEICC)
RDATA_GROUP (G1_PEICC)
-#define FILECODE PROC_MEM_TECH_MTTRDDQS2DEYERIMSEARCH_FILECODE
+#define FILECODE PROC_MEM_TECH_MTRRDDQS2DEYERIMSEARCH_FILECODE
/*----------------------------------------------------------------------------
* DEFINITIONS AND MACROS
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mttRdDqs2DTraining.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mttRdDqs2DTraining.c
index 0fc13f9..08c7730 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mttRdDqs2DTraining.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mttRdDqs2DTraining.c
@@ -70,7 +70,7 @@
CODE_GROUP (G1_PEICC)
RDATA_GROUP (G1_PEICC)
-#define FILECODE PROC_MEM_TECH_MTTRDDQS2DTRAINING_FILECODE
+#define FILECODE PROC_MEM_TECH_MTRRDDQS2DTRAINING_FILECODE
/*----------------------------------------------------------------------------
* DEFINITIONS AND MACROS
*
diff --git a/src/vendorcode/amd/agesa/f16kb/gcccar.inc b/src/vendorcode/amd/agesa/f16kb/gcccar.inc
index 90c8cc6..357ad89 100644
--- a/src/vendorcode/amd/agesa/f16kb/gcccar.inc
+++ b/src/vendorcode/amd/agesa/f16kb/gcccar.inc
@@ -1042,7 +1042,7 @@ SetupStack:
mov $TOP_MEM2, %ecx # MSR:C001_001D
_WRMSR
- # setup MTTRs for stacks
+ # setup MTRRs for stacks
# A speculative read can be generated by a speculative fetch mis-aligned in a code zone
# or due to a data zone being interpreted as code. When a speculative read occurs outside a
# controlled region (intentionally used by software), it could cause an unwanted cache eviction.
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