[coreboot-gerrit] Patch set updated for coreboot: 552b86f rambi: Enable USB boot with EHCI controller

[Aaron Durbin (adurbin@google.com)]

Aaron Durbin (adurbin at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4931

-gerrit

commit 552b86ff407c2208640f11918694dbef7bbf2e7d
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Fri Nov 1 13:35:32 2013 -0700

    rambi: Enable USB boot with EHCI controller
    
    This adds the EHCI driver back to libpayload and configures
    the devicetree to route ports to EHCI.
    
    This is hopefully just temporary until the issues with XHCI
    can be worked out.
    
    BUG=chrome-os-partner:23635
    BRANCH=rambi
    TEST=build and boot from USB on rambi
    
    Change-Id: I0549661f5e5fd83477f4839a05e7e21175b24b64
    Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/175513
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 src/mainboard/google/rambi/devicetree.cb | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/src/mainboard/google/rambi/devicetree.cb b/src/mainboard/google/rambi/devicetree.cb
index 66d98ed..af115a6 100644
--- a/src/mainboard/google/rambi/devicetree.cb
+++ b/src/mainboard/google/rambi/devicetree.cb
@@ -5,6 +5,24 @@ chip soc/intel/baytrail
 	register "sata_ahci" = "0x1"
 	register "ide_legacy_combined" = "0x0"
 
+	# Route USB ports to XHCI -- DISABLED UNTIL XHCI WORKS
+	register "usb_route_to_xhci" = "0"
+
+	# USB Port Disable Mask
+	register "usb2_port_disable_mask" = "0x0"
+	register "usb3_port_disable_mask" = "0x0"
+
+	# USB PHY settings
+	# TODO: These values are from Baytrail and need tuned for Rambi board
+	register "usb2_per_port_lane0" = "0x00049a09"
+	register "usb2_per_port_rcomp_hs_pullup0" = "0x0300401d"
+	register "usb2_per_port_lane1" = "0x00049a09"
+	register "usb2_per_port_rcomp_hs_pullup1" = "0x0300401d"
+	register "usb2_per_port_lane2" = "0x00049209"
+	register "usb2_per_port_rcomp_hs_pullup2" = "0x01004015"
+	register "usb2_per_port_lane3" = "0x00049a09"
+	register "usb2_per_port_rcomp_hs_pullup3" = "0x0300401d"
+
 	device cpu_cluster 0 on
 		device lapic 0 on end
 	end