[coreboot-gerrit] Patch set updated for coreboot: a032be4 northbridge/amd/{gx2, lx}/raminit.c: Initialise `spd_byte`

[Edward O'Callaghan (eocallaghan@alterapraxis.com)]

Edward O'Callaghan (eocallaghan at alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6145

-gerrit

commit a032be417ccb6f7b906760eb10029bf3e1d2b534
Author: Edward O'Callaghan <eocallaghan at alterapraxis.com>
Date:   Sat Jun 28 15:29:26 2014 +1000

    northbridge/amd/{gx2,lx}/raminit.c: Initialise `spd_byte`
    
    If the if-else construct falls through to 'else' then spd_byte is used
    before being initialised. In reality the machine halts before this can
    happen by 'hcf()' so just initialise to zero to avoid compiler warn.
    
    Change-Id: I514dc3d673758f8f546d43a7a0868485d1d8d5ab
    Signed-off-by: Edward O'Callaghan <eocallaghan at alterapraxis.com>
---
 src/northbridge/amd/gx2/raminit.c | 1 +
 src/northbridge/amd/lx/raminit.c  | 1 +
 2 files changed, 2 insertions(+)

diff --git a/src/northbridge/amd/gx2/raminit.c b/src/northbridge/amd/gx2/raminit.c
index 71d0a16..4de25c9 100644
--- a/src/northbridge/amd/gx2/raminit.c
+++ b/src/northbridge/amd/gx2/raminit.c
@@ -306,6 +306,7 @@ static void setCAS(void)
 	} else if ((casmap0 &= casmap1)) {
 		spd_byte = CASDDR[__builtin_ctz(casmap0)];
 	} else {
+		spd_byte = 0;
 		printk(BIOS_EMERG, "DIMM CAS Latencies not compatible\n");
 		post_code(ERROR_DIFF_DIMMS);
 		hcf();
diff --git a/src/northbridge/amd/lx/raminit.c b/src/northbridge/amd/lx/raminit.c
index 6dfb073..4b44d56 100644
--- a/src/northbridge/amd/lx/raminit.c
+++ b/src/northbridge/amd/lx/raminit.c
@@ -319,6 +319,7 @@ static void setCAS(void)
 	} else if ((casmap0 &= casmap1)) {
 		spd_byte = CASDDR[__builtin_ctz(casmap0)];
 	} else {
+		spd_byte = 0;
 		print_emerg("DIMM CAS Latencies not compatible\n");
 		post_code(ERROR_DIFF_DIMMS);
 		hcf();