[coreboot-gerrit] New patch to review for coreboot: 0d0fd07 fsp_baytrail: Set FSP MMIO size by the Kconfig choice

[Martin Roth (gaumless@gmail.com)]

Martin Roth (gaumless at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6087

-gerrit

commit 0d0fd07681b9717f821192987cb241511ff9f266
Author: Martin Roth <martin.roth at se-eng.com>
Date:   Fri Jun 20 20:31:52 2014 -0600

    fsp_baytrail: Set FSP MMIO size by the Kconfig choice
    
    - Add Kconfig selections for MMIO size & base for baytrail.
    - Remove MrcInitMmioSize variable and #defines from chip.h
    - Calculate the MMIO size in MB from the MMIO base for the FSP.
    
    - Remove the MrcInitMmioSize register config from bayleybay_fsp
    devicetree.cb
    
    Change-Id: Ifd592214ed55aea0126aaa9d8bbb703c78cbffef
    Signed-off-by: Martin Roth <martin.roth at se-eng.com>
---
 src/mainboard/intel/bayleybay_fsp/devicetree.cb   |  1 -
 src/soc/intel/fsp_baytrail/Kconfig                | 36 +++++++++++++++++++++--
 src/soc/intel/fsp_baytrail/chip.h                 | 12 --------
 src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c |  4 +--
 4 files changed, 35 insertions(+), 18 deletions(-)

diff --git a/src/mainboard/intel/bayleybay_fsp/devicetree.cb b/src/mainboard/intel/bayleybay_fsp/devicetree.cb
index cfc71ab..6be9b81 100644
--- a/src/mainboard/intel/bayleybay_fsp/devicetree.cb
+++ b/src/mainboard/intel/bayleybay_fsp/devicetree.cb
@@ -28,7 +28,6 @@ chip soc/intel/fsp_baytrail
 	register "MrcInitSPDAddr1"      = "SPD_ADDR_DEFAULT"
 	register "MrcInitSPDAddr2"      = "SPD_ADDR_DEFAULT"
 	register "MrcInitTsegSize"      = "TSEG_SIZE_DEFAULT"
-	register "MrcInitMmioSize"      = "MMIO_SIZE_DEFAULT"
 	register "eMMCBootMode"         = "EMMC_FOLLOWS_DEVICETREE"
 	register "IgdDvmt50PreAlloc"    = "IGD_MEMSIZE_DEFAULT"
 	register "ApertureSize"         = "APERTURE_SIZE_DEFAULT"
diff --git a/src/soc/intel/fsp_baytrail/Kconfig b/src/soc/intel/fsp_baytrail/Kconfig
index bce5542..7f433ef 100644
--- a/src/soc/intel/fsp_baytrail/Kconfig
+++ b/src/soc/intel/fsp_baytrail/Kconfig
@@ -51,11 +51,41 @@ config BOOTBLOCK_CPU_INIT
 	string
 	default "soc/intel/fsp_baytrail/bootblock/bootblock.c"
 
+choice
+	prompt "Set MMIO Size"
+	default SET_MMCONF_2GB if SET_DEFAULT_MMCONF_2GB
+	default SET_MMCONF_1_5GB if SET_DEFAULT_MMCONF_1_5GB
+	default SET_MMCONF_1GB if SET_DEFAULT_MMCONF_1GB
+	default SET_MMCONF_512MB if SET_DEFAULT_MMCONF_512MB
+
+config SET_MMCONF_2GB
+	bool "2 GB"
+	help
+	  Set the MMIO area to 2 GB.
+
+config SET_MMCONF_1_5GB
+	bool "1.5 GB"
+	help
+	  Set the MMIO area to 1.5 GB.
+
+config SET_MMCONF_1GB
+	bool "1 GB"
+	help
+	  Set the MMIO area to 1 GB.
+
+config SET_MMCONF_512MB
+	bool "512 MB"
+	help
+	  Set the MMIO area to 512 MB.
+
+endchoice
+
 config MMCONF_BASE_ADDRESS
 	hex
-	default 0x80000000
-	help
-	  This is set by the FSP
+	default 0xE0000000 if SET_MMCONF_512MB
+	default 0xC0000000 if SET_MMCONF_1GB
+	default 0xA0000000 if SET_MMCONF_1_5GB
+	default 0x80000000 # SET_MMCONF_2GB
 
 config MAX_CPUS
 	int
diff --git a/src/soc/intel/fsp_baytrail/chip.h b/src/soc/intel/fsp_baytrail/chip.h
index 7e86862..5a1ed60 100644
--- a/src/soc/intel/fsp_baytrail/chip.h
+++ b/src/soc/intel/fsp_baytrail/chip.h
@@ -64,18 +64,6 @@ struct soc_intel_fsp_baytrail_config {
 	#define TSEG_SIZE_8_MB		8
 
 	/*
-	 * MrcInitMmioSize
-	 *  0x400, "1.0 GB"s
-	 *  0x600, "1.5 GB"
-	 *  0x800, "2.0 GB"
-	 */
-	uint16_t MrcInitMmioSize;
-	#define MMIO_SIZE_DEFAULT	0x00
-	#define MMIO_SIZE_1_0_GB	0x400
-	#define MMIO_SIZE_1_5_GB	0x600
-	#define MMIO_SIZE_2_0_GB	0x800
-
-	/*
 	 * eMMCBootMode
 	 *   NOTE: These are offset by 1 to set 0 as "use default".  This is so that
 	 *   if the register value is not set in the devicetree.cb file, the default
diff --git a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c
index 60a1f7a..b5a944c 100644
--- a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c
+++ b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c
@@ -106,8 +106,8 @@ static void ConfigureDefaultUpdData(UPD_DATA_REGION *UpdData)
 		UpdData->PcdMrcInitTsegSize = config->MrcInitTsegSize;
 	printk(BIOS_DEBUG, "Tseg Size:\t\t%d MB\n", UpdData->PcdMrcInitTsegSize);
 
-	if (config->MrcInitMmioSize != MMIO_SIZE_DEFAULT)
-		UpdData->PcdMrcInitMmioSize = config->MrcInitMmioSize;
+	UpdData->PcdMrcInitMmioSize = 0x1000 -
+		(CONFIG_MMCONF_BASE_ADDRESS >> 20);
 	printk(BIOS_DEBUG, "MMIO Size:\t\t%d MB\n", UpdData->PcdMrcInitMmioSize);
 
 	if (config->IgdDvmt50PreAlloc != IGD_MEMSIZE_DEFAULT)