[coreboot-gerrit] New patch to review for coreboot: 9e80630 src/superio/ite/it8772f: Separate mainboard from SIO at obj level
Edward O'Callaghan (eocallaghan@alterapraxis.com)
gerrit at coreboot.org
Mon Jun 16 06:15:45 CEST 2014
Edward O'Callaghan (eocallaghan at alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6041
-gerrit
commit 9e80630b9ed72aa3a96daa0d754d41f3abe5996f
Author: Edward O'Callaghan <eocallaghan at alterapraxis.com>
Date: Mon Jun 16 14:13:06 2014 +1000
src/superio/ite/it8772f: Separate mainboard from SIO at obj level
Remove #include early_serial.c and rename to early_init.c as no actual
UART configuration is done here. Note that this SIO component still
hard codes its base address to 0x2e.
Change-Id: Icc817e6f31007f90ff326a36e9c3cc824cae4fa4
Signed-off-by: Edward O'Callaghan <eocallaghan at alterapraxis.com>
---
src/mainboard/samsung/stumpy/romstage.c | 2 -
src/mainboard/samsung/stumpy/smihandler.c | 5 --
src/superio/ite/it8772f/Makefile.inc | 1 +
src/superio/ite/it8772f/early_init.c | 94 +++++++++++++++++++++++++++++++
src/superio/ite/it8772f/early_serial.c | 88 -----------------------------
5 files changed, 95 insertions(+), 95 deletions(-)
diff --git a/src/mainboard/samsung/stumpy/romstage.c b/src/mainboard/samsung/stumpy/romstage.c
index 0ae71a8..09cae66 100644
--- a/src/mainboard/samsung/stumpy/romstage.c
+++ b/src/mainboard/samsung/stumpy/romstage.c
@@ -33,8 +33,6 @@
#include <bootmode.h>
#include <superio/ite/common/ite.h>
#include <superio/ite/it8772f/it8772f.h>
-/* FIXME: SUPERIO include.c */
-#include "superio/ite/it8772f/early_serial.c"
#include "northbridge/intel/sandybridge/sandybridge.h"
#include "northbridge/intel/sandybridge/raminit.h"
#include "southbridge/intel/bd82x6x/pch.h"
diff --git a/src/mainboard/samsung/stumpy/smihandler.c b/src/mainboard/samsung/stumpy/smihandler.c
index 5c3e1b3..47f94d4 100644
--- a/src/mainboard/samsung/stumpy/smihandler.c
+++ b/src/mainboard/samsung/stumpy/smihandler.c
@@ -26,9 +26,6 @@
#include <northbridge/intel/sandybridge/sandybridge.h>
#include <cpu/intel/model_206ax/model_206ax.h>
-/* Include romstage serial for SIO helper functions */
-#include <superio/ite/it8772f/early_serial.c>
-
int mainboard_io_trap_handler(int smif)
{
switch (smif) {
@@ -64,7 +61,6 @@ void mainboard_smi_sleep(u8 slp_typ)
case 3:
case 4:
/* Blink LED */
- it8772f_enter_conf();
it8772f_sio_write(IT8772F_CONFIG_REG_LDN, IT8772F_GPIO);
/* Enable blink pin map */
it8772f_sio_write(IT8772F_GPIO_LED_BLINK1_PINMAP,
@@ -75,7 +71,6 @@ void mainboard_smi_sleep(u8 slp_typ)
reg8 = it8772f_sio_read(GPIO_REG_ENABLE(3));
reg8 &= ~(1 << 5);
it8772f_sio_write(GPIO_REG_ENABLE(3), reg8);
- it8772f_exit_conf();
break;
case 5:
diff --git a/src/superio/ite/it8772f/Makefile.inc b/src/superio/ite/it8772f/Makefile.inc
index 7b6be2c..438ba84 100644
--- a/src/superio/ite/it8772f/Makefile.inc
+++ b/src/superio/ite/it8772f/Makefile.inc
@@ -18,4 +18,5 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
+romstage-$(CONFIG_SUPERIO_ITE_IT8772F) += early_init.c
ramstage-$(CONFIG_SUPERIO_ITE_IT8772F) += superio.c
diff --git a/src/superio/ite/it8772f/early_init.c b/src/superio/ite/it8772f/early_init.c
new file mode 100644
index 0000000..ab8e116
--- /dev/null
+++ b/src/superio/ite/it8772f/early_init.c
@@ -0,0 +1,94 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <device/pnp_def.h>
+#include "it8772f.h"
+
+/* NOTICE: This file is deprecated, use ite/common instead */
+
+/* The base address is 0x2e or 0x4e, depending on config bytes. */
+/* FIXME: SUPERIO include.c */
+#define SIO_BASE 0x2e
+#define SIO_INDEX SIO_BASE
+#define SIO_DATA (SIO_BASE + 1)
+
+/* Global configuration registers. */
+#define IT8772F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */
+#define IT8772F_CONFIG_REG_LDN 0x07 /* Logical Device Number. */
+
+static void it8772f_enter_conf(void)
+{
+ u16 port = SIO_BASE;
+
+ outb(0x87, port);
+ outb(0x01, port);
+ outb(0x55, port);
+ outb((port == 0x4e) ? 0xaa : 0x55, port);
+}
+
+static void it8772f_exit_conf(void)
+{
+ it8772f_sio_write(IT8772F_CONFIG_REG_CC, 0x02);
+}
+
+u8 it8772f_sio_read(u8 index)
+{
+ u8 data;
+ it8772f_enter_conf();
+ outb(index, SIO_BASE);
+ data = inb(SIO_DATA);
+ it8772f_exit_conf();
+ return data;
+}
+
+void it8772f_sio_write(u8 index, u8 value)
+{
+ it8772f_enter_conf();
+ outb(index, SIO_BASE);
+ outb(value, SIO_DATA);
+ it8772f_exit_conf();
+}
+
+/* Set AC resume to be up to the Southbridge */
+void it8772f_ac_resume_southbridge(void)
+{
+ it8772f_enter_conf();
+ it8772f_sio_write(IT8772F_CONFIG_REG_LDN, IT8772F_EC);
+ it8772f_sio_write(0xf4, 0x60);
+ it8772f_exit_conf();
+}
+
+/* Configure a set of GPIOs */
+void it8772f_gpio_setup(int set, u8 select, u8 polarity, u8 pullup,
+ u8 output, u8 enable)
+{
+ set--; /* Set 1 is offset 0 */
+ it8772f_enter_conf();
+ it8772f_sio_write(IT8772F_CONFIG_REG_LDN, IT8772F_GPIO);
+ if (set < 5) {
+ it8772f_sio_write(GPIO_REG_SELECT(set), select);
+ it8772f_sio_write(GPIO_REG_ENABLE(set), enable);
+ it8772f_sio_write(GPIO_REG_POLARITY(set), polarity);
+ }
+ it8772f_sio_write(GPIO_REG_OUTPUT(set), output);
+ it8772f_sio_write(GPIO_REG_PULLUP(set), pullup);
+ it8772f_exit_conf();
+}
diff --git a/src/superio/ite/it8772f/early_serial.c b/src/superio/ite/it8772f/early_serial.c
deleted file mode 100644
index ee9dbc5..0000000
--- a/src/superio/ite/it8772f/early_serial.c
+++ /dev/null
@@ -1,88 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include "it8772f.h"
-
-/* NOTICE: This file is deprecated, use ite/common instead */
-
-/* The base address is 0x2e or 0x4e, depending on config bytes. */
-/* FIXME: SUPERIO include.c */
-#define SIO_BASE 0x2e
-#define SIO_INDEX SIO_BASE
-#define SIO_DATA (SIO_BASE + 1)
-
-/* Global configuration registers. */
-#define IT8772F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */
-#define IT8772F_CONFIG_REG_LDN 0x07 /* Logical Device Number. */
-
-u8 it8772f_sio_read(u8 index)
-{
- outb(index, SIO_BASE);
- return inb(SIO_DATA);
-}
-
-void it8772f_sio_write(u8 index, u8 value)
-{
- outb(index, SIO_BASE);
- outb(value, SIO_DATA);
-}
-
-static void it8772f_enter_conf(void)
-{
- u16 port = SIO_BASE;
-
- outb(0x87, port);
- outb(0x01, port);
- outb(0x55, port);
- outb((port == 0x4e) ? 0xaa : 0x55, port);
-}
-
-static void it8772f_exit_conf(void)
-{
- it8772f_sio_write(IT8772F_CONFIG_REG_CC, 0x02);
-}
-
-/* Set AC resume to be up to the Southbridge */
-void it8772f_ac_resume_southbridge(void)
-{
- it8772f_enter_conf();
- it8772f_sio_write(IT8772F_CONFIG_REG_LDN, IT8772F_EC);
- it8772f_sio_write(0xf4, 0x60);
- it8772f_exit_conf();
-}
-
-/* Configure a set of GPIOs */
-void it8772f_gpio_setup(int set, u8 select, u8 polarity, u8 pullup,
- u8 output, u8 enable)
-{
- set--; /* Set 1 is offset 0 */
- it8772f_enter_conf();
- it8772f_sio_write(IT8772F_CONFIG_REG_LDN, IT8772F_GPIO);
- if (set < 5) {
- it8772f_sio_write(GPIO_REG_SELECT(set), select);
- it8772f_sio_write(GPIO_REG_ENABLE(set), enable);
- it8772f_sio_write(GPIO_REG_POLARITY(set), polarity);
- }
- it8772f_sio_write(GPIO_REG_OUTPUT(set), output);
- it8772f_sio_write(GPIO_REG_PULLUP(set), pullup);
- it8772f_exit_conf();
-}
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