[coreboot-gerrit] Patch set updated for coreboot: 64218ff google/panther: Disable DEVSLP for SATA
Matt DeVillier (matt.devillier@gmail.com)
gerrit at coreboot.org
Sun Jun 15 20:09:34 CEST 2014
Matt DeVillier (matt.devillier at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5999
-gerrit
commit 64218ff9713df61d08cffb64f347f8fcc0963f3e
Author: Stefan Reinauer <reinauer at chromium.org>
Date: Wed Jan 8 15:20:59 2014 -0800
google/panther: Disable DEVSLP for SATA
Some SSD modules don't support DEVSLP correctly due to their
firmware. Since the power savings are minimal, don't use
DEVSLP to prevent potential problems. Some of the symptoms
are that sometimes this causes USB devices to not work properly.
BUG=chrome-os-partner:23186,
BRANCH=panther
TEST=Boot tested on Panther
Change-Id: Iba3f721c73e0e760b6a9861ca23480ddb923df40
Signed-off-by: Matt DeVillier <matt.devillier at gmail.com>
Signed-off-by: Stefan Reinauer <reinauer at google.com>
Reviewed-on: https://chromium-review.googlesource.com/181957
Reviewed-by: Duncan Laurie <dlaurie at chromium.org>
---
src/mainboard/google/panther/devicetree.cb | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/mainboard/google/panther/devicetree.cb b/src/mainboard/google/panther/devicetree.cb
index f461c58..9fbe8e6 100644
--- a/src/mainboard/google/panther/devicetree.cb
+++ b/src/mainboard/google/panther/devicetree.cb
@@ -55,6 +55,7 @@ chip northbridge/intel/haswell
register "ide_legacy_combined" = "0x0"
register "sata_ahci" = "0x1"
register "sata_port_map" = "0x1"
+ register "sata_devslp_disable" = "0x1"
register "sio_acpi_mode" = "0"
register "sio_i2c0_voltage" = "0" # 3.3V
More information about the coreboot-gerrit
mailing list