[coreboot-gerrit] New patch to review for coreboot: dee1382 northbridge/intel: Drop use of set_top_of_ram()

[Kyösti Mälkki (kyosti.malkki@gmail.com)]

Kyösti Mälkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6031

-gerrit

commit dee1382ff3d78512c24aab151f807d9d1ab77983
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date:   Sat Jun 14 15:25:33 2014 +0300

    northbridge/intel: Drop use of set_top_of_ram()
    
    We implement get_top_of_ram() on these chipset to resolve CBMEM
    location early in romstage. Call to set_top_ram() is not required.
    
    Change-Id: I492e436b0c32d2c24677265b35afd05f29dcd0f8
    Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
---
 src/northbridge/intel/gm45/northbridge.c        | 2 --
 src/northbridge/intel/i945/northbridge.c        | 2 --
 src/northbridge/intel/nehalem/northbridge.c     | 2 --
 src/northbridge/intel/sandybridge/northbridge.c | 2 --
 4 files changed, 8 deletions(-)

diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c
index afd270f..afac035 100644
--- a/src/northbridge/intel/gm45/northbridge.c
+++ b/src/northbridge/intel/gm45/northbridge.c
@@ -165,8 +165,6 @@ static void mch_domain_read_resources(device_t dev)
 		fixed_mem_resource(dev, 7, pcie_config_base >> 10,
 			pcie_config_size >> 10, IORESOURCE_RESERVE);
 	}
-
-	set_top_of_ram(tomk << 10);
 }
 
 static void mch_domain_set_resources(device_t dev)
diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c
index 948f5c1..68d6d91 100644
--- a/src/northbridge/intel/i945/northbridge.c
+++ b/src/northbridge/intel/i945/northbridge.c
@@ -170,8 +170,6 @@ static void pci_domain_set_resources(device_t dev)
 	add_fixed_resources(dev, 7);
 
 	assign_resources(dev->link_list);
-
-	set_top_of_ram(tomk_stolen * 1024);
 }
 
 	/* TODO We could determine how many PCIe busses we need in
diff --git a/src/northbridge/intel/nehalem/northbridge.c b/src/northbridge/intel/nehalem/northbridge.c
index 639d245..071ff7f 100644
--- a/src/northbridge/intel/nehalem/northbridge.c
+++ b/src/northbridge/intel/nehalem/northbridge.c
@@ -164,8 +164,6 @@ static void mc_read_resources(device_t dev)
 	    bad_ram_resource(dev, 9, 0x1fc000000ULL >> 10, 0x004000000 >> 10);
 
 	add_fixed_resources(dev, 10);
-
-	set_top_of_ram(tseg_base);
 }
 
 static void mc_set_resources(device_t dev)
diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c
index 5f9912f..b46ae22 100644
--- a/src/northbridge/intel/sandybridge/northbridge.c
+++ b/src/northbridge/intel/sandybridge/northbridge.c
@@ -251,8 +251,6 @@ static void pci_domain_set_resources(device_t dev)
 	add_fixed_resources(dev, 6);
 
 	assign_resources(dev->link_list);
-
-	set_top_of_ram(tomk * 1024);
 }
 
 	/* TODO We could determine how many PCIe busses we need in