[coreboot-gerrit] New patch to review for coreboot: e7e0bdf i945 boards: Drop disabled ram_check() calls
Kyösti Mälkki (kyosti.malkki@gmail.com)
gerrit at coreboot.org
Sun Jun 15 17:51:59 CEST 2014
Kyösti Mälkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6027
-gerrit
commit e7e0bdf34b5b2c9333b98556db605a2edb498c15
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date: Sat Jun 14 21:01:22 2014 +0300
i945 boards: Drop disabled ram_check() calls
This code would not get enabled just by flipping the options in menuconfig,
also ramcheck() no longer test the range like the parameters would imply.
We should add non-destructive ram_check() on S3 resume path to verify
memory controller configuration has been properly recovered.
Change-Id: Ie4675c4770146c4312cdfbc81afa19f243f90ee4
Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
---
src/mainboard/getac/p470/romstage.c | 15 ---------------
src/mainboard/ibase/mb899/romstage.c | 16 ----------------
src/mainboard/intel/d945gclf/romstage.c | 17 -----------------
src/mainboard/kontron/986lcd-m/romstage.c | 17 -----------------
src/mainboard/lenovo/t60/romstage.c | 17 -----------------
src/mainboard/lenovo/x60/romstage.c | 17 -----------------
src/mainboard/roda/rk886ex/romstage.c | 17 -----------------
7 files changed, 116 deletions(-)
diff --git a/src/mainboard/getac/p470/romstage.c b/src/mainboard/getac/p470/romstage.c
index a081a8a..faec40a 100644
--- a/src/mainboard/getac/p470/romstage.c
+++ b/src/mainboard/getac/p470/romstage.c
@@ -340,21 +340,6 @@ void main(unsigned long bist)
/* Initialize the internal PCIe links before we go into stage2 */
i945_late_initialization();
-#if !CONFIG_HAVE_ACPI_RESUME
- /* When doing resume, we must not overwrite RAM */
-#if CONFIG_DEBUG_RAM_SETUP
- sdram_dump_mchbar_registers();
-
- {
- /* This will not work if TSEG is in place! */
- u32 tom = pci_read_config32(PCI_DEV(0,2,0), 0x5c);
-
- printk(BIOS_DEBUG, "TOM: 0x%08x\n", tom);
- ram_check(0x00000000, 0x000a0000);
- ram_check(0x00100000, tom);
- }
-#endif
-#endif
MCHBAR16(SSKPD) = 0xCAFE;
cbmem_was_initted = !cbmem_recovery(boot_mode==2);
diff --git a/src/mainboard/ibase/mb899/romstage.c b/src/mainboard/ibase/mb899/romstage.c
index 418b6e4..e842bba 100644
--- a/src/mainboard/ibase/mb899/romstage.c
+++ b/src/mainboard/ibase/mb899/romstage.c
@@ -290,22 +290,6 @@ void main(unsigned long bist)
/* Initialize the internal PCIe links before we go into stage2 */
i945_late_initialization();
-#if !CONFIG_HAVE_ACPI_RESUME
-#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
-#if CONFIG_DEBUG_RAM_SETUP
- sdram_dump_mchbar_registers();
-#endif
-
- {
- /* This will not work if TSEG is in place! */
- u32 tom = pci_read_config32(PCI_DEV(0,2,0), 0x5c);
-
- printk(BIOS_DEBUG, "TOM: 0x%08x\n", tom);
- ram_check(0x00000000, 0x000a0000);
- //ram_check(0x00100000, tom);
- }
-#endif
-#endif
quick_ram_check();
diff --git a/src/mainboard/intel/d945gclf/romstage.c b/src/mainboard/intel/d945gclf/romstage.c
index 69d4232..5cdb7cd 100644
--- a/src/mainboard/intel/d945gclf/romstage.c
+++ b/src/mainboard/intel/d945gclf/romstage.c
@@ -250,23 +250,6 @@ void main(unsigned long bist)
/* Initialize the internal PCIe links before we go into stage2 */
i945_late_initialization();
-#if !CONFIG_HAVE_ACPI_RESUME
-#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
-#if CONFIG_DEBUG_RAM_SETUP
- sdram_dump_mchbar_registers();
-#endif
-
- {
- /* This will not work if TSEG is in place! */
- u32 tom = pci_read_config32(PCI_DEV(0,2,0), 0x5c);
-
- printk(BIOS_DEBUG, "TOM: 0x%08x\n", tom);
- ram_check(0x00000000, 0x000a0000);
- //ram_check(0x00100000, tom);
- }
-#endif
-#endif
-
MCHBAR16(SSKPD) = 0xCAFE;
cbmem_was_initted = !cbmem_recovery(boot_mode==2);
diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c
index 4acd734..2b63379 100644
--- a/src/mainboard/kontron/986lcd-m/romstage.c
+++ b/src/mainboard/kontron/986lcd-m/romstage.c
@@ -402,23 +402,6 @@ void main(unsigned long bist)
/* Initialize the internal PCIe links before we go into stage2 */
i945_late_initialization();
-#if !CONFIG_HAVE_ACPI_RESUME
-#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
-#if CONFIG_DEBUG_RAM_SETUP
- sdram_dump_mchbar_registers();
-#endif
-
- {
- /* This will not work if TSEG is in place! */
- u32 tom = pci_read_config32(PCI_DEV(0,2,0), 0x5c);
-
- printk(BIOS_DEBUG, "TOM: 0x%08x\n", tom);
- ram_check(0x00000000, 0x000a0000);
- //ram_check(0x00100000, tom);
- }
-#endif
-#endif
-
quick_ram_check();
MCHBAR16(SSKPD) = 0xCAFE;
diff --git a/src/mainboard/lenovo/t60/romstage.c b/src/mainboard/lenovo/t60/romstage.c
index dae917c..d372073 100644
--- a/src/mainboard/lenovo/t60/romstage.c
+++ b/src/mainboard/lenovo/t60/romstage.c
@@ -302,23 +302,6 @@ void main(unsigned long bist)
/* Initialize the internal PCIe links before we go into stage2 */
i945_late_initialization();
-#if !CONFIG_HAVE_ACPI_RESUME
-#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
-#if CONFIG_DEBUG_RAM_SETUP
- sdram_dump_mchbar_registers();
-
- {
- /* This will not work if TSEG is in place! */
- u32 tom = pci_read_config32(PCI_DEV(0,2,0), 0x5c);
-
- printk(BIOS_DEBUG, "TOM: 0x%08x\n", tom);
- ram_check(0x00000000, 0x000a0000);
- ram_check(0x00100000, tom);
- }
-#endif
-#endif
-#endif
-
MCHBAR16(SSKPD) = 0xCAFE;
cbmem_was_initted = !cbmem_recovery(boot_mode==2);
diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c
index 1198fb2..34362de 100644
--- a/src/mainboard/lenovo/x60/romstage.c
+++ b/src/mainboard/lenovo/x60/romstage.c
@@ -304,23 +304,6 @@ void main(unsigned long bist)
/* Initialize the internal PCIe links before we go into stage2 */
i945_late_initialization();
-#if !CONFIG_HAVE_ACPI_RESUME
-#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
-#if CONFIG_DEBUG_RAM_SETUP
- sdram_dump_mchbar_registers();
-
- {
- /* This will not work if TSEG is in place! */
- u32 tom = pci_read_config32(PCI_DEV(0, 2, 0), 0x5c);
-
- printk(BIOS_DEBUG, "TOM: 0x%08x\n", tom);
- ram_check(0x00000000, 0x000a0000);
- ram_check(0x00100000, tom);
- }
-#endif
-#endif
-#endif
-
MCHBAR16(SSKPD) = 0xCAFE;
cbmem_was_initted = !cbmem_recovery(boot_mode==2);
diff --git a/src/mainboard/roda/rk886ex/romstage.c b/src/mainboard/roda/rk886ex/romstage.c
index ad323f5..095dee2 100644
--- a/src/mainboard/roda/rk886ex/romstage.c
+++ b/src/mainboard/roda/rk886ex/romstage.c
@@ -327,23 +327,6 @@ void main(unsigned long bist)
/* Initialize the internal PCIe links before we go into stage2 */
i945_late_initialization();
-#if !CONFIG_HAVE_ACPI_RESUME
-#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
-#if CONFIG_DEBUG_RAM_SETUP
- sdram_dump_mchbar_registers();
-
- {
- /* This will not work if TSEG is in place! */
- u32 tom = pci_read_config32(PCI_DEV(0,2,0), 0x5c);
-
- printk(BIOS_DEBUG, "TOM: 0x%08x\n", tom);
- ram_check(0x00000000, 0x000a0000);
- ram_check(0x00100000, tom);
- }
-#endif
-#endif
-#endif
-
MCHBAR16(SSKPD) = 0xCAFE;
cbmem_was_initted = !cbmem_recovery(boot_mode==2);
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