[coreboot-gerrit] Patch set updated for coreboot: 39a632b lynxpoint: Export pch_enable_lpc() for SuperIO systems
Patrick Georgi (patrick@georgi-clan.de)
gerrit at coreboot.org
Sat Jun 14 23:21:10 CEST 2014
Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6019
-gerrit
commit 39a632b3a0a7d0427f3f6d5884711153d5b07bd2
Author: Stefan Reinauer <reinauer at chromium.org>
Date: Mon Oct 7 16:29:54 2013 -0700
lynxpoint: Export pch_enable_lpc() for SuperIO systems
In order to enable a SuperIO in non ChromeEC systems we
need to make pch_enable_lpc() available to the mainboard
romstage.c
BUG=none
BRANCH=none
TEST=boot ChromeOS on Beltino
Change-Id: I34e7d23012e1852c69e82ba7cdc81a05751846de
Signed-off-by: Matt DeVillier <matt.devillier at gmail.com>
Signed-off-by: Stefan Reinauer <reinauer at google.com>
Reviewed-on: https://chromium-review.googlesource.com/172180
Reviewed-by: Duncan Laurie <dlaurie at chromium.org>
Reviewed-by: Aaron Durbin <adurbin at chromium.org>
Commit-Queue: Stefan Reinauer <reinauer at chromium.org>
---
src/southbridge/intel/lynxpoint/early_pch.c | 2 +-
src/southbridge/intel/lynxpoint/pch.h | 1 +
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c
index 9909bb6..fdbb2a3 100644
--- a/src/southbridge/intel/lynxpoint/early_pch.c
+++ b/src/southbridge/intel/lynxpoint/early_pch.c
@@ -102,7 +102,7 @@ static int sleep_type_s3(void)
return is_s3;
}
-static void pch_enable_lpc(void)
+void pch_enable_lpc(void)
{
const struct device *dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0));
const struct southbridge_intel_lynxpoint_config *config = NULL;
diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h
index 3396367..9b5cb6f 100644
--- a/src/southbridge/intel/lynxpoint/pch.h
+++ b/src/southbridge/intel/lynxpoint/pch.h
@@ -213,6 +213,7 @@ int smbus_read_byte(unsigned device, unsigned address);
int early_spi_read(u32 offset, u32 size, u8 *buffer);
int early_pch_init(const void *gpio_map,
const struct rcba_config_instruction *rcba_config);
+void pch_enable_lpc(void);
#endif /* !__PRE_RAM__ && !__SMM__ */
#endif /* __ASSEMBLER__ */
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