[coreboot-gerrit] Patch merged into coreboot/master: c93a75a AMD/CIMx: Add functions for AMD PCI IRQ routing

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit c93a75a5ab067f86104028b74d92fc54cb939cd5
Author: Mike Loptien <mike.loptien at se-eng.com>
Date:   Fri Jun 6 15:16:29 2014 -0600

    AMD/CIMx: Add functions for AMD PCI IRQ routing
    
    The PCI_INTR table is an Index/Data pair of I/O ports
    0xC00 and 0xC01.  This table is responsible for physically
    routing IRQs to the PIC and IOAPIC.  The settings given
    in this table are chipset and mainboard dependent, so the
    table values will reside in the mainboard.c file. This
    allows for a system to uniquely set its IRQ routing.
    The function to write the PCI_INTR table resides in
    cimx_util.c because the indices into the table have
    the same definitions for all SBx00 FCH chipsets.
    
    The next piece is a function that will read the PCI_INTR
    table and program the INT_LINE and INT_PIN registers in
    PCI config space appropriately.  This function will read
    a devices' INT_PIN register, which is always hardcoded to
    a value if it uses hardware interrupts.  It then uses this
    value, along with the device and function numbers to
    determine an index into the PCI_INTR table.  It will read
    the table and program the corresponding value into the PCI
    config space register 0x3C, INT_LINE.  Finally, it will set
    this IRQ number to LEVEL_TRIGGERED on the PIC because it is
    a PCI device interrupt and the must be level triggered.
    
    For example, the SB800 USB EHCI device 0:18.2 has an INT_PIN
    value hardcoded to 2.  This corresponds to PIN B.  On the
    Persimmon mainboard, I want the USB device to use IRQ 11.  I
    will program the PCI_INTR table at index 0x31 (this USB device
    index) to 11.  This function will then read the INT_PIN register,
    read the PCI_INTR table, and then program the INT_LINE register
    with the value it read.  It will then set the IRQ on the PIC to
    LEVEL_TRIGGERED by writing a 1 to I/O port 0x4D1 at bit position 4.
    
    Also, the SB700 has slightly different register definitions than
    the newer SB800 and SB900 so it needs its own set of #defines for
    the pci_intr registers.
    
    Only the Persimmon mainboard is adapted to this change as an
    example for other mainboards.
    
    Change-Id: I6de858289a17fa1e1abacf6328ea5099be74b1d6
    Signed-off-by: Mike Loptien <mike.loptien at se-eng.com>
    Reviewed-on: http://review.coreboot.org/5877
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
    Reviewed-by: Edward O'Callaghan <eocallaghan at alterapraxis.com>


See http://review.coreboot.org/5877 for details.

-gerrit