[coreboot-gerrit] New patch to review for coreboot: 44a4378 Lenovo x60: add a "#define LPC_DEV PCI_DEV(0, 0x1f, 0)"
HAOUAS Elyes (ehaouas@noos.fr)
gerrit at coreboot.org
Mon Jun 9 08:10:16 CEST 2014
HAOUAS Elyes (ehaouas at noos.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5960
-gerrit
commit 44a43780e64193a5401adafdcba3077e5d69c2d4
Author: Elyes HAOUAS <ehaouas at noos.fr>
Date: Mon Jun 9 08:08:25 2014 +0200
Lenovo x60: add a "#define LPC_DEV PCI_DEV(0, 0x1f, 0)"
Change-Id: Ib8b081121d578b18a77f3f7d1a6c0f1bc3cf977a
Signed-off-by: Elyes HAOUAS <ehaouas at noos.fr>
---
src/mainboard/lenovo/x60/romstage.c | 28 +++++++++++++++-------------
1 file changed, 15 insertions(+), 13 deletions(-)
diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c
index 4f3ef88..3e66709 100644
--- a/src/mainboard/lenovo/x60/romstage.c
+++ b/src/mainboard/lenovo/x60/romstage.c
@@ -39,6 +39,8 @@
#include "southbridge/intel/i82801gx/i82801gx.h"
#include "dock.h"
+#define LPC_DEV PCI_DEV(0, 0x1f, 0)
+
void setup_ich7_gpios(void)
{
printk(BIOS_DEBUG, " GPIOS...");
@@ -82,23 +84,23 @@ void setup_ich7_gpios(void)
static void ich7_enable_lpc(void)
{
// Enable Serial IRQ
- pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0);
+ pci_write_config8(LPC_DEV, SERIRQ_CNTL, 0xd0);
// decode range
- pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0210);
+ pci_write_config16(LPC_DEV, LPC_IO_DEC, 0x0210);
// decode range
- pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x1f0d);
+ pci_write_config16(LPC_DEV, LPC_EN, 0x1f0d);
/* range 0x1600 - 0x167f */
- pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x84, 0x1601);
- pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x86, 0x007c);
+ pci_write_config16(LPC_DEV, 0x84, 0x1601);
+ pci_write_config16(LPC_DEV, 0x86, 0x007c);
/* range 0x15e0 - 0x10ef */
- pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x88, 0x15e1);
- pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x8a, 0x000c);
+ pci_write_config16(LPC_DEV, 0x88, 0x15e1);
+ pci_write_config16(LPC_DEV, 0x8a, 0x000c);
/* range 0x1680 - 0x169f */
- pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x8c, 0x1681);
- pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x8e, 0x001c);
+ pci_write_config16(LPC_DEV, 0x8c, 0x1681);
+ pci_write_config16(LPC_DEV, 0x8e, 0x001c);
}
static void early_superio_config(void)
@@ -167,14 +169,14 @@ static void early_ich7_init(void)
pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20);
// reset rtc power status
- reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4);
+ reg8 = pci_read_config8(LPC_DEV, 0xa4);
reg8 &= ~(1 << 2);
- pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8);
+ pci_write_config8(LPC_DEV, 0xa4, reg8);
// usb transient disconnect
- reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad);
+ reg8 = pci_read_config8(LPC_DEV, 0xad);
reg8 |= (3 << 0);
- pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8);
+ pci_write_config8(LPC_DEV, 0xad, reg8);
reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc);
reg32 |= (1 << 29) | (1 << 17);
More information about the coreboot-gerrit
mailing list