[coreboot-gerrit] New patch to review for coreboot: d921e9a lenovo/x60/i915.c: Add defines for GTT sizes and use them

[Paul Menzel (paulepanter@users.sourceforge.net)]

Paul Menzel (paulepanter at users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5940

-gerrit

commit d921e9a7f1eb6ce30f08af8af310a1e825cc03a9
Author: Paul Menzel <paulepanter at users.sourceforge.net>
Date:   Thu Jun 5 22:22:24 2014 +0200

    lenovo/x60/i915.c: Add defines for GTT sizes and use them
    
    Change-Id: Ia0de8802c6f48eefe1d48e30b5bc07290a407667
    Signed-off-by: Paul Menzel <paulepanter at users.sourceforge.net>
---
 src/mainboard/lenovo/x60/i915.c | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/lenovo/x60/i915.c b/src/mainboard/lenovo/x60/i915.c
index 9300b2b..ba82423 100644
--- a/src/mainboard/lenovo/x60/i915.c
+++ b/src/mainboard/lenovo/x60/i915.c
@@ -59,6 +59,13 @@ static unsigned int physbase;
 
 #define PGETBL_CTL	0x2020
 #define PGETBL_ENABLED	0x00000001
+#define PGETBL_GTT_SIZE	0x00001110
+#define PGETBL_GTT_SIZE_512KB	0x0
+#define PGETBL_GTT_SIZE_256KB	0x1
+#define PGETBL_GTT_SIZE_128KB	0x2
+#define PGETBL_GTT_SIZE_1MB	0x3
+#define PGETBL_GTT_SIZE_2MB	0x4
+#define PGETBL_GTT_SIZE_1_5MB	0x5
 
 
 static u32 htotal, hblank, hsync, vtotal, vblank, vsync;
@@ -138,7 +145,7 @@ int gtt_setup(unsigned int mmiobase)
 	pgetbl_ctl |= PGETBL_ENABLED;
 
 	pgetbl_ctl |= pci_read_config32(dev_find_slot(0, PCI_DEVFN(2,0)), BSM) & 0xfff00000;
-	pgetbl_ctl |= 2; /* set GTT to 256kb */
+	pgetbl_ctl |= PGETBL_GTT_SIZE_256KB << 1; /* set GTT to 256kb */
 
 	write32(mmiobase + GFX_FLSH_CNTL, 0);