[coreboot-gerrit] New patch to review for coreboot: 1a100f7 Board Google: butterfly, link, parrot, peppy, slippy and stout Non-local header treated as local.
HAOUAS Elyes (ehaouas@noos.fr)
gerrit at coreboot.org
Sun Jun 1 19:07:09 CEST 2014
HAOUAS Elyes (ehaouas at noos.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5910
-gerrit
commit 1a100f7c7446675877839a603b8449ac1086eab8
Author: Elyes <ehaouas at noos.fr>
Date: Sun Jun 1 19:04:01 2014 +0200
Board Google:
butterfly, link, parrot,peppy, slippy and stout
Non-local header treated as local.
Change-Id: I1a0ed50724ca4f1c783a578cc7c7661c8221b181
Signed-off-by: Elyes <ehaouas at noos.fr>
---
src/mainboard/google/butterfly/gpio.h | 2 +-
src/mainboard/google/butterfly/romstage.c | 8 ++++----
src/mainboard/google/link/gpio.h | 2 +-
src/mainboard/google/link/romstage.c | 10 +++++-----
src/mainboard/google/parrot/gpio.h | 2 +-
src/mainboard/google/parrot/romstage.c | 10 +++++-----
src/mainboard/google/peppy/romstage.c | 12 ++++++------
src/mainboard/google/slippy/romstage.c | 10 +++++-----
src/mainboard/google/stout/gpio.h | 2 +-
src/mainboard/google/stout/romstage.c | 8 ++++----
10 files changed, 33 insertions(+), 33 deletions(-)
diff --git a/src/mainboard/google/butterfly/gpio.h b/src/mainboard/google/butterfly/gpio.h
index b592e6a..ec68bf8 100644
--- a/src/mainboard/google/butterfly/gpio.h
+++ b/src/mainboard/google/butterfly/gpio.h
@@ -20,7 +20,7 @@
#ifndef BUTTERFLY_GPIO_H
#define BUTTERFLY_GPIO_H
-#include "southbridge/intel/bd82x6x/gpio.h"
+#include <southbridge/intel/bd82x6x/gpio.h>
const struct pch_gpio_set1 pch_gpio_set1_mode = {
.gpio0 = GPIO_MODE_NONE, /* Unused */
diff --git a/src/mainboard/google/butterfly/romstage.c b/src/mainboard/google/butterfly/romstage.c
index d32f3f0..418cb71 100644
--- a/src/mainboard/google/butterfly/romstage.c
+++ b/src/mainboard/google/butterfly/romstage.c
@@ -30,10 +30,10 @@
#include <pc80/mc146818rtc.h>
#include <cbmem.h>
#include <console/console.h>
-#include "northbridge/intel/sandybridge/sandybridge.h"
-#include "northbridge/intel/sandybridge/raminit.h"
-#include "southbridge/intel/bd82x6x/pch.h"
-#include "southbridge/intel/bd82x6x/gpio.h"
+#include <northbridge/intel/sandybridge/sandybridge.h>
+#include <northbridge/intel/sandybridge/raminit.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+#include <southbridge/intel/bd82x6x/gpio.h>
#include <arch/cpu.h>
#include <cpu/x86/bist.h>
#include <cpu/x86/msr.h>
diff --git a/src/mainboard/google/link/gpio.h b/src/mainboard/google/link/gpio.h
index 6caa48b..2b91c6c 100644
--- a/src/mainboard/google/link/gpio.h
+++ b/src/mainboard/google/link/gpio.h
@@ -20,7 +20,7 @@
#ifndef LINK_GPIO_H
#define LINK_GPIO_H
-#include "southbridge/intel/bd82x6x/gpio.h"
+#include <southbridge/intel/bd82x6x/gpio.h>
const struct pch_gpio_set1 pch_gpio_set1_mode = {
.gpio0 = GPIO_MODE_GPIO, /* NMI_DBG# */
diff --git a/src/mainboard/google/link/romstage.c b/src/mainboard/google/link/romstage.c
index 2f17880..3ca61cd 100644
--- a/src/mainboard/google/link/romstage.c
+++ b/src/mainboard/google/link/romstage.c
@@ -31,11 +31,11 @@
#include <pc80/mc146818rtc.h>
#include <cbmem.h>
#include <console/console.h>
-#include "northbridge/intel/sandybridge/sandybridge.h"
-#include "northbridge/intel/sandybridge/raminit.h"
-#include "southbridge/intel/bd82x6x/pch.h"
-#include "southbridge/intel/bd82x6x/gpio.h"
-#include "ec/google/chromeec/ec.h"
+#include <northbridge/intel/sandybridge/sandybridge.h>
+#include <northbridge/intel/sandybridge/raminit.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+#include <southbridge/intel/bd82x6x/gpio.h>
+#include <ec/google/chromeec/ec.h>
#include <arch/cpu.h>
#include <cpu/x86/bist.h>
#include <cpu/x86/msr.h>
diff --git a/src/mainboard/google/parrot/gpio.h b/src/mainboard/google/parrot/gpio.h
index a9eb99b..40fa096 100644
--- a/src/mainboard/google/parrot/gpio.h
+++ b/src/mainboard/google/parrot/gpio.h
@@ -20,7 +20,7 @@
#ifndef PARROT_GPIO_H
#define PARROT_GPIO_H
-#include "southbridge/intel/bd82x6x/gpio.h"
+#include <southbridge/intel/bd82x6x/gpio.h>
const struct pch_gpio_set1 pch_gpio_set1_mode = {
.gpio0 = GPIO_MODE_NONE, /* NOT USED */
diff --git a/src/mainboard/google/parrot/romstage.c b/src/mainboard/google/parrot/romstage.c
index 1799aec..6eb73a2 100644
--- a/src/mainboard/google/parrot/romstage.c
+++ b/src/mainboard/google/parrot/romstage.c
@@ -30,10 +30,10 @@
#include <pc80/mc146818rtc.h>
#include <cbmem.h>
#include <console/console.h>
-#include "northbridge/intel/sandybridge/sandybridge.h"
-#include "northbridge/intel/sandybridge/raminit.h"
-#include "southbridge/intel/bd82x6x/pch.h"
-#include "southbridge/intel/bd82x6x/gpio.h"
+#include <northbridge/intel/sandybridge/sandybridge.h>
+#include <northbridge/intel/sandybridge/raminit.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+#include <southbridge/intel/bd82x6x/gpio.h>
#include <arch/cpu.h>
#include <cpu/x86/bist.h>
#include <cpu/x86/msr.h>
@@ -42,7 +42,7 @@
#include <vendorcode/google/chromeos/chromeos.h>
#endif
#include <cbfs.h>
-#include "ec/compal/ene932/ec.h"
+#include <ec/compal/ene932/ec.h>
static void pch_enable_lpc(void)
{
diff --git a/src/mainboard/google/peppy/romstage.c b/src/mainboard/google/peppy/romstage.c
index 38c224b..8b3516c 100644
--- a/src/mainboard/google/peppy/romstage.c
+++ b/src/mainboard/google/peppy/romstage.c
@@ -24,12 +24,12 @@
#include <string.h>
#include <cbfs.h>
#include <console/console.h>
-#include "cpu/intel/haswell/haswell.h"
-#include "ec/google/chromeec/ec.h"
-#include "northbridge/intel/haswell/haswell.h"
-#include "northbridge/intel/haswell/raminit.h"
-#include "southbridge/intel/lynxpoint/pch.h"
-#include "southbridge/intel/lynxpoint/lp_gpio.h"
+#include <cpu/intel/haswell/haswell.h>
+#include <ec/google/chromeec/ec.h>
+#include <northbridge/intel/haswell/haswell.h>
+#include <northbridge/intel/haswell/raminit.h>
+#include <southbridge/intel/lynxpoint/pch.h>
+#include <southbridge/intel/lynxpoint/lp_gpio.h>
#include "gpio.h"
#include "onboard.h"
diff --git a/src/mainboard/google/slippy/romstage.c b/src/mainboard/google/slippy/romstage.c
index fd190ed..6feebac 100644
--- a/src/mainboard/google/slippy/romstage.c
+++ b/src/mainboard/google/slippy/romstage.c
@@ -24,11 +24,11 @@
#include <string.h>
#include <cbfs.h>
#include <console/console.h>
-#include "cpu/intel/haswell/haswell.h"
-#include "northbridge/intel/haswell/haswell.h"
-#include "northbridge/intel/haswell/raminit.h"
-#include "southbridge/intel/lynxpoint/pch.h"
-#include "southbridge/intel/lynxpoint/lp_gpio.h"
+#include <cpu/intel/haswell/haswell.h>
+#include <northbridge/intel/haswell/haswell.h>
+#include <northbridge/intel/haswell/raminit.h>
+#include <southbridge/intel/lynxpoint/pch.h>
+#include <southbridge/intel/lynxpoint/lp_gpio.h>
#include "gpio.h"
const struct rcba_config_instruction rcba_config[] = {
diff --git a/src/mainboard/google/stout/gpio.h b/src/mainboard/google/stout/gpio.h
index 7bc4667..af3ad12 100644
--- a/src/mainboard/google/stout/gpio.h
+++ b/src/mainboard/google/stout/gpio.h
@@ -20,7 +20,7 @@
#ifndef STOUT_GPIO_H
#define STOUT_GPIO_H
-#include "southbridge/intel/bd82x6x/gpio.h"
+#include <southbridge/intel/bd82x6x/gpio.h>
const struct pch_gpio_set1 pch_gpio_set1_mode = {
.gpio0 = GPIO_MODE_GPIO, /* GPIO0 */
diff --git a/src/mainboard/google/stout/romstage.c b/src/mainboard/google/stout/romstage.c
index f53c07d..76a90ed 100644
--- a/src/mainboard/google/stout/romstage.c
+++ b/src/mainboard/google/stout/romstage.c
@@ -30,10 +30,10 @@
#include <pc80/mc146818rtc.h>
#include <cbmem.h>
#include <console/console.h>
-#include "northbridge/intel/sandybridge/sandybridge.h"
-#include "northbridge/intel/sandybridge/raminit.h"
-#include "southbridge/intel/bd82x6x/pch.h"
-#include "southbridge/intel/bd82x6x/gpio.h"
+#include <northbridge/intel/sandybridge/sandybridge.h>
+#include <northbridge/intel/sandybridge/raminit.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+#include <southbridge/intel/bd82x6x/gpio.h>
#include <arch/cpu.h>
#include <cpu/x86/bist.h>
#include <cpu/x86/msr.h>
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