[coreboot-gerrit] New patch to review for coreboot: c4eb66b AGESA boards: Use devicetree for PCI bus enumeration
Kyösti Mälkki (kyosti.malkki@gmail.com)
gerrit at coreboot.org
Fri Jul 25 14:27:40 CEST 2014
Kyösti Mälkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6358
-gerrit
commit c4eb66bf74931c69a81606688062e7be0cf7ca89
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date: Tue Jul 22 15:24:15 2014 +0300
AGESA boards: Use devicetree for PCI bus enumeration
Previously MP table contained PCI_INT entries for PCI bus behind bridge
0:14.4 even if said PCI bridge function was disabled.
Remove these as invalid, indeterminate bus number could cause conflicts.
PCI_INT entries with bus_sb800[2], bus_hudson[2] and bus_yangtze[2]
were invalid as there is no PCI bridge hardware on device 0:14.0.
Remove these as invalid, indeterminate bus number could cause conflicts.
Change-Id: Ie6a3807f64c8651cf9f732612e1aa7f376a3134f
Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
---
src/mainboard/amd/dinar/mptable.c | 42 ++++++++++++-----------
src/mainboard/amd/inagua/mptable.c | 45 ++++++++++++-------------
src/mainboard/amd/olivehill/mptable.c | 44 ++++++++++++------------
src/mainboard/amd/parmer/mptable.c | 44 ++++++++++++------------
src/mainboard/amd/persimmon/mptable.c | 16 +++++----
src/mainboard/amd/south_station/mptable.c | 45 ++++++++++++-------------
src/mainboard/amd/thatcher/mptable.c | 44 ++++++++++++------------
src/mainboard/amd/torpedo/mptable.c | 46 ++++++++++++--------------
src/mainboard/amd/union_station/mptable.c | 45 ++++++++++++-------------
src/mainboard/asrock/e350m1/mptable.c | 45 ++++++++++++-------------
src/mainboard/asrock/imb-a180/mptable.c | 44 ++++++++++++------------
src/mainboard/asus/f2a85-m/mptable.c | 20 +++++------
src/mainboard/gizmosphere/gizmo/mptable.c | 45 ++++++++++++-------------
src/mainboard/hp/pavilion_m6_1035dx/mptable.c | 44 ++++++++++++------------
src/mainboard/jetway/nf81-t56n-lf/mptable.c | 16 +++++----
src/mainboard/lippert/frontrunner-af/mptable.c | 45 ++++++++++++-------------
src/mainboard/lippert/toucan-af/mptable.c | 45 ++++++++++++-------------
src/mainboard/supermicro/h8qgi/mptable.c | 41 ++++++++++++-----------
src/mainboard/supermicro/h8scm/mptable.c | 41 ++++++++++++-----------
src/mainboard/tyan/s8226/mptable.c | 41 ++++++++++++-----------
20 files changed, 386 insertions(+), 412 deletions(-)
diff --git a/src/mainboard/amd/dinar/mptable.c b/src/mainboard/amd/dinar/mptable.c
index d239a7e..4e481f5 100644
--- a/src/mainboard/amd/dinar/mptable.c
+++ b/src/mainboard/amd/dinar/mptable.c
@@ -28,8 +28,6 @@
#include <cpu/x86/lapic.h>
#include <cpu/amd/amdfam15.h>
-extern u8 bus_sb700[2];
-
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
@@ -126,24 +124,28 @@ static void *smp_write_config_table(void *v)
PCI_INT(0x0, 0x11, 0x0, 0x16); //6, INTG
/* PCI slots */
- /* PCI_SLOT 0. */
- PCI_INT(bus_sb700[1], 0x5, 0x0, 0x14);
- PCI_INT(bus_sb700[1], 0x5, 0x1, 0x15);
- PCI_INT(bus_sb700[1], 0x5, 0x2, 0x16);
- PCI_INT(bus_sb700[1], 0x5, 0x3, 0x17);
-
- /* PCI_SLOT 1. */
- PCI_INT(bus_sb700[1], 0x6, 0x0, 0x15);
- PCI_INT(bus_sb700[1], 0x6, 0x1, 0x16);
- PCI_INT(bus_sb700[1], 0x6, 0x2, 0x17);
- PCI_INT(bus_sb700[1], 0x6, 0x3, 0x14);
-
- /* PCI_SLOT 2. */
- PCI_INT(bus_sb700[1], 0x7, 0x0, 0x16);
- PCI_INT(bus_sb700[1], 0x7, 0x1, 0x17);
- PCI_INT(bus_sb700[1], 0x7, 0x2, 0x14);
- PCI_INT(bus_sb700[1], 0x7, 0x3, 0x15);
-
+ dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
+ if (dev && dev->enabled) {
+ u8 bus_pci = dev->link_list->secondary;
+
+ /* PCI_SLOT 0. */
+ PCI_INT(bus_pci, 0x5, 0x0, 0x14);
+ PCI_INT(bus_pci, 0x5, 0x1, 0x15);
+ PCI_INT(bus_pci, 0x5, 0x2, 0x16);
+ PCI_INT(bus_pci, 0x5, 0x3, 0x17);
+
+ /* PCI_SLOT 1. */
+ PCI_INT(bus_pci, 0x6, 0x0, 0x15);
+ PCI_INT(bus_pci, 0x6, 0x1, 0x16);
+ PCI_INT(bus_pci, 0x6, 0x2, 0x17);
+ PCI_INT(bus_pci, 0x6, 0x3, 0x14);
+
+ /* PCI_SLOT 2. */
+ PCI_INT(bus_pci, 0x7, 0x0, 0x16);
+ PCI_INT(bus_pci, 0x7, 0x1, 0x17);
+ PCI_INT(bus_pci, 0x7, 0x2, 0x14);
+ PCI_INT(bus_pci, 0x7, 0x3, 0x15);
+ }
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0);
diff --git a/src/mainboard/amd/inagua/mptable.c b/src/mainboard/amd/inagua/mptable.c
index 5fdac94..5be5dbc 100644
--- a/src/mainboard/amd/inagua/mptable.c
+++ b/src/mainboard/amd/inagua/mptable.c
@@ -27,11 +27,8 @@
#include <cpu/amd/amdfam14.h>
#include <SBPLATFORM.h>
-extern u8 bus_sb800[6];
-
extern u32 apicid_sb800;
-
u8 intr_data[] = {
[0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* INTA# - INTH# */
[0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, /* Misc-nil,0,1,2, INT from Serial irq */
@@ -112,27 +109,27 @@ static void *smp_write_config_table(void *v)
/* on board NIC & Slot PCIE. */
/* PCI slots */
- /* PCI_SLOT 0. */
- PCI_INT(bus_sb800[1], 0x5, 0x0, 0x14);
- PCI_INT(bus_sb800[1], 0x5, 0x1, 0x15);
- PCI_INT(bus_sb800[1], 0x5, 0x2, 0x16);
- PCI_INT(bus_sb800[1], 0x5, 0x3, 0x17);
-
- /* PCI_SLOT 1. */
- PCI_INT(bus_sb800[1], 0x6, 0x0, 0x15);
- PCI_INT(bus_sb800[1], 0x6, 0x1, 0x16);
- PCI_INT(bus_sb800[1], 0x6, 0x2, 0x17);
- PCI_INT(bus_sb800[1], 0x6, 0x3, 0x14);
-
- /* PCI_SLOT 2. */
- PCI_INT(bus_sb800[1], 0x7, 0x0, 0x16);
- PCI_INT(bus_sb800[1], 0x7, 0x1, 0x17);
- PCI_INT(bus_sb800[1], 0x7, 0x2, 0x14);
- PCI_INT(bus_sb800[1], 0x7, 0x3, 0x15);
-
- PCI_INT(bus_sb800[2], 0x0, 0x0, 0x12);
- PCI_INT(bus_sb800[2], 0x0, 0x1, 0x13);
- PCI_INT(bus_sb800[2], 0x0, 0x2, 0x14);
+ device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
+ if (dev && dev->enabled) {
+ u8 bus_pci = dev->link_list->secondary;
+ /* PCI_SLOT 0. */
+ PCI_INT(bus_pci, 0x5, 0x0, 0x14);
+ PCI_INT(bus_pci, 0x5, 0x1, 0x15);
+ PCI_INT(bus_pci, 0x5, 0x2, 0x16);
+ PCI_INT(bus_pci, 0x5, 0x3, 0x17);
+
+ /* PCI_SLOT 1. */
+ PCI_INT(bus_pci, 0x6, 0x0, 0x15);
+ PCI_INT(bus_pci, 0x6, 0x1, 0x16);
+ PCI_INT(bus_pci, 0x6, 0x2, 0x17);
+ PCI_INT(bus_pci, 0x6, 0x3, 0x14);
+
+ /* PCI_SLOT 2. */
+ PCI_INT(bus_pci, 0x7, 0x0, 0x16);
+ PCI_INT(bus_pci, 0x7, 0x1, 0x17);
+ PCI_INT(bus_pci, 0x7, 0x2, 0x14);
+ PCI_INT(bus_pci, 0x7, 0x3, 0x15);
+ }
/* PCIe PortA */
PCI_INT(0x0, 0x15, 0x0, 0x10);
diff --git a/src/mainboard/amd/olivehill/mptable.c b/src/mainboard/amd/olivehill/mptable.c
index 4a4b15d..c06863b 100644
--- a/src/mainboard/amd/olivehill/mptable.c
+++ b/src/mainboard/amd/olivehill/mptable.c
@@ -29,8 +29,6 @@
#include "southbridge/amd/agesa/hudson/hudson.h" /* pm_ioread() */
#define IO_APIC_ID CONFIG_MAX_CPUS
-extern u8 bus_yangtze[6];
-
extern u32 apicid_yangtze;
u8 picr_data[0x54] = {
@@ -189,27 +187,27 @@ static void *smp_write_config_table(void *v)
/* on board NIC & Slot PCIE. */
/* PCI slots */
- /* PCI_SLOT 0. */
- PCI_INT(bus_yangtze[1], 0x5, 0x0, 0x14);
- PCI_INT(bus_yangtze[1], 0x5, 0x1, 0x15);
- PCI_INT(bus_yangtze[1], 0x5, 0x2, 0x16);
- PCI_INT(bus_yangtze[1], 0x5, 0x3, 0x17);
-
- /* PCI_SLOT 1. */
- PCI_INT(bus_yangtze[1], 0x6, 0x0, 0x15);
- PCI_INT(bus_yangtze[1], 0x6, 0x1, 0x16);
- PCI_INT(bus_yangtze[1], 0x6, 0x2, 0x17);
- PCI_INT(bus_yangtze[1], 0x6, 0x3, 0x14);
-
- /* PCI_SLOT 2. */
- PCI_INT(bus_yangtze[1], 0x7, 0x0, 0x16);
- PCI_INT(bus_yangtze[1], 0x7, 0x1, 0x17);
- PCI_INT(bus_yangtze[1], 0x7, 0x2, 0x14);
- PCI_INT(bus_yangtze[1], 0x7, 0x3, 0x15);
-
- PCI_INT(bus_yangtze[2], 0x0, 0x0, 0x12);
- PCI_INT(bus_yangtze[2], 0x0, 0x1, 0x13);
- PCI_INT(bus_yangtze[2], 0x0, 0x2, 0x14);
+ device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
+ if (dev && dev->enabled) {
+ u8 bus_pci = dev->link_list->secondary;
+ /* PCI_SLOT 0. */
+ PCI_INT(bus_pci, 0x5, 0x0, 0x14);
+ PCI_INT(bus_pci, 0x5, 0x1, 0x15);
+ PCI_INT(bus_pci, 0x5, 0x2, 0x16);
+ PCI_INT(bus_pci, 0x5, 0x3, 0x17);
+
+ /* PCI_SLOT 1. */
+ PCI_INT(bus_pci, 0x6, 0x0, 0x15);
+ PCI_INT(bus_pci, 0x6, 0x1, 0x16);
+ PCI_INT(bus_pci, 0x6, 0x2, 0x17);
+ PCI_INT(bus_pci, 0x6, 0x3, 0x14);
+
+ /* PCI_SLOT 2. */
+ PCI_INT(bus_pci, 0x7, 0x0, 0x16);
+ PCI_INT(bus_pci, 0x7, 0x1, 0x17);
+ PCI_INT(bus_pci, 0x7, 0x2, 0x14);
+ PCI_INT(bus_pci, 0x7, 0x3, 0x15);
+ }
/* PCIe Lan*/
PCI_INT(0x0, 0x06, 0x0, 0x13);
diff --git a/src/mainboard/amd/parmer/mptable.c b/src/mainboard/amd/parmer/mptable.c
index 06c1791..2f5179f 100644
--- a/src/mainboard/amd/parmer/mptable.c
+++ b/src/mainboard/amd/parmer/mptable.c
@@ -29,8 +29,6 @@
#include "southbridge/amd/agesa/hudson/hudson.h" /* pm_ioread() */
#define IO_APIC_ID CONFIG_MAX_CPUS
-extern u8 bus_hudson[6];
-
extern u32 apicid_hudson;
u8 picr_data[0x54] = {
@@ -150,27 +148,27 @@ static void *smp_write_config_table(void *v)
/* on board NIC & Slot PCIE. */
/* PCI slots */
- /* PCI_SLOT 0. */
- PCI_INT(bus_hudson[1], 0x5, 0x0, 0x14);
- PCI_INT(bus_hudson[1], 0x5, 0x1, 0x15);
- PCI_INT(bus_hudson[1], 0x5, 0x2, 0x16);
- PCI_INT(bus_hudson[1], 0x5, 0x3, 0x17);
-
- /* PCI_SLOT 1. */
- PCI_INT(bus_hudson[1], 0x6, 0x0, 0x15);
- PCI_INT(bus_hudson[1], 0x6, 0x1, 0x16);
- PCI_INT(bus_hudson[1], 0x6, 0x2, 0x17);
- PCI_INT(bus_hudson[1], 0x6, 0x3, 0x14);
-
- /* PCI_SLOT 2. */
- PCI_INT(bus_hudson[1], 0x7, 0x0, 0x16);
- PCI_INT(bus_hudson[1], 0x7, 0x1, 0x17);
- PCI_INT(bus_hudson[1], 0x7, 0x2, 0x14);
- PCI_INT(bus_hudson[1], 0x7, 0x3, 0x15);
-
- PCI_INT(bus_hudson[2], 0x0, 0x0, 0x12);
- PCI_INT(bus_hudson[2], 0x0, 0x1, 0x13);
- PCI_INT(bus_hudson[2], 0x0, 0x2, 0x14);
+ device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
+ if (dev && dev->enabled) {
+ u8 bus_pci = dev->link_list->secondary;
+ /* PCI_SLOT 0. */
+ PCI_INT(bus_pci, 0x5, 0x0, 0x14);
+ PCI_INT(bus_pci, 0x5, 0x1, 0x15);
+ PCI_INT(bus_pci, 0x5, 0x2, 0x16);
+ PCI_INT(bus_pci, 0x5, 0x3, 0x17);
+
+ /* PCI_SLOT 1. */
+ PCI_INT(bus_pci, 0x6, 0x0, 0x15);
+ PCI_INT(bus_pci, 0x6, 0x1, 0x16);
+ PCI_INT(bus_pci, 0x6, 0x2, 0x17);
+ PCI_INT(bus_pci, 0x6, 0x3, 0x14);
+
+ /* PCI_SLOT 2. */
+ PCI_INT(bus_pci, 0x7, 0x0, 0x16);
+ PCI_INT(bus_pci, 0x7, 0x1, 0x17);
+ PCI_INT(bus_pci, 0x7, 0x2, 0x14);
+ PCI_INT(bus_pci, 0x7, 0x3, 0x15);
+ }
/* PCIe Lan*/
PCI_INT(0x0, 0x06, 0x0, 0x13);
diff --git a/src/mainboard/amd/persimmon/mptable.c b/src/mainboard/amd/persimmon/mptable.c
index 1c7e86a..0d5f5ce 100644
--- a/src/mainboard/amd/persimmon/mptable.c
+++ b/src/mainboard/amd/persimmon/mptable.c
@@ -31,11 +31,9 @@
#include <drivers/generic/ioapic/chip.h>
#include <arch/ioapic.h>
-extern u8 bus_sb800[6];
extern u32 apicid_sb800;
extern u32 apicver_sb800;
-
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
@@ -110,11 +108,15 @@ static void *smp_write_config_table(void *v)
PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_E]); /* Use INTE */
/* PCI slots */
- /* PCI_SLOT 0 */
- PCI_INT(bus_sb800[1], 0x5, 0x0, intr_data_ptr[PIRQ_E]); /* INTA -> INTE */
- PCI_INT(bus_sb800[1], 0x5, 0x1, intr_data_ptr[PIRQ_F]); /* INTB -> INTF */
- PCI_INT(bus_sb800[1], 0x5, 0x2, intr_data_ptr[PIRQ_G]); /* INTC -> INTG */
- PCI_INT(bus_sb800[1], 0x5, 0x3, intr_data_ptr[PIRQ_H]); /* INTD -> INTH */
+ device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
+ if (dev && dev->enabled) {
+ u8 bus_pci = dev->link_list->secondary;
+ /* PCI_SLOT 0 */
+ PCI_INT(bus_pci, 0x5, 0x0, intr_data_ptr[PIRQ_E]); /* INTA -> INTE */
+ PCI_INT(bus_pci, 0x5, 0x1, intr_data_ptr[PIRQ_F]); /* INTB -> INTF */
+ PCI_INT(bus_pci, 0x5, 0x2, intr_data_ptr[PIRQ_G]); /* INTC -> INTG */
+ PCI_INT(bus_pci, 0x5, 0x3, intr_data_ptr[PIRQ_H]); /* INTD -> INTH */
+ }
/* PCIe PortA */
PCI_INT(0x0, 0x15, 0x0, intr_data_ptr[PIRQ_E]); /* INTA -> INTE */
diff --git a/src/mainboard/amd/south_station/mptable.c b/src/mainboard/amd/south_station/mptable.c
index 4b4658c..d7a4357 100644
--- a/src/mainboard/amd/south_station/mptable.c
+++ b/src/mainboard/amd/south_station/mptable.c
@@ -27,11 +27,8 @@
#include <cpu/amd/amdfam14.h>
#include <SBPLATFORM.h>
-extern u8 bus_sb800[6];
-
extern u32 apicid_sb800;
-
u8 intr_data[] = {
[0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* INTA# - INTH# */
[0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, /* Misc-nil,0,1,2, INT from Serial irq */
@@ -108,27 +105,27 @@ static void *smp_write_config_table(void *v)
/* on board NIC & Slot PCIE. */
/* PCI slots */
- /* PCI_SLOT 0. */
- PCI_INT(bus_sb800[1], 0x5, 0x0, 0x14);
- PCI_INT(bus_sb800[1], 0x5, 0x1, 0x15);
- PCI_INT(bus_sb800[1], 0x5, 0x2, 0x16);
- PCI_INT(bus_sb800[1], 0x5, 0x3, 0x17);
-
- /* PCI_SLOT 1. */
- PCI_INT(bus_sb800[1], 0x6, 0x0, 0x15);
- PCI_INT(bus_sb800[1], 0x6, 0x1, 0x16);
- PCI_INT(bus_sb800[1], 0x6, 0x2, 0x17);
- PCI_INT(bus_sb800[1], 0x6, 0x3, 0x14);
-
- /* PCI_SLOT 2. */
- PCI_INT(bus_sb800[1], 0x7, 0x0, 0x16);
- PCI_INT(bus_sb800[1], 0x7, 0x1, 0x17);
- PCI_INT(bus_sb800[1], 0x7, 0x2, 0x14);
- PCI_INT(bus_sb800[1], 0x7, 0x3, 0x15);
-
- PCI_INT(bus_sb800[2], 0x0, 0x0, 0x12);
- PCI_INT(bus_sb800[2], 0x0, 0x1, 0x13);
- PCI_INT(bus_sb800[2], 0x0, 0x2, 0x14);
+ device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
+ if (dev && dev->enabled) {
+ u8 bus_pci = dev->link_list->secondary;
+ /* PCI_SLOT 0. */
+ PCI_INT(bus_pci, 0x5, 0x0, 0x14);
+ PCI_INT(bus_pci, 0x5, 0x1, 0x15);
+ PCI_INT(bus_pci, 0x5, 0x2, 0x16);
+ PCI_INT(bus_pci, 0x5, 0x3, 0x17);
+
+ /* PCI_SLOT 1. */
+ PCI_INT(bus_pci, 0x6, 0x0, 0x15);
+ PCI_INT(bus_pci, 0x6, 0x1, 0x16);
+ PCI_INT(bus_pci, 0x6, 0x2, 0x17);
+ PCI_INT(bus_pci, 0x6, 0x3, 0x14);
+
+ /* PCI_SLOT 2. */
+ PCI_INT(bus_pci, 0x7, 0x0, 0x16);
+ PCI_INT(bus_pci, 0x7, 0x1, 0x17);
+ PCI_INT(bus_pci, 0x7, 0x2, 0x14);
+ PCI_INT(bus_pci, 0x7, 0x3, 0x15);
+ }
/* PCIe PortA */
PCI_INT(0x0, 0x15, 0x0, 0x10);
diff --git a/src/mainboard/amd/thatcher/mptable.c b/src/mainboard/amd/thatcher/mptable.c
index 089d260..7f9aa7c 100644
--- a/src/mainboard/amd/thatcher/mptable.c
+++ b/src/mainboard/amd/thatcher/mptable.c
@@ -29,8 +29,6 @@
#include "southbridge/amd/agesa/hudson/hudson.h" /* pm_ioread() */
#define IO_APIC_ID CONFIG_MAX_CPUS
-extern u8 bus_hudson[6];
-
extern u32 apicid_hudson;
u8 picr_data[] = {
@@ -150,27 +148,27 @@ static void *smp_write_config_table(void *v)
/* on board NIC & Slot PCIE. */
/* PCI slots */
- /* PCI_SLOT 0. */
- PCI_INT(bus_hudson[1], 0x5, 0x0, 0x14);
- PCI_INT(bus_hudson[1], 0x5, 0x1, 0x15);
- PCI_INT(bus_hudson[1], 0x5, 0x2, 0x16);
- PCI_INT(bus_hudson[1], 0x5, 0x3, 0x17);
-
- /* PCI_SLOT 1. */
- PCI_INT(bus_hudson[1], 0x6, 0x0, 0x15);
- PCI_INT(bus_hudson[1], 0x6, 0x1, 0x16);
- PCI_INT(bus_hudson[1], 0x6, 0x2, 0x17);
- PCI_INT(bus_hudson[1], 0x6, 0x3, 0x14);
-
- /* PCI_SLOT 2. */
- PCI_INT(bus_hudson[1], 0x7, 0x0, 0x16);
- PCI_INT(bus_hudson[1], 0x7, 0x1, 0x17);
- PCI_INT(bus_hudson[1], 0x7, 0x2, 0x14);
- PCI_INT(bus_hudson[1], 0x7, 0x3, 0x15);
-
- PCI_INT(bus_hudson[2], 0x0, 0x0, 0x12);
- PCI_INT(bus_hudson[2], 0x0, 0x1, 0x13);
- PCI_INT(bus_hudson[2], 0x0, 0x2, 0x14);
+ device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
+ if (dev && dev->enabled) {
+ u8 bus_pci = dev->link_list->secondary;
+ /* PCI_SLOT 0. */
+ PCI_INT(bus_pci, 0x5, 0x0, 0x14);
+ PCI_INT(bus_pci, 0x5, 0x1, 0x15);
+ PCI_INT(bus_pci, 0x5, 0x2, 0x16);
+ PCI_INT(bus_pci, 0x5, 0x3, 0x17);
+
+ /* PCI_SLOT 1. */
+ PCI_INT(bus_pci, 0x6, 0x0, 0x15);
+ PCI_INT(bus_pci, 0x6, 0x1, 0x16);
+ PCI_INT(bus_pci, 0x6, 0x2, 0x17);
+ PCI_INT(bus_pci, 0x6, 0x3, 0x14);
+
+ /* PCI_SLOT 2. */
+ PCI_INT(bus_pci, 0x7, 0x0, 0x16);
+ PCI_INT(bus_pci, 0x7, 0x1, 0x17);
+ PCI_INT(bus_pci, 0x7, 0x2, 0x14);
+ PCI_INT(bus_pci, 0x7, 0x3, 0x15);
+ }
/* PCIe Lan*/
PCI_INT(0x0, 0x06, 0x0, 0x13);
diff --git a/src/mainboard/amd/torpedo/mptable.c b/src/mainboard/amd/torpedo/mptable.c
index 821bcde..151243a 100644
--- a/src/mainboard/amd/torpedo/mptable.c
+++ b/src/mainboard/amd/torpedo/mptable.c
@@ -30,9 +30,6 @@
#include "SbPlatform.h"
#define IO_APIC_ID CONFIG_MAX_CPUS
-extern u8 bus_sb900[6];
-
-
u32 apicid_sb900;
u8 picr_data[] = {
@@ -193,27 +190,28 @@ static void *smp_write_config_table(void *v)
/* on board NIC & Slot PCIE. */
/* PCI slots */
- /* PCI_SLOT 0. */
- PCI_INT(bus_sb900[1], 0x5, 0x0, 0x14);
- PCI_INT(bus_sb900[1], 0x5, 0x1, 0x15);
- PCI_INT(bus_sb900[1], 0x5, 0x2, 0x16);
- PCI_INT(bus_sb900[1], 0x5, 0x3, 0x17);
-
- /* PCI_SLOT 1. */
- PCI_INT(bus_sb900[1], 0x6, 0x0, 0x15);
- PCI_INT(bus_sb900[1], 0x6, 0x1, 0x16);
- PCI_INT(bus_sb900[1], 0x6, 0x2, 0x17);
- PCI_INT(bus_sb900[1], 0x6, 0x3, 0x14);
-
- /* PCI_SLOT 2. */
- PCI_INT(bus_sb900[1], 0x7, 0x0, 0x16);
- PCI_INT(bus_sb900[1], 0x7, 0x1, 0x17);
- PCI_INT(bus_sb900[1], 0x7, 0x2, 0x14);
- PCI_INT(bus_sb900[1], 0x7, 0x3, 0x15);
-
- PCI_INT(bus_sb900[1], 0x0, 0x0, 0x12);
- PCI_INT(bus_sb900[1], 0x0, 0x1, 0x13);
- PCI_INT(bus_sb900[1], 0x0, 0x2, 0x14);
+ device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
+ if (dev && dev->enabled) {
+ u8 bus_pci = dev->link_list->secondary;
+
+ /* PCI_SLOT 0. */
+ PCI_INT(bus_pci, 0x5, 0x0, 0x14);
+ PCI_INT(bus_pci, 0x5, 0x1, 0x15);
+ PCI_INT(bus_pci, 0x5, 0x2, 0x16);
+ PCI_INT(bus_pci, 0x5, 0x3, 0x17);
+
+ /* PCI_SLOT 1. */
+ PCI_INT(bus_pci, 0x6, 0x0, 0x15);
+ PCI_INT(bus_pci, 0x6, 0x1, 0x16);
+ PCI_INT(bus_pci, 0x6, 0x2, 0x17);
+ PCI_INT(bus_pci, 0x6, 0x3, 0x14);
+
+ /* PCI_SLOT 2. */
+ PCI_INT(bus_pci, 0x7, 0x0, 0x16);
+ PCI_INT(bus_pci, 0x7, 0x1, 0x17);
+ PCI_INT(bus_pci, 0x7, 0x2, 0x14);
+ PCI_INT(bus_pci, 0x7, 0x3, 0x15);
+ }
/* PCIe Lan*/
PCI_INT(0x0, 0x06, 0x0, 0x13);
diff --git a/src/mainboard/amd/union_station/mptable.c b/src/mainboard/amd/union_station/mptable.c
index 4b4658c..d7a4357 100644
--- a/src/mainboard/amd/union_station/mptable.c
+++ b/src/mainboard/amd/union_station/mptable.c
@@ -27,11 +27,8 @@
#include <cpu/amd/amdfam14.h>
#include <SBPLATFORM.h>
-extern u8 bus_sb800[6];
-
extern u32 apicid_sb800;
-
u8 intr_data[] = {
[0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* INTA# - INTH# */
[0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, /* Misc-nil,0,1,2, INT from Serial irq */
@@ -108,27 +105,27 @@ static void *smp_write_config_table(void *v)
/* on board NIC & Slot PCIE. */
/* PCI slots */
- /* PCI_SLOT 0. */
- PCI_INT(bus_sb800[1], 0x5, 0x0, 0x14);
- PCI_INT(bus_sb800[1], 0x5, 0x1, 0x15);
- PCI_INT(bus_sb800[1], 0x5, 0x2, 0x16);
- PCI_INT(bus_sb800[1], 0x5, 0x3, 0x17);
-
- /* PCI_SLOT 1. */
- PCI_INT(bus_sb800[1], 0x6, 0x0, 0x15);
- PCI_INT(bus_sb800[1], 0x6, 0x1, 0x16);
- PCI_INT(bus_sb800[1], 0x6, 0x2, 0x17);
- PCI_INT(bus_sb800[1], 0x6, 0x3, 0x14);
-
- /* PCI_SLOT 2. */
- PCI_INT(bus_sb800[1], 0x7, 0x0, 0x16);
- PCI_INT(bus_sb800[1], 0x7, 0x1, 0x17);
- PCI_INT(bus_sb800[1], 0x7, 0x2, 0x14);
- PCI_INT(bus_sb800[1], 0x7, 0x3, 0x15);
-
- PCI_INT(bus_sb800[2], 0x0, 0x0, 0x12);
- PCI_INT(bus_sb800[2], 0x0, 0x1, 0x13);
- PCI_INT(bus_sb800[2], 0x0, 0x2, 0x14);
+ device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
+ if (dev && dev->enabled) {
+ u8 bus_pci = dev->link_list->secondary;
+ /* PCI_SLOT 0. */
+ PCI_INT(bus_pci, 0x5, 0x0, 0x14);
+ PCI_INT(bus_pci, 0x5, 0x1, 0x15);
+ PCI_INT(bus_pci, 0x5, 0x2, 0x16);
+ PCI_INT(bus_pci, 0x5, 0x3, 0x17);
+
+ /* PCI_SLOT 1. */
+ PCI_INT(bus_pci, 0x6, 0x0, 0x15);
+ PCI_INT(bus_pci, 0x6, 0x1, 0x16);
+ PCI_INT(bus_pci, 0x6, 0x2, 0x17);
+ PCI_INT(bus_pci, 0x6, 0x3, 0x14);
+
+ /* PCI_SLOT 2. */
+ PCI_INT(bus_pci, 0x7, 0x0, 0x16);
+ PCI_INT(bus_pci, 0x7, 0x1, 0x17);
+ PCI_INT(bus_pci, 0x7, 0x2, 0x14);
+ PCI_INT(bus_pci, 0x7, 0x3, 0x15);
+ }
/* PCIe PortA */
PCI_INT(0x0, 0x15, 0x0, 0x10);
diff --git a/src/mainboard/asrock/e350m1/mptable.c b/src/mainboard/asrock/e350m1/mptable.c
index 198ac21..fd2f712 100644
--- a/src/mainboard/asrock/e350m1/mptable.c
+++ b/src/mainboard/asrock/e350m1/mptable.c
@@ -28,11 +28,8 @@
#include <southbridge/amd/cimx/sb800/SBPLATFORM.h>
-extern u8 bus_sb800[6];
-
extern u32 apicid_sb800;
-
u8 intr_data[] = {
[0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* INTA# - INTH# */
[0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, /* Misc-nil,0,1,2, INT from Serial irq */
@@ -109,27 +106,27 @@ static void *smp_write_config_table(void *v)
/* on board NIC & Slot PCIE. */
/* PCI slots */
- /* PCI_SLOT 0. */
- PCI_INT(bus_sb800[1], 0x5, 0x0, 0x14);
- PCI_INT(bus_sb800[1], 0x5, 0x1, 0x15);
- PCI_INT(bus_sb800[1], 0x5, 0x2, 0x16);
- PCI_INT(bus_sb800[1], 0x5, 0x3, 0x17);
-
- /* PCI_SLOT 1. */
- PCI_INT(bus_sb800[1], 0x6, 0x0, 0x15);
- PCI_INT(bus_sb800[1], 0x6, 0x1, 0x16);
- PCI_INT(bus_sb800[1], 0x6, 0x2, 0x17);
- PCI_INT(bus_sb800[1], 0x6, 0x3, 0x14);
-
- /* PCI_SLOT 2. */
- PCI_INT(bus_sb800[1], 0x7, 0x0, 0x16);
- PCI_INT(bus_sb800[1], 0x7, 0x1, 0x17);
- PCI_INT(bus_sb800[1], 0x7, 0x2, 0x14);
- PCI_INT(bus_sb800[1], 0x7, 0x3, 0x15);
-
- PCI_INT(bus_sb800[2], 0x0, 0x0, 0x12);
- PCI_INT(bus_sb800[2], 0x0, 0x1, 0x13);
- PCI_INT(bus_sb800[2], 0x0, 0x2, 0x14);
+ device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
+ if (dev && dev->enabled) {
+ u8 bus_pci = dev->link_list->secondary;
+ /* PCI_SLOT 0. */
+ PCI_INT(bus_pci, 0x5, 0x0, 0x14);
+ PCI_INT(bus_pci, 0x5, 0x1, 0x15);
+ PCI_INT(bus_pci, 0x5, 0x2, 0x16);
+ PCI_INT(bus_pci, 0x5, 0x3, 0x17);
+
+ /* PCI_SLOT 1. */
+ PCI_INT(bus_pci, 0x6, 0x0, 0x15);
+ PCI_INT(bus_pci, 0x6, 0x1, 0x16);
+ PCI_INT(bus_pci, 0x6, 0x2, 0x17);
+ PCI_INT(bus_pci, 0x6, 0x3, 0x14);
+
+ /* PCI_SLOT 2. */
+ PCI_INT(bus_pci, 0x7, 0x0, 0x16);
+ PCI_INT(bus_pci, 0x7, 0x1, 0x17);
+ PCI_INT(bus_pci, 0x7, 0x2, 0x14);
+ PCI_INT(bus_pci, 0x7, 0x3, 0x15);
+ }
/* PCIe PortA */
PCI_INT(0x0, 0x15, 0x0, 0x10);
diff --git a/src/mainboard/asrock/imb-a180/mptable.c b/src/mainboard/asrock/imb-a180/mptable.c
index a8326a0..11da130 100644
--- a/src/mainboard/asrock/imb-a180/mptable.c
+++ b/src/mainboard/asrock/imb-a180/mptable.c
@@ -29,8 +29,6 @@
#include "southbridge/amd/agesa/hudson/hudson.h" /* pm_ioread() */
#define IO_APIC_ID CONFIG_MAX_CPUS
-extern u8 bus_yangtze[6];
-
extern u32 apicid_yangtze;
u8 picr_data[0x54] = {
@@ -189,27 +187,27 @@ static void *smp_write_config_table(void *v)
/* on board NIC & Slot PCIE. */
/* PCI slots */
- /* PCI_SLOT 0. */
- PCI_INT(bus_yangtze[1], 0x5, 0x0, 0x14);
- PCI_INT(bus_yangtze[1], 0x5, 0x1, 0x15);
- PCI_INT(bus_yangtze[1], 0x5, 0x2, 0x16);
- PCI_INT(bus_yangtze[1], 0x5, 0x3, 0x17);
-
- /* PCI_SLOT 1. */
- PCI_INT(bus_yangtze[1], 0x6, 0x0, 0x15);
- PCI_INT(bus_yangtze[1], 0x6, 0x1, 0x16);
- PCI_INT(bus_yangtze[1], 0x6, 0x2, 0x17);
- PCI_INT(bus_yangtze[1], 0x6, 0x3, 0x14);
-
- /* PCI_SLOT 2. */
- PCI_INT(bus_yangtze[1], 0x7, 0x0, 0x16);
- PCI_INT(bus_yangtze[1], 0x7, 0x1, 0x17);
- PCI_INT(bus_yangtze[1], 0x7, 0x2, 0x14);
- PCI_INT(bus_yangtze[1], 0x7, 0x3, 0x15);
-
- PCI_INT(bus_yangtze[2], 0x0, 0x0, 0x12);
- PCI_INT(bus_yangtze[2], 0x0, 0x1, 0x13);
- PCI_INT(bus_yangtze[2], 0x0, 0x2, 0x14);
+ device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
+ if (dev && dev->enabled) {
+ u8 bus_pci = dev->link_list->secondary;
+ /* PCI_SLOT 0. */
+ PCI_INT(bus_pci, 0x5, 0x0, 0x14);
+ PCI_INT(bus_pci, 0x5, 0x1, 0x15);
+ PCI_INT(bus_pci, 0x5, 0x2, 0x16);
+ PCI_INT(bus_pci, 0x5, 0x3, 0x17);
+
+ /* PCI_SLOT 1. */
+ PCI_INT(bus_pci, 0x6, 0x0, 0x15);
+ PCI_INT(bus_pci, 0x6, 0x1, 0x16);
+ PCI_INT(bus_pci, 0x6, 0x2, 0x17);
+ PCI_INT(bus_pci, 0x6, 0x3, 0x14);
+
+ /* PCI_SLOT 2. */
+ PCI_INT(bus_pci, 0x7, 0x0, 0x16);
+ PCI_INT(bus_pci, 0x7, 0x1, 0x17);
+ PCI_INT(bus_pci, 0x7, 0x2, 0x14);
+ PCI_INT(bus_pci, 0x7, 0x3, 0x15);
+ }
/* PCIe Lan*/
PCI_INT(0x0, 0x06, 0x0, 0x13);
diff --git a/src/mainboard/asus/f2a85-m/mptable.c b/src/mainboard/asus/f2a85-m/mptable.c
index cc3e9ec..3316b83 100644
--- a/src/mainboard/asus/f2a85-m/mptable.c
+++ b/src/mainboard/asus/f2a85-m/mptable.c
@@ -28,8 +28,6 @@
#include "southbridge/amd/agesa/hudson/hudson.h" /* pm_ioread() */
#define IO_APIC_ID CONFIG_MAX_CPUS
-extern u8 bus_hudson[6];
-
extern u32 apicid_hudson;
u8 picr_data[] = {
@@ -155,15 +153,15 @@ static void *smp_write_config_table(void *v)
/* on board NIC & Slot PCIE. */
/* PCI slots */
- /* PCI_SLOT 0. */
- PCI_INT(bus_hudson[1], 0x5, 0x0, 0x14);
- PCI_INT(bus_hudson[1], 0x5, 0x1, 0x15);
- PCI_INT(bus_hudson[1], 0x5, 0x2, 0x16);
- PCI_INT(bus_hudson[1], 0x5, 0x3, 0x17);
-
- PCI_INT(bus_hudson[2], 0x0, 0x0, 0x12);
- PCI_INT(bus_hudson[2], 0x0, 0x1, 0x13);
- PCI_INT(bus_hudson[2], 0x0, 0x2, 0x14);
+ device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
+ if (dev && dev->enabled) {
+ u8 bus_pci = dev->link_list->secondary;
+ /* PCI_SLOT 0. */
+ PCI_INT(bus_pci, 0x5, 0x0, 0x14);
+ PCI_INT(bus_pci, 0x5, 0x1, 0x15);
+ PCI_INT(bus_pci, 0x5, 0x2, 0x16);
+ PCI_INT(bus_pci, 0x5, 0x3, 0x17);
+ }
/* PCIe Lan*/
PCI_INT(0x0, 0x06, 0x0, 0x13);
diff --git a/src/mainboard/gizmosphere/gizmo/mptable.c b/src/mainboard/gizmosphere/gizmo/mptable.c
index 701cd7b..aa2fad4 100755
--- a/src/mainboard/gizmosphere/gizmo/mptable.c
+++ b/src/mainboard/gizmosphere/gizmo/mptable.c
@@ -28,11 +28,8 @@
#include <cpu/amd/amdfam14.h>
#include <SBPLATFORM.h>
-extern u8 bus_sb800[6];
-
extern u32 apicid_sb800;
-
u8 intr_data[] = {
[0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* INTA# - INTH# */
[0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, /* Misc-nil,0,1,2, INT from Serial irq */
@@ -109,27 +106,27 @@ static void *smp_write_config_table(void *v)
/* on board NIC & Slot PCIE. */
/* PCI slots */
- /* PCI_SLOT 0. */
- PCI_INT(bus_sb800[1], 0x5, 0x0, 0x14);
- PCI_INT(bus_sb800[1], 0x5, 0x1, 0x15);
- PCI_INT(bus_sb800[1], 0x5, 0x2, 0x16);
- PCI_INT(bus_sb800[1], 0x5, 0x3, 0x17);
-
- /* PCI_SLOT 1. */
- PCI_INT(bus_sb800[1], 0x6, 0x0, 0x15);
- PCI_INT(bus_sb800[1], 0x6, 0x1, 0x16);
- PCI_INT(bus_sb800[1], 0x6, 0x2, 0x17);
- PCI_INT(bus_sb800[1], 0x6, 0x3, 0x14);
-
- /* PCI_SLOT 2. */
- PCI_INT(bus_sb800[1], 0x7, 0x0, 0x16);
- PCI_INT(bus_sb800[1], 0x7, 0x1, 0x17);
- PCI_INT(bus_sb800[1], 0x7, 0x2, 0x14);
- PCI_INT(bus_sb800[1], 0x7, 0x3, 0x15);
-
- PCI_INT(bus_sb800[2], 0x0, 0x0, 0x12);
- PCI_INT(bus_sb800[2], 0x0, 0x1, 0x13);
- PCI_INT(bus_sb800[2], 0x0, 0x2, 0x14);
+ device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
+ if (dev && dev->enabled) {
+ u8 bus_pci = dev->link_list->secondary;
+ /* PCI_SLOT 0. */
+ PCI_INT(bus_pci, 0x5, 0x0, 0x14);
+ PCI_INT(bus_pci, 0x5, 0x1, 0x15);
+ PCI_INT(bus_pci, 0x5, 0x2, 0x16);
+ PCI_INT(bus_pci, 0x5, 0x3, 0x17);
+
+ /* PCI_SLOT 1. */
+ PCI_INT(bus_pci, 0x6, 0x0, 0x15);
+ PCI_INT(bus_pci, 0x6, 0x1, 0x16);
+ PCI_INT(bus_pci, 0x6, 0x2, 0x17);
+ PCI_INT(bus_pci, 0x6, 0x3, 0x14);
+
+ /* PCI_SLOT 2. */
+ PCI_INT(bus_pci, 0x7, 0x0, 0x16);
+ PCI_INT(bus_pci, 0x7, 0x1, 0x17);
+ PCI_INT(bus_pci, 0x7, 0x2, 0x14);
+ PCI_INT(bus_pci, 0x7, 0x3, 0x15);
+ }
/* PCIe PortA */
PCI_INT(0x0, 0x15, 0x0, 0x10);
diff --git a/src/mainboard/hp/pavilion_m6_1035dx/mptable.c b/src/mainboard/hp/pavilion_m6_1035dx/mptable.c
index 40b2e04..9ef2b81 100644
--- a/src/mainboard/hp/pavilion_m6_1035dx/mptable.c
+++ b/src/mainboard/hp/pavilion_m6_1035dx/mptable.c
@@ -29,8 +29,6 @@
#include <southbridge/amd/agesa/hudson/hudson.h> /* pm_ioread() */
#define IO_APIC_ID CONFIG_MAX_CPUS
-extern u8 bus_hudson[6];
-
extern u32 apicid_hudson;
u8 picr_data[0x54] = {
@@ -150,27 +148,27 @@ static void *smp_write_config_table(void *v)
/* on board NIC & Slot PCIE. */
/* PCI slots */
- /* PCI_SLOT 0. */
- PCI_INT(bus_hudson[1], 0x5, 0x0, 0x14);
- PCI_INT(bus_hudson[1], 0x5, 0x1, 0x15);
- PCI_INT(bus_hudson[1], 0x5, 0x2, 0x16);
- PCI_INT(bus_hudson[1], 0x5, 0x3, 0x17);
-
- /* PCI_SLOT 1. */
- PCI_INT(bus_hudson[1], 0x6, 0x0, 0x15);
- PCI_INT(bus_hudson[1], 0x6, 0x1, 0x16);
- PCI_INT(bus_hudson[1], 0x6, 0x2, 0x17);
- PCI_INT(bus_hudson[1], 0x6, 0x3, 0x14);
-
- /* PCI_SLOT 2. */
- PCI_INT(bus_hudson[1], 0x7, 0x0, 0x16);
- PCI_INT(bus_hudson[1], 0x7, 0x1, 0x17);
- PCI_INT(bus_hudson[1], 0x7, 0x2, 0x14);
- PCI_INT(bus_hudson[1], 0x7, 0x3, 0x15);
-
- PCI_INT(bus_hudson[2], 0x0, 0x0, 0x12);
- PCI_INT(bus_hudson[2], 0x0, 0x1, 0x13);
- PCI_INT(bus_hudson[2], 0x0, 0x2, 0x14);
+ device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
+ if (dev && dev->enabled) {
+ u8 bus_pci = dev->link_list->secondary;
+ /* PCI_SLOT 0. */
+ PCI_INT(bus_pci, 0x5, 0x0, 0x14);
+ PCI_INT(bus_pci, 0x5, 0x1, 0x15);
+ PCI_INT(bus_pci, 0x5, 0x2, 0x16);
+ PCI_INT(bus_pci, 0x5, 0x3, 0x17);
+
+ /* PCI_SLOT 1. */
+ PCI_INT(bus_pci, 0x6, 0x0, 0x15);
+ PCI_INT(bus_pci, 0x6, 0x1, 0x16);
+ PCI_INT(bus_pci, 0x6, 0x2, 0x17);
+ PCI_INT(bus_pci, 0x6, 0x3, 0x14);
+
+ /* PCI_SLOT 2. */
+ PCI_INT(bus_pci, 0x7, 0x0, 0x16);
+ PCI_INT(bus_pci, 0x7, 0x1, 0x17);
+ PCI_INT(bus_pci, 0x7, 0x2, 0x14);
+ PCI_INT(bus_pci, 0x7, 0x3, 0x15);
+ }
/* PCIe Lan*/
PCI_INT(0x0, 0x06, 0x0, 0x13);
diff --git a/src/mainboard/jetway/nf81-t56n-lf/mptable.c b/src/mainboard/jetway/nf81-t56n-lf/mptable.c
index 1bbe487..b621dd2 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/mptable.c
+++ b/src/mainboard/jetway/nf81-t56n-lf/mptable.c
@@ -33,11 +33,9 @@
#include <southbridge/amd/amd_pci_util.h>
#include <southbridge/amd/cimx/sb800/SBPLATFORM.h>
-extern u8 bus_sb800[6];
extern u32 apicid_sb800;
extern u32 apicver_sb800;
-
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
@@ -112,11 +110,15 @@ static void *smp_write_config_table(void *v)
PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_E]); /* Use INTE */
/* PCI slots */
- /* PCI_SLOT 0 */
- PCI_INT(bus_sb800[1], 0x5, 0x0, intr_data_ptr[PIRQ_E]); /* INTA -> INTE */
- PCI_INT(bus_sb800[1], 0x5, 0x1, intr_data_ptr[PIRQ_F]); /* INTB -> INTF */
- PCI_INT(bus_sb800[1], 0x5, 0x2, intr_data_ptr[PIRQ_G]); /* INTC -> INTG */
- PCI_INT(bus_sb800[1], 0x5, 0x3, intr_data_ptr[PIRQ_H]); /* INTD -> INTH */
+ device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
+ if (dev && dev->enabled) {
+ u8 bus_pci = dev->link_list->secondary;
+ /* PCI_SLOT 0 */
+ PCI_INT(bus_pci, 0x5, 0x0, intr_data_ptr[PIRQ_E]); /* INTA -> INTE */
+ PCI_INT(bus_pci, 0x5, 0x1, intr_data_ptr[PIRQ_F]); /* INTB -> INTF */
+ PCI_INT(bus_pci, 0x5, 0x2, intr_data_ptr[PIRQ_G]); /* INTC -> INTG */
+ PCI_INT(bus_pci, 0x5, 0x3, intr_data_ptr[PIRQ_H]); /* INTD -> INTH */
+ }
/* On-board Realtek NIC 2. (PCIe PortA) */
PCI_INT(0x0, 0x15, 0x0, intr_data_ptr[PIRQ_E]); /* INTA -> INTE */
diff --git a/src/mainboard/lippert/frontrunner-af/mptable.c b/src/mainboard/lippert/frontrunner-af/mptable.c
index 8b57167..f5de39e 100644
--- a/src/mainboard/lippert/frontrunner-af/mptable.c
+++ b/src/mainboard/lippert/frontrunner-af/mptable.c
@@ -27,11 +27,8 @@
#include <cpu/amd/amdfam14.h>
#include <SBPLATFORM.h>
-extern u8 bus_sb800[6];
-
extern u32 apicid_sb800;
-
u8 intr_data[] = {
[0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* INTA# - INTH# */
[0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, /* Misc-nil,0,1,2, INT from Serial irq */
@@ -108,27 +105,27 @@ static void *smp_write_config_table(void *v)
/* on board NIC & Slot PCIE. */
/* PCI slots */
- /* PCI_SLOT 0. */
- PCI_INT(bus_sb800[1], 0x5, 0x0, 0x14);
- PCI_INT(bus_sb800[1], 0x5, 0x1, 0x15);
- PCI_INT(bus_sb800[1], 0x5, 0x2, 0x16);
- PCI_INT(bus_sb800[1], 0x5, 0x3, 0x17);
-
- /* PCI_SLOT 1. */
- PCI_INT(bus_sb800[1], 0x6, 0x0, 0x15);
- PCI_INT(bus_sb800[1], 0x6, 0x1, 0x16);
- PCI_INT(bus_sb800[1], 0x6, 0x2, 0x17);
- PCI_INT(bus_sb800[1], 0x6, 0x3, 0x14);
-
- /* PCI_SLOT 2. */
- PCI_INT(bus_sb800[1], 0x7, 0x0, 0x16);
- PCI_INT(bus_sb800[1], 0x7, 0x1, 0x17);
- PCI_INT(bus_sb800[1], 0x7, 0x2, 0x14);
- PCI_INT(bus_sb800[1], 0x7, 0x3, 0x15);
-
- PCI_INT(bus_sb800[2], 0x0, 0x0, 0x12);
- PCI_INT(bus_sb800[2], 0x0, 0x1, 0x13);
- PCI_INT(bus_sb800[2], 0x0, 0x2, 0x14);
+ device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
+ if (dev && dev->enabled) {
+ u8 bus_pci = dev->link_list->secondary;
+ /* PCI_SLOT 0. */
+ PCI_INT(bus_pci, 0x5, 0x0, 0x14);
+ PCI_INT(bus_pci, 0x5, 0x1, 0x15);
+ PCI_INT(bus_pci, 0x5, 0x2, 0x16);
+ PCI_INT(bus_pci, 0x5, 0x3, 0x17);
+
+ /* PCI_SLOT 1. */
+ PCI_INT(bus_pci, 0x6, 0x0, 0x15);
+ PCI_INT(bus_pci, 0x6, 0x1, 0x16);
+ PCI_INT(bus_pci, 0x6, 0x2, 0x17);
+ PCI_INT(bus_pci, 0x6, 0x3, 0x14);
+
+ /* PCI_SLOT 2. */
+ PCI_INT(bus_pci, 0x7, 0x0, 0x16);
+ PCI_INT(bus_pci, 0x7, 0x1, 0x17);
+ PCI_INT(bus_pci, 0x7, 0x2, 0x14);
+ PCI_INT(bus_pci, 0x7, 0x3, 0x15);
+ }
/* PCIe PortA */
PCI_INT(0x0, 0x15, 0x0, 0x10);
diff --git a/src/mainboard/lippert/toucan-af/mptable.c b/src/mainboard/lippert/toucan-af/mptable.c
index 8b57167..f5de39e 100644
--- a/src/mainboard/lippert/toucan-af/mptable.c
+++ b/src/mainboard/lippert/toucan-af/mptable.c
@@ -27,11 +27,8 @@
#include <cpu/amd/amdfam14.h>
#include <SBPLATFORM.h>
-extern u8 bus_sb800[6];
-
extern u32 apicid_sb800;
-
u8 intr_data[] = {
[0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* INTA# - INTH# */
[0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, /* Misc-nil,0,1,2, INT from Serial irq */
@@ -108,27 +105,27 @@ static void *smp_write_config_table(void *v)
/* on board NIC & Slot PCIE. */
/* PCI slots */
- /* PCI_SLOT 0. */
- PCI_INT(bus_sb800[1], 0x5, 0x0, 0x14);
- PCI_INT(bus_sb800[1], 0x5, 0x1, 0x15);
- PCI_INT(bus_sb800[1], 0x5, 0x2, 0x16);
- PCI_INT(bus_sb800[1], 0x5, 0x3, 0x17);
-
- /* PCI_SLOT 1. */
- PCI_INT(bus_sb800[1], 0x6, 0x0, 0x15);
- PCI_INT(bus_sb800[1], 0x6, 0x1, 0x16);
- PCI_INT(bus_sb800[1], 0x6, 0x2, 0x17);
- PCI_INT(bus_sb800[1], 0x6, 0x3, 0x14);
-
- /* PCI_SLOT 2. */
- PCI_INT(bus_sb800[1], 0x7, 0x0, 0x16);
- PCI_INT(bus_sb800[1], 0x7, 0x1, 0x17);
- PCI_INT(bus_sb800[1], 0x7, 0x2, 0x14);
- PCI_INT(bus_sb800[1], 0x7, 0x3, 0x15);
-
- PCI_INT(bus_sb800[2], 0x0, 0x0, 0x12);
- PCI_INT(bus_sb800[2], 0x0, 0x1, 0x13);
- PCI_INT(bus_sb800[2], 0x0, 0x2, 0x14);
+ device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
+ if (dev && dev->enabled) {
+ u8 bus_pci = dev->link_list->secondary;
+ /* PCI_SLOT 0. */
+ PCI_INT(bus_pci, 0x5, 0x0, 0x14);
+ PCI_INT(bus_pci, 0x5, 0x1, 0x15);
+ PCI_INT(bus_pci, 0x5, 0x2, 0x16);
+ PCI_INT(bus_pci, 0x5, 0x3, 0x17);
+
+ /* PCI_SLOT 1. */
+ PCI_INT(bus_pci, 0x6, 0x0, 0x15);
+ PCI_INT(bus_pci, 0x6, 0x1, 0x16);
+ PCI_INT(bus_pci, 0x6, 0x2, 0x17);
+ PCI_INT(bus_pci, 0x6, 0x3, 0x14);
+
+ /* PCI_SLOT 2. */
+ PCI_INT(bus_pci, 0x7, 0x0, 0x16);
+ PCI_INT(bus_pci, 0x7, 0x1, 0x17);
+ PCI_INT(bus_pci, 0x7, 0x2, 0x14);
+ PCI_INT(bus_pci, 0x7, 0x3, 0x15);
+ }
/* PCIe PortA */
PCI_INT(0x0, 0x15, 0x0, 0x10);
diff --git a/src/mainboard/supermicro/h8qgi/mptable.c b/src/mainboard/supermicro/h8qgi/mptable.c
index 3793212..5ec4a35 100644
--- a/src/mainboard/supermicro/h8qgi/mptable.c
+++ b/src/mainboard/supermicro/h8qgi/mptable.c
@@ -28,8 +28,6 @@
#include <cpu/x86/lapic.h>
#include <cpu/amd/amdfam10_sysconf.h>
-extern u8 bus_sp5100[2];
-
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
@@ -142,24 +140,27 @@ static void *smp_write_config_table(void *v)
PCI_INT(0x0, 0x11, 0x0, 0x16); //6, INTG
/* PCI slots */
- /* PCI_SLOT 0. */
- PCI_INT(bus_sp5100[1], 0x5, 0x0, 0x14);
- PCI_INT(bus_sp5100[1], 0x5, 0x1, 0x15);
- PCI_INT(bus_sp5100[1], 0x5, 0x2, 0x16);
- PCI_INT(bus_sp5100[1], 0x5, 0x3, 0x17);
-
- /* PCI_SLOT 1. */
- PCI_INT(bus_sp5100[1], 0x6, 0x0, 0x15);
- PCI_INT(bus_sp5100[1], 0x6, 0x1, 0x16);
- PCI_INT(bus_sp5100[1], 0x6, 0x2, 0x17);
- PCI_INT(bus_sp5100[1], 0x6, 0x3, 0x14);
-
- /* PCI_SLOT 2. */
- PCI_INT(bus_sp5100[1], 0x7, 0x0, 0x16);
- PCI_INT(bus_sp5100[1], 0x7, 0x1, 0x17);
- PCI_INT(bus_sp5100[1], 0x7, 0x2, 0x14);
- PCI_INT(bus_sp5100[1], 0x7, 0x3, 0x15);
-
+ dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
+ if (dev && dev->enabled) {
+ u8 bus_pci = dev->link_list->secondary;
+ /* PCI_SLOT 0. */
+ PCI_INT(bus_pci, 0x5, 0x0, 0x14);
+ PCI_INT(bus_pci, 0x5, 0x1, 0x15);
+ PCI_INT(bus_pci, 0x5, 0x2, 0x16);
+ PCI_INT(bus_pci, 0x5, 0x3, 0x17);
+
+ /* PCI_SLOT 1. */
+ PCI_INT(bus_pci, 0x6, 0x0, 0x15);
+ PCI_INT(bus_pci, 0x6, 0x1, 0x16);
+ PCI_INT(bus_pci, 0x6, 0x2, 0x17);
+ PCI_INT(bus_pci, 0x6, 0x3, 0x14);
+
+ /* PCI_SLOT 2. */
+ PCI_INT(bus_pci, 0x7, 0x0, 0x16);
+ PCI_INT(bus_pci, 0x7, 0x1, 0x17);
+ PCI_INT(bus_pci, 0x7, 0x2, 0x14);
+ PCI_INT(bus_pci, 0x7, 0x3, 0x15);
+ }
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0);
diff --git a/src/mainboard/supermicro/h8scm/mptable.c b/src/mainboard/supermicro/h8scm/mptable.c
index 3793212..5ec4a35 100644
--- a/src/mainboard/supermicro/h8scm/mptable.c
+++ b/src/mainboard/supermicro/h8scm/mptable.c
@@ -28,8 +28,6 @@
#include <cpu/x86/lapic.h>
#include <cpu/amd/amdfam10_sysconf.h>
-extern u8 bus_sp5100[2];
-
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
@@ -142,24 +140,27 @@ static void *smp_write_config_table(void *v)
PCI_INT(0x0, 0x11, 0x0, 0x16); //6, INTG
/* PCI slots */
- /* PCI_SLOT 0. */
- PCI_INT(bus_sp5100[1], 0x5, 0x0, 0x14);
- PCI_INT(bus_sp5100[1], 0x5, 0x1, 0x15);
- PCI_INT(bus_sp5100[1], 0x5, 0x2, 0x16);
- PCI_INT(bus_sp5100[1], 0x5, 0x3, 0x17);
-
- /* PCI_SLOT 1. */
- PCI_INT(bus_sp5100[1], 0x6, 0x0, 0x15);
- PCI_INT(bus_sp5100[1], 0x6, 0x1, 0x16);
- PCI_INT(bus_sp5100[1], 0x6, 0x2, 0x17);
- PCI_INT(bus_sp5100[1], 0x6, 0x3, 0x14);
-
- /* PCI_SLOT 2. */
- PCI_INT(bus_sp5100[1], 0x7, 0x0, 0x16);
- PCI_INT(bus_sp5100[1], 0x7, 0x1, 0x17);
- PCI_INT(bus_sp5100[1], 0x7, 0x2, 0x14);
- PCI_INT(bus_sp5100[1], 0x7, 0x3, 0x15);
-
+ dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
+ if (dev && dev->enabled) {
+ u8 bus_pci = dev->link_list->secondary;
+ /* PCI_SLOT 0. */
+ PCI_INT(bus_pci, 0x5, 0x0, 0x14);
+ PCI_INT(bus_pci, 0x5, 0x1, 0x15);
+ PCI_INT(bus_pci, 0x5, 0x2, 0x16);
+ PCI_INT(bus_pci, 0x5, 0x3, 0x17);
+
+ /* PCI_SLOT 1. */
+ PCI_INT(bus_pci, 0x6, 0x0, 0x15);
+ PCI_INT(bus_pci, 0x6, 0x1, 0x16);
+ PCI_INT(bus_pci, 0x6, 0x2, 0x17);
+ PCI_INT(bus_pci, 0x6, 0x3, 0x14);
+
+ /* PCI_SLOT 2. */
+ PCI_INT(bus_pci, 0x7, 0x0, 0x16);
+ PCI_INT(bus_pci, 0x7, 0x1, 0x17);
+ PCI_INT(bus_pci, 0x7, 0x2, 0x14);
+ PCI_INT(bus_pci, 0x7, 0x3, 0x15);
+ }
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0);
diff --git a/src/mainboard/tyan/s8226/mptable.c b/src/mainboard/tyan/s8226/mptable.c
index 3793212..5ec4a35 100644
--- a/src/mainboard/tyan/s8226/mptable.c
+++ b/src/mainboard/tyan/s8226/mptable.c
@@ -28,8 +28,6 @@
#include <cpu/x86/lapic.h>
#include <cpu/amd/amdfam10_sysconf.h>
-extern u8 bus_sp5100[2];
-
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
@@ -142,24 +140,27 @@ static void *smp_write_config_table(void *v)
PCI_INT(0x0, 0x11, 0x0, 0x16); //6, INTG
/* PCI slots */
- /* PCI_SLOT 0. */
- PCI_INT(bus_sp5100[1], 0x5, 0x0, 0x14);
- PCI_INT(bus_sp5100[1], 0x5, 0x1, 0x15);
- PCI_INT(bus_sp5100[1], 0x5, 0x2, 0x16);
- PCI_INT(bus_sp5100[1], 0x5, 0x3, 0x17);
-
- /* PCI_SLOT 1. */
- PCI_INT(bus_sp5100[1], 0x6, 0x0, 0x15);
- PCI_INT(bus_sp5100[1], 0x6, 0x1, 0x16);
- PCI_INT(bus_sp5100[1], 0x6, 0x2, 0x17);
- PCI_INT(bus_sp5100[1], 0x6, 0x3, 0x14);
-
- /* PCI_SLOT 2. */
- PCI_INT(bus_sp5100[1], 0x7, 0x0, 0x16);
- PCI_INT(bus_sp5100[1], 0x7, 0x1, 0x17);
- PCI_INT(bus_sp5100[1], 0x7, 0x2, 0x14);
- PCI_INT(bus_sp5100[1], 0x7, 0x3, 0x15);
-
+ dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
+ if (dev && dev->enabled) {
+ u8 bus_pci = dev->link_list->secondary;
+ /* PCI_SLOT 0. */
+ PCI_INT(bus_pci, 0x5, 0x0, 0x14);
+ PCI_INT(bus_pci, 0x5, 0x1, 0x15);
+ PCI_INT(bus_pci, 0x5, 0x2, 0x16);
+ PCI_INT(bus_pci, 0x5, 0x3, 0x17);
+
+ /* PCI_SLOT 1. */
+ PCI_INT(bus_pci, 0x6, 0x0, 0x15);
+ PCI_INT(bus_pci, 0x6, 0x1, 0x16);
+ PCI_INT(bus_pci, 0x6, 0x2, 0x17);
+ PCI_INT(bus_pci, 0x6, 0x3, 0x14);
+
+ /* PCI_SLOT 2. */
+ PCI_INT(bus_pci, 0x7, 0x0, 0x16);
+ PCI_INT(bus_pci, 0x7, 0x1, 0x17);
+ PCI_INT(bus_pci, 0x7, 0x2, 0x14);
+ PCI_INT(bus_pci, 0x7, 0x3, 0x15);
+ }
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0);
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