[coreboot-gerrit] New patch to review for coreboot: ffebe5f southbridge/via: Remove a trailing whitespace

[HAOUAS Elyes (ehaouas@noos.fr)]

HAOUAS Elyes (ehaouas at noos.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6345

-gerrit

commit ffebe5f52a276c6525161c0641f55772a9b8e5a8
Author: Elyes HAOUAS <ehaouas at noos.fr>
Date:   Tue Jul 22 20:01:10 2014 +0200

    southbridge/via: Remove a trailing whitespace
    
    Change-Id: I28deda21a7070ea6f14f973b66fd5dd119bc6225
    Signed-off-by: Elyes HAOUAS <ehaouas at noos.fr>
---
 src/southbridge/via/vt8235/early_smbus.c |  4 ++--
 src/southbridge/via/vt8237r/vt8237r.h    | 36 ++++++++++++++++----------------
 2 files changed, 20 insertions(+), 20 deletions(-)

diff --git a/src/southbridge/via/vt8235/early_smbus.c b/src/southbridge/via/vt8235/early_smbus.c
index 96da2fa..0d484f3 100644
--- a/src/southbridge/via/vt8235/early_smbus.c
+++ b/src/southbridge/via/vt8235/early_smbus.c
@@ -21,8 +21,8 @@
 
 #define SMBUS_TIMEOUT (100*1000*10)
 
-#define  I2C_TRANS_CMD          0x40
-#define  CLOCK_SLAVE_ADDRESS    0x69
+#define I2C_TRANS_CMD          0x40
+#define CLOCK_SLAVE_ADDRESS    0x69
 
 static void enable_smbus(void)
 {
diff --git a/src/southbridge/via/vt8237r/vt8237r.h b/src/southbridge/via/vt8237r/vt8237r.h
index ee5cc82..1c50208 100644
--- a/src/southbridge/via/vt8237r/vt8237r.h
+++ b/src/southbridge/via/vt8237r/vt8237r.h
@@ -32,26 +32,26 @@
 
 /* PMBASE FIXME mostly taken from ich7 */
 #define PM1_STS		0x00
-#define   WAK_STS	(1 << 15)
-#define   PCIEXPWAK_STS	(1 << 14)
-#define   PRBTNOR_STS	(1 << 11)
-#define   RTC_STS	(1 << 10)
-#define   PWRBTN_STS	(1 << 8)
-#define   GBL_STS	(1 << 5)
-#define   BM_STS	(1 << 4)
-#define   TMROF_STS	(1 << 0)
+#define WAK_STS	(1 << 15)
+#define PCIEXPWAK_STS	(1 << 14)
+#define PRBTNOR_STS	(1 << 11)
+#define RTC_STS	(1 << 10)
+#define PWRBTN_STS	(1 << 8)
+#define GBL_STS	(1 << 5)
+#define BM_STS	(1 << 4)
+#define TMROF_STS	(1 << 0)
 #define PM1_EN		0x02
-#define   PCIEXPWAK_DIS	(1 << 14)
-#define   RTC_EN	(1 << 10)
-#define   PWRBTN_EN	(1 << 8)
-#define   GBL_EN	(1 << 5)
-#define   TMROF_EN	(1 << 0)
+#define PCIEXPWAK_DIS	(1 << 14)
+#define RTC_EN	(1 << 10)
+#define PWRBTN_EN	(1 << 8)
+#define GBL_EN	(1 << 5)
+#define TMROF_EN	(1 << 0)
 #define PM1_CNT		0x04
-#define   SLP_EN	(1 << 13)
-#define   SLP_TYP	(7 << 10)
-#define   GBL_RLS	(1 << 2)
-#define   BM_RLD	(1 << 1)
-#define   SCI_EN	(1 << 0)
+#define SLP_EN	(1 << 13)
+#define SLP_TYP	(7 << 10)
+#define GBL_RLS	(1 << 2)
+#define BM_RLD	(1 << 1)
+#define SCI_EN	(1 << 0)
 #define PM1_TMR		0x08
 #define PROC_CNT	0x10
 #define LV2		0x14