[coreboot-gerrit] New patch to review for coreboot: 4c94cbf southbridge/amd: Remove a trailing whitespace

[HAOUAS Elyes (ehaouas@noos.fr)]

HAOUAS Elyes (ehaouas at noos.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6334

-gerrit

commit 4c94cbfc3388fbfdaff2cf722889b92524488eb8
Author: Elyes HAOUAS <ehaouas at noos.fr>
Date:   Tue Jul 22 19:16:18 2014 +0200

    southbridge/amd: Remove a trailing whitespace
    
    Change-Id: I25cdfe6b3c8067793620677c62251e78704f7851
    Signed-off-by: Elyes HAOUAS <ehaouas at noos.fr>
---
 src/southbridge/amd/agesa/hudson/early_setup.c | 2 +-
 src/southbridge/amd/agesa/hudson/smbus.c       | 2 +-
 src/southbridge/amd/cimx/sb800/SBPLATFORM.h    | 2 +-
 src/southbridge/amd/cimx/sb900/SbPlatform.h    | 2 +-
 src/southbridge/amd/rs690/rs690.h              | 6 +++---
 src/southbridge/amd/rs780/rs780.h              | 6 +++---
 src/southbridge/amd/sb800/early_setup.c        | 2 +-
 src/southbridge/amd/sb800/smbus.c              | 2 +-
 8 files changed, 12 insertions(+), 12 deletions(-)

diff --git a/src/southbridge/amd/agesa/hudson/early_setup.c b/src/southbridge/amd/agesa/hudson/early_setup.c
index d8fdc27..7f1026a 100644
--- a/src/southbridge/amd/agesa/hudson/early_setup.c
+++ b/src/southbridge/amd/agesa/hudson/early_setup.c
@@ -18,7 +18,7 @@
  */
 
 #ifndef  _HUDSON_EARLY_SETUP_C_
-#define  _HUDSON_EARLY_SETUP_C_
+#define _HUDSON_EARLY_SETUP_C_
 
 #include <stdint.h>
 #include <arch/io.h>
diff --git a/src/southbridge/amd/agesa/hudson/smbus.c b/src/southbridge/amd/agesa/hudson/smbus.c
index 0c04158..e5f8e49 100644
--- a/src/southbridge/amd/agesa/hudson/smbus.c
+++ b/src/southbridge/amd/agesa/hudson/smbus.c
@@ -18,7 +18,7 @@
  */
 
 #ifndef  _HUDSON_SMBUS_C_
-#define  _HUDSON_SMBUS_C_
+#define _HUDSON_SMBUS_C_
 
 #include <io.h>
 #include <stdint.h>
diff --git a/src/southbridge/amd/cimx/sb800/SBPLATFORM.h b/src/southbridge/amd/cimx/sb800/SBPLATFORM.h
index ea3f719..f20b7dc 100644
--- a/src/southbridge/amd/cimx/sb800/SBPLATFORM.h
+++ b/src/southbridge/amd/cimx/sb800/SBPLATFORM.h
@@ -22,7 +22,7 @@
  */
 
 #ifndef  _AMD_SBPLATFORM_H_
-#define  _AMD_SBPLATFORM_H_
+#define _AMD_SBPLATFORM_H_
 
 #include <stddef.h>
 
diff --git a/src/southbridge/amd/cimx/sb900/SbPlatform.h b/src/southbridge/amd/cimx/sb900/SbPlatform.h
index 176ad87..ad56870 100644
--- a/src/southbridge/amd/cimx/sb900/SbPlatform.h
+++ b/src/southbridge/amd/cimx/sb900/SbPlatform.h
@@ -22,7 +22,7 @@
  */
 
 #ifndef  _AMD_SBPLATFORM_H_
-#define  _AMD_SBPLATFORM_H_
+#define _AMD_SBPLATFORM_H_
 
 #include <stddef.h>
 
diff --git a/src/southbridge/amd/rs690/rs690.h b/src/southbridge/amd/rs690/rs690.h
index 9f143d4..2cc5e48 100644
--- a/src/southbridge/amd/rs690/rs690.h
+++ b/src/southbridge/amd/rs690/rs690.h
@@ -82,16 +82,16 @@ typedef enum _NB_REVISION_ {
  ------------------- -----------------------*/
 #define	PCIE_CI_CNTL			0x20
 #define	PCIE_LC_LINK_WIDTH		0xa2
-#define   PCIE_LC_STATE0			0xa5
+#define PCIE_LC_STATE0			0xa5
 #define	PCIE_VC0_RESOURCE_STATUS	0x11a	/* 16bit read only */
 
 #define	PCIE_CORE_INDEX_GFX			(0 << 16) /* see 5.2.2 */
 #define	PCIE_CORE_INDEX_GPPSB		(1 << 16)
 
 /* contents of PCIE_NBCFG_REG7 */
-#define   RECONFIG_GPPSB_EN			(1 << 12)
+#define RECONFIG_GPPSB_EN			(1 << 12)
 #define	RECONFIG_GPPSB_GPPSB			(1 << 14)
-#define   RECONFIG_GPPSB_LINK_CONFIG		(1 << 15)
+#define RECONFIG_GPPSB_LINK_CONFIG		(1 << 15)
 #define	RECONFIG_GPPSB_ATOMIC_RESET		(1 << 17)
 
 /* contents of PCIE_VC0_RESOURCE_STATUS */
diff --git a/src/southbridge/amd/rs780/rs780.h b/src/southbridge/amd/rs780/rs780.h
index c44a813..1d72c45 100644
--- a/src/southbridge/amd/rs780/rs780.h
+++ b/src/southbridge/amd/rs780/rs780.h
@@ -150,7 +150,7 @@ typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V2
  ------------------- -----------------------*/
 #define	PCIE_CI_CNTL			0x20
 #define	PCIE_LC_LINK_WIDTH		0xa2
-#define   PCIE_LC_STATE0			0xa5
+#define PCIE_LC_STATE0			0xa5
 #define	PCIE_VC0_RESOURCE_STATUS	0x12a	/* 16bit read only */
 
 #define	PCIE_CORE_INDEX_GFX		(0x00 << 16) /* see 5.2.2 */
@@ -159,9 +159,9 @@ typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V2
 #define	PCIE_CORE_INDEX_BRDCST		(0x03 << 16)
 
 /* contents of PCIE_NBCFG_REG7 */
-#define   RECONFIG_GPPSB_EN			(1 << 12)
+#define RECONFIG_GPPSB_EN			(1 << 12)
 #define	RECONFIG_GPPSB_GPPSB			(1 << 14)
-#define   RECONFIG_GPPSB_LINK_CONFIG		(1 << 15)
+#define RECONFIG_GPPSB_LINK_CONFIG		(1 << 15)
 #define	RECONFIG_GPPSB_ATOMIC_RESET		(1 << 17)
 
 /* contents of PCIE_VC0_RESOURCE_STATUS */
diff --git a/src/southbridge/amd/sb800/early_setup.c b/src/southbridge/amd/sb800/early_setup.c
index ef0548c..f079473 100644
--- a/src/southbridge/amd/sb800/early_setup.c
+++ b/src/southbridge/amd/sb800/early_setup.c
@@ -18,7 +18,7 @@
  */
 
 #ifndef  _SB800_EARLY_SETUP_C_
-#define  _SB800_EARLY_SETUP_C_
+#define _SB800_EARLY_SETUP_C_
 
 #include <reset.h>
 #include <arch/acpi.h>
diff --git a/src/southbridge/amd/sb800/smbus.c b/src/southbridge/amd/sb800/smbus.c
index c1a9ded..513a56a 100644
--- a/src/southbridge/amd/sb800/smbus.c
+++ b/src/southbridge/amd/sb800/smbus.c
@@ -18,7 +18,7 @@
  */
 
 #ifndef  _SB800_SMBUS_C_
-#define  _SB800_SMBUS_C_
+#define _SB800_SMBUS_C_
 
 #include "smbus.h"