[coreboot-gerrit] Patch merged into coreboot/master: 9f0a2be AMD SPI: Optimise for longer writes

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit 9f0a2be1658cf6d329aefac2660a53a465312468
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date:   Mon Jun 30 07:34:36 2014 +0300

    AMD SPI: Optimise for longer writes
    
    Leave it to the implementation of flash->write() to split the writes
    to match SPI controller and SPI flash part restrictions. This allows
    for some optimisation for auto-address-increment (AAI) commands.
    
    Kconfig AMD_SB_SPI_TX_LEN can be kept as local.
    
    Change-Id: I4a8bc55ab7eb0eeda8f25003a8f5ff2a643ab7a7
    Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
    Reviewed-on: http://review.coreboot.org/6164
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan at alterapraxis.com>


See http://review.coreboot.org/6164 for details.

-gerrit