[coreboot-gerrit] Patch set updated for coreboot: 954c27c AMD SPI: Optimise for longer writes

[Kyösti Mälkki (kyosti.malkki@gmail.com)]

Kyösti Mälkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6164

-gerrit

commit 954c27cdfb6cd0851ebb57c03a5e3b87b94569e6
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date:   Mon Jun 30 07:34:36 2014 +0300

    AMD SPI: Optimise for longer writes
    
    Leave it to the implementation of flash->write() to split the writes
    to match SPI controller and SPI flash part restrictions. This allows
    for some optimisation for auto-address-increment (AAI) commands.
    
    Kconfig AMD_SB_SPI_TX_LEN can be kept as local.
    
    Change-Id: I4a8bc55ab7eb0eeda8f25003a8f5ff2a643ab7a7
    Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
---
 src/cpu/amd/agesa/spi.c                |  7 +------
 src/southbridge/amd/Kconfig            |  9 ---------
 src/southbridge/amd/agesa/hudson/spi.c | 15 +++++++++++++++
 src/southbridge/amd/cimx/sb800/spi.c   | 14 ++++++++++++++
 4 files changed, 30 insertions(+), 15 deletions(-)

diff --git a/src/cpu/amd/agesa/spi.c b/src/cpu/amd/agesa/spi.c
index 5631053..1c652fd 100644
--- a/src/cpu/amd/agesa/spi.c
+++ b/src/cpu/amd/agesa/spi.c
@@ -40,12 +40,7 @@ void spi_SaveS3info(u32 pos, u32 size, u8 *buf, u32 len)
 
 	flash->erase(flash, pos, size);
 	flash->write(flash, pos, sizeof(len), &len);
-
-	u32 nvram_pos;
-	for (nvram_pos = 0; nvram_pos < len - CONFIG_AMD_SB_SPI_TX_LEN; nvram_pos += CONFIG_AMD_SB_SPI_TX_LEN) {
-		flash->write(flash, nvram_pos + pos + 4, CONFIG_AMD_SB_SPI_TX_LEN, (u8 *)(buf + nvram_pos));
-	}
-	flash->write(flash, nvram_pos + pos + 4, len % CONFIG_AMD_SB_SPI_TX_LEN, (u8 *)(buf + nvram_pos));
+	flash->write(flash, pos + sizeof(len), len, buf);
 
 	flash->spi->rw = SPI_WRITE_FLAG;
 	spi_release_bus(flash->spi);
diff --git a/src/southbridge/amd/Kconfig b/src/southbridge/amd/Kconfig
index 39aeb09..867afca 100644
--- a/src/southbridge/amd/Kconfig
+++ b/src/southbridge/amd/Kconfig
@@ -14,12 +14,3 @@ source src/southbridge/amd/sb800/Kconfig
 source src/southbridge/amd/cimx/Kconfig
 source src/southbridge/amd/agesa/Kconfig
 source src/southbridge/amd/sr5650/Kconfig
-
-if CPU_AMD_AGESA
-
-config AMD_SB_SPI_TX_LEN
-	int
-	default 4
-	depends on SPI_FLASH
-
-endif
diff --git a/src/southbridge/amd/agesa/hudson/spi.c b/src/southbridge/amd/agesa/hudson/spi.c
index f050a63..2aeb2c0 100644
--- a/src/southbridge/amd/agesa/hudson/spi.c
+++ b/src/southbridge/amd/agesa/hudson/spi.c
@@ -20,6 +20,7 @@
 #include <stdlib.h>
 #include <string.h>
 #include <arch/io.h>
+#include <console/console.h>
 #include <spi-generic.h>
 #include <device/device.h>
 #include <device/pci.h>
@@ -101,6 +102,20 @@ int spi_xfer(struct spi_slave *slave, const void *dout,
 	u8 count;
 
 	bytesout--;
+
+	/*
+	 * Check if this is a write command attempting to transfer more bytes
+	 * than the controller can handle. Iterations for writes are not
+	 * supported here because each SPI write command needs to be preceded
+	 * and followed by other SPI commands, and this sequence is controlled
+	 * by the SPI chip driver.
+	 */
+	if (bytesout > AMD_SB_SPI_TX_LEN) {
+		printk(BIOS_DEBUG, "FCH SPI: Too much to write. Does your SPI chip driver use"
+		     " spi_crop_chunk()?\n");
+		return -1;
+	}
+
 	readoffby1 = bytesout ? 0 : 1;
 
 #if CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE
diff --git a/src/southbridge/amd/cimx/sb800/spi.c b/src/southbridge/amd/cimx/sb800/spi.c
index e5b2407..f38e691 100644
--- a/src/southbridge/amd/cimx/sb800/spi.c
+++ b/src/southbridge/amd/cimx/sb800/spi.c
@@ -20,6 +20,7 @@
 #include <stdlib.h>
 #include <string.h>
 #include <arch/io.h>
+#include <console/console.h>
 #include <spi-generic.h>
 #include <device/device.h>
 #include <device/pci.h>
@@ -74,6 +75,19 @@ int spi_xfer(struct spi_slave *slave, const void *dout,
 
 	bytesout--;
 
+	/*
+	 * Check if this is a write command attempting to transfer more bytes
+	 * than the controller can handle. Iterations for writes are not
+	 * supported here because each SPI write command needs to be preceded
+	 * and followed by other SPI commands, and this sequence is controlled
+	 * by the SPI chip driver.
+	 */
+	if (bytesout > AMD_SB_SPI_TX_LEN) {
+		printk(BIOS_DEBUG, "FCH SPI: Too much to write. Does your SPI chip driver use"
+		     " spi_crop_chunk()?\n");
+		return -1;
+	}
+
 	readoffby1 = bytesout ? 0 : 1;
 
 	readwrite = (bytesin + readoffby1) << 4 | bytesout;