[coreboot-gerrit] New patch to review for coreboot: 7009236 northbridge: Trivial - drop trailing blank lines at EOF
Edward O'Callaghan (eocallaghan@alterapraxis.com)
gerrit at coreboot.org
Mon Jul 7 16:02:41 CEST 2014
Edward O'Callaghan (eocallaghan at alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6210
-gerrit
commit 70092365239fc02aebd0983b7b15ebd26c414716
Author: Edward O'Callaghan <eocallaghan at alterapraxis.com>
Date: Mon Jul 7 23:54:59 2014 +1000
northbridge: Trivial - drop trailing blank lines at EOF
Change-Id: I9515778e97cc5ae0e366b888da90a651ae5994fe
Signed-off-by: Edward O'Callaghan <eocallaghan at alterapraxis.com>
---
src/northbridge/amd/agesa/family10/northbridge.c | 1 -
src/northbridge/amd/agesa/family14/fam14_callouts.c | 1 -
src/northbridge/amd/agesa/family15/fam15_callouts.c | 1 -
src/northbridge/amd/amdfam10/nums.h | 1 -
src/northbridge/amd/amdfam10/pci.c | 2 --
src/northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c | 1 -
src/northbridge/amd/amdfam10/reset_test.c | 1 -
src/northbridge/amd/amdfam10/resourcemap.c | 1 -
src/northbridge/amd/amdfam10/setup_resource_map.c | 1 -
src/northbridge/amd/amdht/h3finit.h | 2 --
src/northbridge/amd/amdht/h3gtopo.h | 1 -
src/northbridge/amd/amdht/h3ncmn.c | 1 -
src/northbridge/amd/amdht/ht_wrapper.c | 4 ----
src/northbridge/amd/amdk8/acpi.c | 1 -
src/northbridge/amd/amdk8/coherent_ht.c | 1 -
src/northbridge/amd/amdk8/early_ht.c | 1 -
src/northbridge/amd/amdk8/get_sblk_pci1234.c | 1 -
src/northbridge/amd/amdk8/incoherent_ht.c | 3 ---
src/northbridge/amd/amdk8/reset_test.c | 1 -
src/northbridge/amd/amdk8/setup_resource_map.c | 1 -
src/northbridge/amd/amdmct/mct/mctardk3.c | 1 -
src/northbridge/amd/amdmct/mct/mctcsi_d.c | 2 --
src/northbridge/amd/amdmct/mct/mcttmrl.c | 2 --
src/northbridge/amd/amdmct/wrappers/mcti.h | 1 -
src/northbridge/amd/cimx/rd890/NbPlatform.h | 1 -
src/northbridge/amd/cimx/rd890/chip.h | 1 -
src/northbridge/amd/cimx/rd890/nb_cimx.h | 1 -
src/northbridge/amd/gx2/grphinit.c | 2 --
src/northbridge/amd/gx2/northbridgeinit.c | 1 -
src/northbridge/intel/e7505/debug.h | 1 -
src/northbridge/intel/e7505/e7505.h | 1 -
src/northbridge/intel/e7505/northbridge.c | 1 -
src/northbridge/intel/e7520/chip.h | 1 -
src/northbridge/intel/e7520/northbridge.h | 1 -
src/northbridge/intel/e7520/pciexp_porta.c | 2 --
src/northbridge/intel/e7520/pciexp_porta1.c | 2 --
src/northbridge/intel/e7520/pciexp_portb.c | 2 --
src/northbridge/intel/e7520/pciexp_portc.c | 2 --
src/northbridge/intel/e7525/chip.h | 1 -
src/northbridge/intel/e7525/northbridge.h | 1 -
src/northbridge/intel/e7525/pciexp_porta.c | 2 --
src/northbridge/intel/e7525/pciexp_porta1.c | 2 --
src/northbridge/intel/e7525/pciexp_portb.c | 2 --
src/northbridge/intel/e7525/pciexp_portc.c | 2 --
src/northbridge/intel/fsp_sandybridge/acpi.c | 2 --
src/northbridge/intel/fsp_sandybridge/chip.h | 1 -
src/northbridge/intel/fsp_sandybridge/gma.h | 1 -
src/northbridge/intel/gm45/early_init.c | 1 -
src/northbridge/intel/gm45/raminit_rcomp_calibration.c | 1 -
src/northbridge/intel/gm45/thermal.c | 1 -
src/northbridge/intel/haswell/acpi.c | 2 --
src/northbridge/intel/haswell/gma.h | 1 -
src/northbridge/intel/haswell/minihd.c | 1 -
src/northbridge/intel/haswell/mrccache.c | 1 -
src/northbridge/intel/i3100/chip.h | 1 -
src/northbridge/intel/i440bx/i440bx.h | 1 -
src/northbridge/intel/i440lx/i440lx.h | 1 -
src/northbridge/intel/i440lx/raminit.c | 1 -
src/northbridge/intel/i82830/i82830.h | 1 -
src/northbridge/intel/i855/raminit.c | 1 -
src/northbridge/intel/i945/acpi.c | 2 --
src/northbridge/intel/i945/early_init.c | 1 -
src/northbridge/intel/i945/gma.c | 1 -
src/northbridge/intel/i945/rcven.c | 1 -
src/northbridge/intel/nehalem/chip.h | 1 -
src/northbridge/intel/sandybridge/acpi.c | 2 --
src/northbridge/intel/sandybridge/chip.h | 1 -
src/northbridge/intel/sandybridge/gma.h | 1 -
src/northbridge/intel/sandybridge/mrccache.c | 1 -
src/northbridge/via/cx700/registers.h | 2 --
70 files changed, 93 deletions(-)
diff --git a/src/northbridge/amd/agesa/family10/northbridge.c b/src/northbridge/amd/agesa/family10/northbridge.c
index 73545a0..4b2d003 100644
--- a/src/northbridge/amd/agesa/family10/northbridge.c
+++ b/src/northbridge/amd/agesa/family10/northbridge.c
@@ -1440,4 +1440,3 @@ struct chip_operations northbridge_amd_agesa_family10_root_complex_ops = {
CHIP_NAME("AMD FAM10 Root Complex")
.enable_dev = root_complex_enable_dev,
};
-
diff --git a/src/northbridge/amd/agesa/family14/fam14_callouts.c b/src/northbridge/amd/agesa/family14/fam14_callouts.c
index 05d378d..3be5037 100644
--- a/src/northbridge/amd/agesa/family14/fam14_callouts.c
+++ b/src/northbridge/amd/agesa/family14/fam14_callouts.c
@@ -37,4 +37,3 @@ AGESA_STATUS BiosReadSpd (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
return Status;
}
-
diff --git a/src/northbridge/amd/agesa/family15/fam15_callouts.c b/src/northbridge/amd/agesa/family15/fam15_callouts.c
index 5aa50ef..3b65492 100644
--- a/src/northbridge/amd/agesa/family15/fam15_callouts.c
+++ b/src/northbridge/amd/agesa/family15/fam15_callouts.c
@@ -25,4 +25,3 @@
#include "heapManager.h"
#include <northbridge/amd/agesa/family15/dimmSpd.h>
#include <arch/io.h>
-
diff --git a/src/northbridge/amd/amdfam10/nums.h b/src/northbridge/amd/amdfam10/nums.h
index 8d30cc3..12bac5d 100644
--- a/src/northbridge/amd/amdfam10/nums.h
+++ b/src/northbridge/amd/amdfam10/nums.h
@@ -38,4 +38,3 @@
#define HC_POSSIBLE_NUM 32
#endif
-
diff --git a/src/northbridge/amd/amdfam10/pci.c b/src/northbridge/amd/amdfam10/pci.c
index b950b45..061359e 100644
--- a/src/northbridge/amd/amdfam10/pci.c
+++ b/src/northbridge/amd/amdfam10/pci.c
@@ -73,5 +73,3 @@ static void pci_write_config32_index_wait(device_t dev, u32 index_reg, u32 index
}
#endif
#endif
-
-
diff --git a/src/northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c b/src/northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c
index adf4d23..e3fecaa 100644
--- a/src/northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c
+++ b/src/northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c
@@ -80,4 +80,3 @@ static void fill_mem_ctrl(u32 controllers, struct mem_controller *ctrl_a, const
}
}
}
-
diff --git a/src/northbridge/amd/amdfam10/reset_test.c b/src/northbridge/amd/amdfam10/reset_test.c
index 46c934f..24f5397 100644
--- a/src/northbridge/amd/amdfam10/reset_test.c
+++ b/src/northbridge/amd/amdfam10/reset_test.c
@@ -168,4 +168,3 @@ u8 get_sbbusn(u8 sblk)
{
return node_link_to_bus(0, sblk);
}
-
diff --git a/src/northbridge/amd/amdfam10/resourcemap.c b/src/northbridge/amd/amdfam10/resourcemap.c
index 50d30a2..c545377 100644
--- a/src/northbridge/amd/amdfam10/resourcemap.c
+++ b/src/northbridge/amd/amdfam10/resourcemap.c
@@ -284,4 +284,3 @@ static void setup_default_resource_map(void)
max = ARRAY_SIZE(register_values);
setup_resource_map(register_values, max);
}
-
diff --git a/src/northbridge/amd/amdfam10/setup_resource_map.c b/src/northbridge/amd/amdfam10/setup_resource_map.c
index 2e1bff8..2eeca44 100644
--- a/src/northbridge/amd/amdfam10/setup_resource_map.c
+++ b/src/northbridge/amd/amdfam10/setup_resource_map.c
@@ -227,4 +227,3 @@ static void setup_io_resource_map(const u32 *register_values, u32 max)
}
}
#endif
-
diff --git a/src/northbridge/amd/amdht/h3finit.h b/src/northbridge/amd/amdht/h3finit.h
index e169456..136a5cf 100644
--- a/src/northbridge/amd/amdht/h3finit.h
+++ b/src/northbridge/amd/amdht/h3finit.h
@@ -609,5 +609,3 @@ void amdHtInitialize(AMD_HTBLOCK *pBlock);
#endif /* H3FINIT_H */
-
-
diff --git a/src/northbridge/amd/amdht/h3gtopo.h b/src/northbridge/amd/amdht/h3gtopo.h
index bcd3a41..624b0d8 100644
--- a/src/northbridge/amd/amdht/h3gtopo.h
+++ b/src/northbridge/amd/amdht/h3gtopo.h
@@ -357,4 +357,3 @@ void getAmdTopolist(u8 ***p);
#endif /* HTTOPO_H */
-
diff --git a/src/northbridge/amd/amdht/h3ncmn.c b/src/northbridge/amd/amdht/h3ncmn.c
index cba21b3..830ed1c 100644
--- a/src/northbridge/amd/amdht/h3ncmn.c
+++ b/src/northbridge/amd/amdht/h3ncmn.c
@@ -2219,4 +2219,3 @@ void newNorthBridge(u8 node, cNorthBridge *nb)
/* Update the initial limited key to the real one, which may include other matching info */
nb->compatibleKey = makeKey(node);
}
-
diff --git a/src/northbridge/amd/amdht/ht_wrapper.c b/src/northbridge/amd/amdht/ht_wrapper.c
index 8efd4cb..5742494 100644
--- a/src/northbridge/amd/amdht/ht_wrapper.c
+++ b/src/northbridge/amd/amdht/ht_wrapper.c
@@ -143,7 +143,3 @@ static void amd_ht_init(struct sys_info *sysinfo)
}
-
-
-
-
diff --git a/src/northbridge/amd/amdk8/acpi.c b/src/northbridge/amd/amdk8/acpi.c
index 2eb39c0..f7134f6 100644
--- a/src/northbridge/amd/amdk8/acpi.c
+++ b/src/northbridge/amd/amdk8/acpi.c
@@ -307,4 +307,3 @@ void update_ssdtx(void *ssdtx, int i)
/* FIXME: need to update the GSI id in the ssdtx too */
}
-
diff --git a/src/northbridge/amd/amdk8/coherent_ht.c b/src/northbridge/amd/amdk8/coherent_ht.c
index 22d74c2..5219d4c 100644
--- a/src/northbridge/amd/amdk8/coherent_ht.c
+++ b/src/northbridge/amd/amdk8/coherent_ht.c
@@ -1854,4 +1854,3 @@ static int setup_coherent_ht_domain(void)
return optimize_link_coherent_ht();
#endif
}
-
diff --git a/src/northbridge/amd/amdk8/early_ht.c b/src/northbridge/amd/amdk8/early_ht.c
index 2ecc0d0..6449f4b 100644
--- a/src/northbridge/amd/amdk8/early_ht.c
+++ b/src/northbridge/amd/amdk8/early_ht.c
@@ -140,4 +140,3 @@ out:
#endif
}
-
diff --git a/src/northbridge/amd/amdk8/get_sblk_pci1234.c b/src/northbridge/amd/amdk8/get_sblk_pci1234.c
index a4943bd..6fdc3c4 100644
--- a/src/northbridge/amd/amdk8/get_sblk_pci1234.c
+++ b/src/northbridge/amd/amdk8/get_sblk_pci1234.c
@@ -260,4 +260,3 @@ void get_sblk_pci1234(void)
}
}
-
diff --git a/src/northbridge/amd/amdk8/incoherent_ht.c b/src/northbridge/amd/amdk8/incoherent_ht.c
index c1509f0..9d92174 100644
--- a/src/northbridge/amd/amdk8/incoherent_ht.c
+++ b/src/northbridge/amd/amdk8/incoherent_ht.c
@@ -864,6 +864,3 @@ static int optimize_link_incoherent_ht(struct sys_info *sysinfo)
}
#endif
-
-
-
diff --git a/src/northbridge/amd/amdk8/reset_test.c b/src/northbridge/amd/amdk8/reset_test.c
index bee3faa..6ef3ec0 100644
--- a/src/northbridge/amd/amdk8/reset_test.c
+++ b/src/northbridge/amd/amdk8/reset_test.c
@@ -84,4 +84,3 @@ static inline unsigned get_sbbusn(unsigned sblk)
{
return node_link_to_bus(0, sblk);
}
-
diff --git a/src/northbridge/amd/amdk8/setup_resource_map.c b/src/northbridge/amd/amdk8/setup_resource_map.c
index 8d1052e..230459a 100644
--- a/src/northbridge/amd/amdk8/setup_resource_map.c
+++ b/src/northbridge/amd/amdk8/setup_resource_map.c
@@ -182,4 +182,3 @@ static void setup_mem_resource_map(const unsigned int *register_values, int max)
}
}
#endif
-
diff --git a/src/northbridge/amd/amdmct/mct/mctardk3.c b/src/northbridge/amd/amdmct/mct/mctardk3.c
index 9bc30fe..b70385b 100644
--- a/src/northbridge/amd/amdmct/mct/mctardk3.c
+++ b/src/northbridge/amd/amdmct/mct/mctardk3.c
@@ -203,4 +203,3 @@ static void Get_ChannelPS_Cfg0_D(u8 MAAdimms, u8 Speed, u8 MAAload,
p+=11;
}
}
-
diff --git a/src/northbridge/amd/amdmct/mct/mctcsi_d.c b/src/northbridge/amd/amdmct/mct/mctcsi_d.c
index 130a775..71f7829 100644
--- a/src/northbridge/amd/amdmct/mct/mctcsi_d.c
+++ b/src/northbridge/amd/amdmct/mct/mctcsi_d.c
@@ -143,5 +143,3 @@ void InterleaveBanks_D(struct MCTStatStruc *pMCTstat,
print_tx("InterleaveBanks_D: ErrCode ", pDCTstat->ErrCode);
print_t("InterleaveBanks_D: Done\n");
}
-
-
diff --git a/src/northbridge/amd/amdmct/mct/mcttmrl.c b/src/northbridge/amd/amdmct/mct/mcttmrl.c
index f94494d..03ebf97 100644
--- a/src/northbridge/amd/amdmct/mct/mcttmrl.c
+++ b/src/northbridge/amd/amdmct/mct/mcttmrl.c
@@ -409,5 +409,3 @@ u8 mct_GetStartMaxRdLat_D(struct MCTStatStruc *pMCTstat,
return val;
}
-
-
diff --git a/src/northbridge/amd/amdmct/wrappers/mcti.h b/src/northbridge/amd/amdmct/wrappers/mcti.h
index 100f932..a92fdb8 100644
--- a/src/northbridge/amd/amdmct/wrappers/mcti.h
+++ b/src/northbridge/amd/amdmct/wrappers/mcti.h
@@ -71,4 +71,3 @@ UPDATE AS NEEDED
#define MCT_TRNG_KEEPOUT_START 0x00000C00
#define MCT_TRNG_KEEPOUT_END 0x00000CFF
-
diff --git a/src/northbridge/amd/cimx/rd890/NbPlatform.h b/src/northbridge/amd/cimx/rd890/NbPlatform.h
index 29b5d64..20f7974 100644
--- a/src/northbridge/amd/cimx/rd890/NbPlatform.h
+++ b/src/northbridge/amd/cimx/rd890/NbPlatform.h
@@ -144,4 +144,3 @@
#define CIMX_NBPCIE_MISC 0xFFFFFFFF
#endif
-
diff --git a/src/northbridge/amd/cimx/rd890/chip.h b/src/northbridge/amd/cimx/rd890/chip.h
index 237d55c..d76ea82 100644
--- a/src/northbridge/amd/cimx/rd890/chip.h
+++ b/src/northbridge/amd/cimx/rd890/chip.h
@@ -32,4 +32,3 @@ struct northbridge_amd_cimx_rd890_config
};
#endif /* _CIMX_RD890_CHIP_H_ */
-
diff --git a/src/northbridge/amd/cimx/rd890/nb_cimx.h b/src/northbridge/amd/cimx/rd890/nb_cimx.h
index e09af0a..7466d9a 100644
--- a/src/northbridge/amd/cimx/rd890/nb_cimx.h
+++ b/src/northbridge/amd/cimx/rd890/nb_cimx.h
@@ -41,4 +41,3 @@ void nb_Pcie_Early_Init(void);
void nb_Pcie_Late_Init(void);
#endif//_RD890_EARLY_H_
-
diff --git a/src/northbridge/amd/gx2/grphinit.c b/src/northbridge/amd/gx2/grphinit.c
index d7e2c08..b58519f 100644
--- a/src/northbridge/amd/gx2/grphinit.c
+++ b/src/northbridge/amd/gx2/grphinit.c
@@ -87,5 +87,3 @@ void graphics_init(void)
res = vrRead(wClassIndex);
printk(BIOS_DEBUG, "VRC_VG value: 0x%04x\n", res);
}
-
-
diff --git a/src/northbridge/amd/gx2/northbridgeinit.c b/src/northbridge/amd/gx2/northbridgeinit.c
index ef5277c..136dcf2 100644
--- a/src/northbridge/amd/gx2/northbridgeinit.c
+++ b/src/northbridge/amd/gx2/northbridgeinit.c
@@ -675,4 +675,3 @@ void northbridge_init_early(void)
__asm__ __volatile__("FINIT\n");
printk(BIOS_DEBUG, "Exit %s\n", __func__);
}
-
diff --git a/src/northbridge/intel/e7505/debug.h b/src/northbridge/intel/e7505/debug.h
index a517fc0..2b060e6 100644
--- a/src/northbridge/intel/e7505/debug.h
+++ b/src/northbridge/intel/e7505/debug.h
@@ -12,4 +12,3 @@ void dump_io_resources(unsigned port);
void dump_mem(unsigned start, unsigned end);
#endif
-
diff --git a/src/northbridge/intel/e7505/e7505.h b/src/northbridge/intel/e7505/e7505.h
index 456a0a9..08b681a 100644
--- a/src/northbridge/intel/e7505/e7505.h
+++ b/src/northbridge/intel/e7505/e7505.h
@@ -82,4 +82,3 @@
#define NERR_GLOBAL 0x44 /* Next global error register, 32 bits */
#define DRAM_FERR 0x80 /* DRAM first error register, 8 bits */
#define DRAM_NERR 0x82 /* DRAM next error register, 8 bits */
-
diff --git a/src/northbridge/intel/e7505/northbridge.c b/src/northbridge/intel/e7505/northbridge.c
index a63029b..8f1632d 100644
--- a/src/northbridge/intel/e7505/northbridge.c
+++ b/src/northbridge/intel/e7505/northbridge.c
@@ -142,4 +142,3 @@ struct chip_operations northbridge_intel_e7505_ops = {
CHIP_NAME("Intel E7505 Northbridge")
.enable_dev = enable_dev,
};
-
diff --git a/src/northbridge/intel/e7520/chip.h b/src/northbridge/intel/e7520/chip.h
index 99833bd..2b9e196 100644
--- a/src/northbridge/intel/e7520/chip.h
+++ b/src/northbridge/intel/e7520/chip.h
@@ -3,4 +3,3 @@ struct northbridge_intel_e7520_config
/* Interrupt line connect */
unsigned int intrline;
};
-
diff --git a/src/northbridge/intel/e7520/northbridge.h b/src/northbridge/intel/e7520/northbridge.h
index 516834f..b89b721 100644
--- a/src/northbridge/intel/e7520/northbridge.h
+++ b/src/northbridge/intel/e7520/northbridge.h
@@ -5,4 +5,3 @@ extern unsigned int e7520_scan_root_bus(device_t root, unsigned int max);
#endif /* NORTHBRIDGE_INTEL_E7520_H */
-
diff --git a/src/northbridge/intel/e7520/pciexp_porta.c b/src/northbridge/intel/e7520/pciexp_porta.c
index ab73a71..f3639ad 100644
--- a/src/northbridge/intel/e7520/pciexp_porta.c
+++ b/src/northbridge/intel/e7520/pciexp_porta.c
@@ -58,5 +58,3 @@ static const struct pci_driver pci_driver __pci_driver = {
.vendor = PCI_VENDOR_ID_INTEL,
.device = PCI_DEVICE_ID_INTEL_PCIE_PA,
};
-
-
diff --git a/src/northbridge/intel/e7520/pciexp_porta1.c b/src/northbridge/intel/e7520/pciexp_porta1.c
index c79535f..250db0a 100644
--- a/src/northbridge/intel/e7520/pciexp_porta1.c
+++ b/src/northbridge/intel/e7520/pciexp_porta1.c
@@ -37,5 +37,3 @@ static const struct pci_driver pci_driver __pci_driver = {
.vendor = PCI_VENDOR_ID_INTEL,
.device = PCI_DEVICE_ID_INTEL_PCIE_PA1,
};
-
-
diff --git a/src/northbridge/intel/e7520/pciexp_portb.c b/src/northbridge/intel/e7520/pciexp_portb.c
index b20abde..d45bb31 100644
--- a/src/northbridge/intel/e7520/pciexp_portb.c
+++ b/src/northbridge/intel/e7520/pciexp_portb.c
@@ -38,5 +38,3 @@ static const struct pci_driver pci_driver __pci_driver = {
.vendor = PCI_VENDOR_ID_INTEL,
.device = PCI_DEVICE_ID_INTEL_PCIE_PB,
};
-
-
diff --git a/src/northbridge/intel/e7520/pciexp_portc.c b/src/northbridge/intel/e7520/pciexp_portc.c
index d2706d1..6b3d4d3 100644
--- a/src/northbridge/intel/e7520/pciexp_portc.c
+++ b/src/northbridge/intel/e7520/pciexp_portc.c
@@ -37,5 +37,3 @@ static const struct pci_driver pci_driver __pci_driver = {
.vendor = PCI_VENDOR_ID_INTEL,
.device = PCI_DEVICE_ID_INTEL_PCIE_PC,
};
-
-
diff --git a/src/northbridge/intel/e7525/chip.h b/src/northbridge/intel/e7525/chip.h
index c7783d4..c98555c 100644
--- a/src/northbridge/intel/e7525/chip.h
+++ b/src/northbridge/intel/e7525/chip.h
@@ -3,4 +3,3 @@ struct northbridge_intel_e7525_config
/* Interrupt line connect */
unsigned int intrline;
};
-
diff --git a/src/northbridge/intel/e7525/northbridge.h b/src/northbridge/intel/e7525/northbridge.h
index 0ee533f..9299091 100644
--- a/src/northbridge/intel/e7525/northbridge.h
+++ b/src/northbridge/intel/e7525/northbridge.h
@@ -5,4 +5,3 @@ extern unsigned int e7525_scan_root_bus(device_t root, unsigned int max);
#endif /* NORTHBRIDGE_INTEL_E7525_H */
-
diff --git a/src/northbridge/intel/e7525/pciexp_porta.c b/src/northbridge/intel/e7525/pciexp_porta.c
index 4bae287..daf218e 100644
--- a/src/northbridge/intel/e7525/pciexp_porta.c
+++ b/src/northbridge/intel/e7525/pciexp_porta.c
@@ -37,5 +37,3 @@ static const struct pci_driver pci_driver __pci_driver = {
.vendor = PCI_VENDOR_ID_INTEL,
.device = PCI_DEVICE_ID_INTEL_PCIE_PA,
};
-
-
diff --git a/src/northbridge/intel/e7525/pciexp_porta1.c b/src/northbridge/intel/e7525/pciexp_porta1.c
index b54ee8a..8f54714 100644
--- a/src/northbridge/intel/e7525/pciexp_porta1.c
+++ b/src/northbridge/intel/e7525/pciexp_porta1.c
@@ -37,5 +37,3 @@ static const struct pci_driver pci_driver __pci_driver = {
.vendor = PCI_VENDOR_ID_INTEL,
.device = PCI_DEVICE_ID_INTEL_PCIE_PA1,
};
-
-
diff --git a/src/northbridge/intel/e7525/pciexp_portb.c b/src/northbridge/intel/e7525/pciexp_portb.c
index 7b78b42..3487fa9 100644
--- a/src/northbridge/intel/e7525/pciexp_portb.c
+++ b/src/northbridge/intel/e7525/pciexp_portb.c
@@ -37,5 +37,3 @@ static const struct pci_driver pci_driver __pci_driver = {
.vendor = PCI_VENDOR_ID_INTEL,
.device = PCI_DEVICE_ID_INTEL_PCIE_PB,
};
-
-
diff --git a/src/northbridge/intel/e7525/pciexp_portc.c b/src/northbridge/intel/e7525/pciexp_portc.c
index da6eaf7..e181bf1 100644
--- a/src/northbridge/intel/e7525/pciexp_portc.c
+++ b/src/northbridge/intel/e7525/pciexp_portc.c
@@ -37,5 +37,3 @@ static const struct pci_driver pci_driver __pci_driver = {
.vendor = PCI_VENDOR_ID_INTEL,
.device = PCI_DEVICE_ID_INTEL_PCIE_PC,
};
-
-
diff --git a/src/northbridge/intel/fsp_sandybridge/acpi.c b/src/northbridge/intel/fsp_sandybridge/acpi.c
index 3c15615..3e47ed4 100644
--- a/src/northbridge/intel/fsp_sandybridge/acpi.c
+++ b/src/northbridge/intel/fsp_sandybridge/acpi.c
@@ -198,5 +198,3 @@ int init_igd_opregion(igd_opregion_t *opregion)
return 0;
}
-
-
diff --git a/src/northbridge/intel/fsp_sandybridge/chip.h b/src/northbridge/intel/fsp_sandybridge/chip.h
index 7e6c1d8..9b5f605 100644
--- a/src/northbridge/intel/fsp_sandybridge/chip.h
+++ b/src/northbridge/intel/fsp_sandybridge/chip.h
@@ -39,4 +39,3 @@ struct northbridge_intel_fsp_sandybridge_config {
u32 gpu_cpu_backlight; /* CPU Backlight PWM value */
u32 gpu_pch_backlight; /* PCH Backlight PWM value */
};
-
diff --git a/src/northbridge/intel/fsp_sandybridge/gma.h b/src/northbridge/intel/fsp_sandybridge/gma.h
index bd4c266..cdf5d91 100644
--- a/src/northbridge/intel/fsp_sandybridge/gma.h
+++ b/src/northbridge/intel/fsp_sandybridge/gma.h
@@ -165,4 +165,3 @@ typedef struct {
} __attribute__((packed)) optionrom_vbt_t;
#define VBT_SIGNATURE 0x54425624
-
diff --git a/src/northbridge/intel/gm45/early_init.c b/src/northbridge/intel/gm45/early_init.c
index ed5bf99..335ef68 100644
--- a/src/northbridge/intel/gm45/early_init.c
+++ b/src/northbridge/intel/gm45/early_init.c
@@ -45,4 +45,3 @@ void gm45_early_init(void)
pci_write_config8(d0f0, D0F0_PAM(5), 0x33);
pci_write_config8(d0f0, D0F0_PAM(6), 0x33);
}
-
diff --git a/src/northbridge/intel/gm45/raminit_rcomp_calibration.c b/src/northbridge/intel/gm45/raminit_rcomp_calibration.c
index 4327045..adf92a1 100644
--- a/src/northbridge/intel/gm45/raminit_rcomp_calibration.c
+++ b/src/northbridge/intel/gm45/raminit_rcomp_calibration.c
@@ -249,4 +249,3 @@ void raminit_rcomp_calibration(const stepping_t stepping) {
mchbar += 0x0040;
}
}
-
diff --git a/src/northbridge/intel/gm45/thermal.c b/src/northbridge/intel/gm45/thermal.c
index c2ab2a5..d4694b5 100644
--- a/src/northbridge/intel/gm45/thermal.c
+++ b/src/northbridge/intel/gm45/thermal.c
@@ -197,4 +197,3 @@ void raminit_thermal(const sysinfo_t *sysinfo)
tmp = MCHBAR32(0x11d4) & ~0x1f;
MCHBAR32(0x11d4) = tmp | 4;
}
-
diff --git a/src/northbridge/intel/haswell/acpi.c b/src/northbridge/intel/haswell/acpi.c
index 81da086..964a9d3 100644
--- a/src/northbridge/intel/haswell/acpi.c
+++ b/src/northbridge/intel/haswell/acpi.c
@@ -191,5 +191,3 @@ int init_igd_opregion(igd_opregion_t *opregion)
return 0;
}
-
-
diff --git a/src/northbridge/intel/haswell/gma.h b/src/northbridge/intel/haswell/gma.h
index bfa43ef..29281ba 100644
--- a/src/northbridge/intel/haswell/gma.h
+++ b/src/northbridge/intel/haswell/gma.h
@@ -165,4 +165,3 @@ typedef struct {
} __attribute__((packed)) optionrom_vbt_t;
#define VBT_SIGNATURE 0x54425624
-
diff --git a/src/northbridge/intel/haswell/minihd.c b/src/northbridge/intel/haswell/minihd.c
index cef6126..4a38b28 100644
--- a/src/northbridge/intel/haswell/minihd.c
+++ b/src/northbridge/intel/haswell/minihd.c
@@ -137,4 +137,3 @@ static const struct pci_driver haswell_minihd __pci_driver = {
.vendor = PCI_VENDOR_ID_INTEL,
.devices = pci_device_ids,
};
-
diff --git a/src/northbridge/intel/haswell/mrccache.c b/src/northbridge/intel/haswell/mrccache.c
index f411db6..a921e04 100644
--- a/src/northbridge/intel/haswell/mrccache.c
+++ b/src/northbridge/intel/haswell/mrccache.c
@@ -248,4 +248,3 @@ struct mrc_data_container *find_current_mrc_cache(void)
// 0. compare MRC data to last mrc-cache block (exit if same)
return find_current_mrc_cache_local(cache_base, cache_size);
}
-
diff --git a/src/northbridge/intel/i3100/chip.h b/src/northbridge/intel/i3100/chip.h
index 3674801..ca76b02 100644
--- a/src/northbridge/intel/i3100/chip.h
+++ b/src/northbridge/intel/i3100/chip.h
@@ -22,4 +22,3 @@ struct northbridge_intel_i3100_config
/* Interrupt line connect */
u16 intrline;
};
-
diff --git a/src/northbridge/intel/i440bx/i440bx.h b/src/northbridge/intel/i440bx/i440bx.h
index 2d0ebcc..149517a 100644
--- a/src/northbridge/intel/i440bx/i440bx.h
+++ b/src/northbridge/intel/i440bx/i440bx.h
@@ -86,4 +86,3 @@
#define DWTC 0xe0 /* DRAM Write Thermal Throttling Control (0x000..000). */
#define DRTC 0xe8 /* DRAM Read Thermal Throttling Control (0x000..000). */
#define BUFFC 0xf0 /* Buffer Control Register (0x0000). */
-
diff --git a/src/northbridge/intel/i440lx/i440lx.h b/src/northbridge/intel/i440lx/i440lx.h
index 5e49b81..47d5b52 100644
--- a/src/northbridge/intel/i440lx/i440lx.h
+++ b/src/northbridge/intel/i440lx/i440lx.h
@@ -70,4 +70,3 @@
#define PAM4 0x5d
#define PAM5 0x5e
#define PAM6 0x5f
-
diff --git a/src/northbridge/intel/i440lx/raminit.c b/src/northbridge/intel/i440lx/raminit.c
index d96e4eb..26c0c4b 100644
--- a/src/northbridge/intel/i440lx/raminit.c
+++ b/src/northbridge/intel/i440lx/raminit.c
@@ -451,4 +451,3 @@ static void sdram_enable(void)
PRINT_DEBUG("Northbridge following SDRAM init:\n");
}
-
diff --git a/src/northbridge/intel/i82830/i82830.h b/src/northbridge/intel/i82830/i82830.h
index 40c32c9..bdf7e51 100644
--- a/src/northbridge/intel/i82830/i82830.h
+++ b/src/northbridge/intel/i82830/i82830.h
@@ -49,4 +49,3 @@
#define APBASE 0x10 /* Aperture Base Configuration (0x00000008) */
#define APSIZE 0xb4 /* Apterture Size (0x00) */
#define ATTBASE 0xb8 /* Aperture Translation Table Base (0x00000000) */
-
diff --git a/src/northbridge/intel/i855/raminit.c b/src/northbridge/intel/i855/raminit.c
index 919c653..0ab4d38 100644
--- a/src/northbridge/intel/i855/raminit.c
+++ b/src/northbridge/intel/i855/raminit.c
@@ -981,4 +981,3 @@ static void sdram_set_spd_registers(void)
/* Setup Initial Northbridge Registers */
northbridge_set_registers();
}
-
diff --git a/src/northbridge/intel/i945/acpi.c b/src/northbridge/intel/i945/acpi.c
index 2640cca..e05bd58 100644
--- a/src/northbridge/intel/i945/acpi.c
+++ b/src/northbridge/intel/i945/acpi.c
@@ -71,5 +71,3 @@ unsigned long acpi_fill_mcfg(unsigned long current)
return current;
}
-
-
diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c
index a55ea05..08ce10b 100644
--- a/src/northbridge/intel/i945/early_init.c
+++ b/src/northbridge/intel/i945/early_init.c
@@ -903,4 +903,3 @@ void i945_late_initialization(void)
i945_setup_root_complex_topology();
}
-
diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c
index 2197186..c04483e 100644
--- a/src/northbridge/intel/i945/gma.c
+++ b/src/northbridge/intel/i945/gma.c
@@ -152,4 +152,3 @@ static const struct pci_driver i945_gma_func1_driver __pci_driver = {
.vendor = PCI_VENDOR_ID_INTEL,
.device = 0x27a6,
};
-
diff --git a/src/northbridge/intel/i945/rcven.c b/src/northbridge/intel/i945/rcven.c
index 15829c5..88d6a00 100644
--- a/src/northbridge/intel/i945/rcven.c
+++ b/src/northbridge/intel/i945/rcven.c
@@ -335,4 +335,3 @@ void receive_enable_adjust(struct sys_info *sysinfo)
if (receive_enable_autoconfig(0x80, sysinfo))
return;
}
-
diff --git a/src/northbridge/intel/nehalem/chip.h b/src/northbridge/intel/nehalem/chip.h
index 95f8b5f..e33d108 100644
--- a/src/northbridge/intel/nehalem/chip.h
+++ b/src/northbridge/intel/nehalem/chip.h
@@ -44,4 +44,3 @@ struct northbridge_intel_nehalem_config {
int gpu_link_frequency_270_mhz;
int gpu_lvds_num_lanes;
};
-
diff --git a/src/northbridge/intel/sandybridge/acpi.c b/src/northbridge/intel/sandybridge/acpi.c
index 0a179ca..398cb30 100644
--- a/src/northbridge/intel/sandybridge/acpi.c
+++ b/src/northbridge/intel/sandybridge/acpi.c
@@ -198,5 +198,3 @@ int init_igd_opregion(igd_opregion_t *opregion)
return 0;
}
-
-
diff --git a/src/northbridge/intel/sandybridge/chip.h b/src/northbridge/intel/sandybridge/chip.h
index 16df91b..17bc7e7 100644
--- a/src/northbridge/intel/sandybridge/chip.h
+++ b/src/northbridge/intel/sandybridge/chip.h
@@ -39,4 +39,3 @@ struct northbridge_intel_sandybridge_config {
u32 gpu_cpu_backlight; /* CPU Backlight PWM value */
u32 gpu_pch_backlight; /* PCH Backlight PWM value */
};
-
diff --git a/src/northbridge/intel/sandybridge/gma.h b/src/northbridge/intel/sandybridge/gma.h
index 63368f1..bc5d986 100644
--- a/src/northbridge/intel/sandybridge/gma.h
+++ b/src/northbridge/intel/sandybridge/gma.h
@@ -170,4 +170,3 @@ struct northbridge_intel_sandybridge_config;
int i915lightup(const struct northbridge_intel_sandybridge_config *info,
u32 physbase, u16 pio, u32 mmio, u32 lfb);
-
diff --git a/src/northbridge/intel/sandybridge/mrccache.c b/src/northbridge/intel/sandybridge/mrccache.c
index 915f9d3..c84ff82 100644
--- a/src/northbridge/intel/sandybridge/mrccache.c
+++ b/src/northbridge/intel/sandybridge/mrccache.c
@@ -247,4 +247,3 @@ struct mrc_data_container *find_current_mrc_cache(void)
// 0. compare MRC data to last mrc-cache block (exit if same)
return find_current_mrc_cache_local(cache_base, cache_size);
}
-
diff --git a/src/northbridge/via/cx700/registers.h b/src/northbridge/via/cx700/registers.h
index 0894e51..67c3da4 100644
--- a/src/northbridge/via/cx700/registers.h
+++ b/src/northbridge/via/cx700/registers.h
@@ -42,5 +42,3 @@
#define DDRII_333 0x2
#define DDRII_266 0x1
#define DDRII_200 0x0
-
-
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