[coreboot-gerrit] Patch merged into coreboot/master: 33a6c0e x86: parallel MP initialization
gerrit at coreboot.org
gerrit at coreboot.org
Thu Jan 30 06:05:13 CET 2014
the following patch was just integrated into master:
commit 33a6c0e4c172c64ddc43e5270834c09f4e68cf4c
Author: Aaron Durbin <adurbin at chromium.org>
Date: Mon Oct 21 12:15:29 2013 -0500
x86: parallel MP initialization
Provide a common entry point for bringing up the APs
in parallel. This work is based off of the Haswell one
which can be moved over to this in the future. The APs
are brought up and have the BSP's MTRRs duplicated in
their own MTRRs. Additionally, Microcode is loaded before
enabling caching. However, the current microcode loading
support assumes Intel's mechanism.
The infrastructure provides a notion of a flight plan
for the BSP and APs. This allows for flexibility in the
order of operations for a given architecture/chip without
providing any specific policy. Therefore, the chipset
caller can provide the order that is required.
BUG=chrome-os-partner:22862
BRANCH=None
TEST=Built and booted on rambi with baytrail specific patches.
Change-Id: I0539047a1b24c13ef278695737cdba3b9344c820
Signed-off-by: Aaron Durbin <adurbin at chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/173703
See http://review.coreboot.org/4888 for details.
-gerrit
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