[coreboot-gerrit] Patch set updated for coreboot: e8a22cc Jetway NF81-T56N-LF [2/2]: actually implement mainboard support.

Edward O'Callaghan (eocallaghan@alterapraxis.com) gerrit at coreboot.org
Tue Jan 28 04:30:12 CET 2014


Edward O'Callaghan (eocallaghan at alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4801

-gerrit

commit e8a22ccdcca9d9ecb6f112e2ba5e5f388ad64732
Author: Edward O'Callaghan <eocallaghan at alterapraxis.com>
Date:   Sat Jan 25 21:46:10 2014 +1100

    Jetway NF81-T56N-LF [2/2]: actually implement mainboard support.
    
    Step 2: change the Persimmon code to adapt it to the new board's hardware.
    
    The NF81-T56N-LF is a IPC form factor embedded board:
    - AMD Fusion G-T56N (1.65 GHz dual core) APU
      - 2x SO-DIMM sockets for DDR3 800-1066 SDRAM (1.5 or 1.35V)?
      - VGA and LVDS (via Analogix ANX3110)
    - AMD A55E (Hudson-E1) southbridge
      - 6x USB 2.0/1.1 ports
      - 5x SATA3 6Gb/s, 1x mSATA socket
      - 6-Channel HD Audio (via VIA VT1705)??
      - PCI and ISA (via ITE IT8888)??
      - NEC uPD78F0532 microcontroller on I2C ("SEMA")??
    - 2x RJ45 GbE (via Realtek RTL8111E x2)
    - Fintek F71869AD Super I/O
      - PS/2 KB/MS port
      - RS232 header (via Unisonic UTC 75232 RS232 driver/receiver)
      - GPIO header
      - CIR header
    - 1x MXIC MX25L1606E (SO8, soldered) 16 Mbit SPI flash (BIOS)
    
    Note: MX25L1606E is 16Mbit, 8bits in a byte, so 2MB. Jetway *lies*
    claiming the SPI flash is 16MB. They also use red pen over the chip
    so you wont see this deceit.
    
    Change-Id: I03ccc58bc782e800aeef0d19679ce060277b0c04
    Signed-off-by: Edward O'Callaghan <eocallaghan at alterapraxis.com>
---
 src/mainboard/jetway/Kconfig                     |  3 +++
 src/mainboard/jetway/nf81-t56n-lf/Kconfig        | 18 ++++++++++--------
 src/mainboard/jetway/nf81-t56n-lf/OptionsIds.h   |  2 +-
 src/mainboard/jetway/nf81-t56n-lf/board_info.txt |  5 +++--
 src/mainboard/jetway/nf81-t56n-lf/devicetree.cb  | 19 +++++++++++++------
 src/mainboard/jetway/nf81-t56n-lf/platform_cfg.h |  3 +++
 src/mainboard/jetway/nf81-t56n-lf/romstage.c     |  7 ++++---
 7 files changed, 37 insertions(+), 20 deletions(-)

diff --git a/src/mainboard/jetway/Kconfig b/src/mainboard/jetway/Kconfig
index 7e6e29d..5b55daa 100644
--- a/src/mainboard/jetway/Kconfig
+++ b/src/mainboard/jetway/Kconfig
@@ -11,6 +11,8 @@ config BOARD_JETWAY_J7F4K1G5D
 	bool "J7F4K1G5D"
 config BOARD_JETWAY_PA78VM5
 	bool "PA78VM5 (Fam10)"
+config BOARD_JETWAY_NF81_T56N_LF
+	bool "NF81_T56N_LF"
 
 endchoice
 
@@ -18,6 +20,7 @@ source "src/mainboard/jetway/j7f2/Kconfig"
 source "src/mainboard/jetway/j7f4k1g2e/Kconfig"
 source "src/mainboard/jetway/j7f4k1g5d/Kconfig"
 source "src/mainboard/jetway/pa78vm5/Kconfig"
+source "src/mainboard/jetway/nf81-t56n-lf/Kconfig"
 
 config MAINBOARD_VENDOR
 	string
diff --git a/src/mainboard/jetway/nf81-t56n-lf/Kconfig b/src/mainboard/jetway/nf81-t56n-lf/Kconfig
index febd8dd..d602ffa 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/Kconfig
+++ b/src/mainboard/jetway/nf81-t56n-lf/Kconfig
@@ -2,6 +2,7 @@
 # This file is part of the coreboot project.
 #
 # Copyright (C) 2011 Advanced Micro Devices, Inc.
+# Copyright (C) 2014 Edward O'Callaghan <eocallaghan at alterapraxis.com>.
 #
 # This program is free software; you can redistribute it and/or modify
 # it under the terms of the GNU General Public License as published by
@@ -17,7 +18,7 @@
 # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
 #
 
-if BOARD_AMD_PERSIMMON
+if BOARD_JETWAY_NF81_T56N_LF
 
 config BOARD_SPECIFIC_OPTIONS # dummy
 	def_bool y
@@ -25,22 +26,23 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select CPU_AMD_AGESA_FAMILY14
 	select NORTHBRIDGE_AMD_AGESA_FAMILY14
 	select SOUTHBRIDGE_AMD_CIMX_SB800
-	select SUPERIO_FINTEK_F81865F
+	select SUPERIO_FINTEK_F71869AD
 	select HAVE_OPTION_TABLE
 	select HAVE_PIRQ_TABLE
 	select HAVE_MP_TABLE
-	select HAVE_ACPI_RESUME
+#	FIXME: Disable S3 for now. Enable by default once stabilised.
+#	select HAVE_ACPI_RESUME
 	select SB_HT_CHAIN_UNITID_OFFSET_ONLY
 	select LIFT_BSP_APIC_ID
 	select SERIAL_CPU_INIT
 	select AMDMCT
 	select HAVE_ACPI_TABLES
-	select BOARD_ROMSIZE_KB_4096
+	select BOARD_ROMSIZE_KB_2048
 	select GFXUMA
 
 config MAINBOARD_DIR
 	string
-	default amd/persimmon
+	default jetway/nf81-t56n-lf
 
 config APIC_ID_OFFSET
 	hex
@@ -48,7 +50,7 @@ config APIC_ID_OFFSET
 
 config MAINBOARD_PART_NUMBER
 	string
-	default "Persimmon"
+	default "NF81-T56N-LF"
 
 config HW_MEM_HOLE_SIZEK
 	hex
@@ -101,7 +103,7 @@ config VGA_BIOS
 
 config VGA_BIOS_ID
 	string
-	default "1002,9802"
+	default "1002,9806" # FUSION_G_T56N
 
 config SB800_AHCI_ROM
 	bool
@@ -111,4 +113,4 @@ config DRIVERS_PS2_KEYBOARD
 	bool
 	default n
 
-endif # BOARD_AMD_PERSIMMON
+endif # BOARD_JETWAY_NF81_T56N_LF
diff --git a/src/mainboard/jetway/nf81-t56n-lf/OptionsIds.h b/src/mainboard/jetway/nf81-t56n-lf/OptionsIds.h
index cf0a4be..fd05c16 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/OptionsIds.h
+++ b/src/mainboard/jetway/nf81-t56n-lf/OptionsIds.h
@@ -51,7 +51,7 @@
  **/
 
 #define IDSOPT_IDS_ENABLED     TRUE
-//#define IDSOPT_TRACING_ENABLED TRUE
+#define IDSOPT_TRACING_ENABLED TRUE
 #define IDSOPT_ASSERT_ENABLED  TRUE
 
 //#define IDSOPT_DEBUG_ENABLED  FALSE
diff --git a/src/mainboard/jetway/nf81-t56n-lf/board_info.txt b/src/mainboard/jetway/nf81-t56n-lf/board_info.txt
index 85cb19a..6748751 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/board_info.txt
+++ b/src/mainboard/jetway/nf81-t56n-lf/board_info.txt
@@ -1,5 +1,6 @@
-Board name: DBFT1-00-EVAL-KT (Persimmon)
-Category: eval
+Board URL: http://www.jetway.com.tw/jw/ipcboard_view.asp?productid=822&proname=NF81-T56N-LF
+Category: Mini-ITX
+ROM package: SOIC8
 ROM protocol: SPI
 ROM socketed: n
 Flashrom support: y
diff --git a/src/mainboard/jetway/nf81-t56n-lf/devicetree.cb b/src/mainboard/jetway/nf81-t56n-lf/devicetree.cb
index 8b1acd5..98d9ee6 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/devicetree.cb
+++ b/src/mainboard/jetway/nf81-t56n-lf/devicetree.cb
@@ -2,6 +2,7 @@
 # This file is part of the coreboot project.
 #
 # Copyright (C) 2011 Advanced Micro Devices, Inc.
+# Copyright (C) 2014 Edward O'Callaghan <eocallaghan at alterapraxis.com>.
 #
 # This program is free software; you can redistribute it and/or modify
 # it under the terms of the GNU General Public License as published by
@@ -29,6 +30,7 @@ chip northbridge/amd/agesa/family14/root_complex
 					chip northbridge/amd/agesa/family14 # PCI side of HT root complex
 						device pci 0.0 on end # Root Complex
 						device pci 1.0 on end # Internal Graphics P2P bridge 0x980[2456]
+						device pci 1.1 on end # Internal Audio P2P bridge 0x1314
 						device pci 4.0 on end # PCIE P2P bridge on-board NIC
 						device pci 5.0 off end # PCIE P2P bridge
 						device pci 6.0 on end # PCIE P2P bridge PCIe slot
@@ -53,7 +55,7 @@ chip northbridge/amd/agesa/family14/root_complex
 					device pci 14.1 on end # IDE	0x439c
 					device pci 14.2 on end # HDA	0x4383
 					device pci 14.3 on # LPC		0x439d
-					chip superio/fintek/f81865f
+					chip superio/fintek/f71869ad
 						device pnp 4e.0 off		# Floppy
 							io 0x60 = 0x3f0
 							irq 0x70 = 6
@@ -76,17 +78,17 @@ chip northbridge/amd/agesa/family14/root_complex
 							io 0x60 = 0x2f8
 							irq 0x70 = 3
 						end
-					end # f81865f
+					end # f71869ad
 				end #LPC
 				device pci 14.4 on  end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0}
-				device pci 14.5 off end # OHCI FS/LS USB
+				device pci 14.5 on end # OHCI FS/LS USB (0x4399)
 				device pci 14.6 off end # Hudson-E1 GbE MAC: Broadcom BCM5785 (14E4:1699)
-				device pci 15.0 off end # PCIe PortA
+				device pci 15.0 on end # PCIe PortA (0x43a0) GbE MAC: Realtek Semiconductor Co., Ltd. RTL8111/8168/8411 (10ec:8168)
 				device pci 15.1 off end # PCIe PortB
 				device pci 15.2 off end # PCIe PortC
 				device pci 15.3 off end # PCIe PortD
-				device pci 16.0 off end # OHCI USB 10-13
-				device pci 16.2 off end # EHCI USB 10-13
+				device pci 16.0 on end # OHCI USB 10-13 (0x4397)
+				device pci 16.2 on end # EHCI USB 10-13 (0x4396)
 				register "gpp_configuration" = "0" #4:0:0:0 (really need to disable all 4 somehow)
 				register "boot_switch_sata_ide" = "0"	# 0: boot from SATA. 1: IDE
 
@@ -150,6 +152,11 @@ chip northbridge/amd/agesa/family14/root_complex
 			device pci 18.6 on end
 			device pci 18.7 on end
 
+#
+# FIXME: Verify the proper SocketId/MemChannelId/DimmId addresses of the SPD
+# with i2cdump tool.
+# Notes:  0xa0=0x50*2, 0xa2=0x51*2.. 0x50-0x54 are usually RAM modules on the SMBus.
+#
 			register "spdAddrLookup" = "
 			{
 				{ {0xA0, 0xA2}, {0x00, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses
diff --git a/src/mainboard/jetway/nf81-t56n-lf/platform_cfg.h b/src/mainboard/jetway/nf81-t56n-lf/platform_cfg.h
index 0578e27..e638892 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/platform_cfg.h
+++ b/src/mainboard/jetway/nf81-t56n-lf/platform_cfg.h
@@ -2,6 +2,7 @@
  * This file is part of the coreboot project.
  *
  * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ * Copyright (C) 2014 Edward O'Callaghan <eocallaghan at alterapraxis.com>.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -227,6 +228,7 @@
  */
 #define GEC_CONFIG			0
 
+/* FIXME: Verify this for sound to work! */
 static const CODECENTRY persimmon_codec_alc269[] =
 {
 	/* NID, PinConfig */
@@ -244,6 +246,7 @@ static const CODECENTRY persimmon_codec_alc269[] =
 	{0xff, 0xffffffff} /* end of table */
 };
 
+/* FIXME: Verify this for sound to work! */
 static const CODECTBLLIST codec_tablelist[] =
 {
 	{0x010ec0269, (CODECENTRY*)&persimmon_codec_alc269[0]},
diff --git a/src/mainboard/jetway/nf81-t56n-lf/romstage.c b/src/mainboard/jetway/nf81-t56n-lf/romstage.c
index 98c64ed..f8271f7 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/romstage.c
+++ b/src/mainboard/jetway/nf81-t56n-lf/romstage.c
@@ -2,6 +2,7 @@
  * This file is part of the coreboot project.
  *
  * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ * Copyright (C) 2014 Edward O'Callaghan <eocallaghan at alterapraxis.com>.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -31,7 +32,7 @@
 #include <cpu/x86/mtrr.h>
 #include "agesawrapper.h"
 #include "cpu/x86/bist.h"
-#include "superio/fintek/f81865f/f81865f_early_serial.c"
+#include "superio/fintek/f71869ad/f71869ad.h"
 #include "cpu/x86/lapic.h"
 #include "drivers/pc80/i8254.c"
 #include "drivers/pc80/i8259.c"
@@ -45,7 +46,7 @@
 void disable_cache_as_ram(void); /* cache_as_ram.inc */
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx);
 
-#define SERIAL_DEV PNP_DEV(0x4e, F81865F_SP1)
+#define SERIAL_DEV PNP_DEV(0x4e, F71869AD_SP1)
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
@@ -70,7 +71,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 		sb_Poweron_Init();
 
 		post_code(0x31);
-		f81865f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+		f71869ad_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 		console_init();
 	}
 



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