[coreboot-gerrit] New patch to review for coreboot: f6ebfd7 baytrail: Add a shared GNVS init function

[Aaron Durbin (adurbin@google.com)]

Aaron Durbin (adurbin at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5058

-gerrit

commit f6ebfd77bc732ccef4a03b6c493d433a1fc244ad
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Tue Jan 21 15:16:51 2014 -0800

    baytrail: Add a shared GNVS init function
    
    There are several things in GNVS being initialized in the
    mainboard ACPI table creation step that are shared across all
    boards using the chipset.
    
    Move the init that is not board specific into a shared function
    and call it from the table creation step.
    
    BUG=chrome-os-partner:8127
    BRANCH=baytrail
    TEST=build and boot on rambi device
    
    Change-Id: I178193d7fe298ec26247402370a1af9280bb09c1
    Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/183332
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 src/mainboard/google/rambi/acpi_tables.c | 19 +------------------
 src/soc/intel/baytrail/acpi.c            | 27 +++++++++++++++++++++++++++
 src/soc/intel/baytrail/baytrail/acpi.h   |  2 ++
 src/soc/intel/baytrail/baytrail/nvs.h    |  5 +++++
 4 files changed, 35 insertions(+), 18 deletions(-)

diff --git a/src/mainboard/google/rambi/acpi_tables.c b/src/mainboard/google/rambi/acpi_tables.c
index 1d96dec..baa8ad1 100644
--- a/src/mainboard/google/rambi/acpi_tables.c
+++ b/src/mainboard/google/rambi/acpi_tables.c
@@ -30,8 +30,6 @@
 #include <device/pci_ids.h>
 #include <cpu/cpu.h>
 #include <cpu/x86/msr.h>
-#include <ec/google/chromeec/ec.h>
-#include <vendorcode/google/chromeos/gnvs.h>
 #include <baytrail/acpi.h>
 #include <baytrail/nvs.h>
 #include <baytrail/iomap.h>
@@ -42,7 +40,7 @@ extern const unsigned char AmlCode[];
 
 static void acpi_create_gnvs(global_nvs_t *gnvs)
 {
-	gnvs->pcnt = dev_count_cpu();
+	acpi_init_gnvs(gnvs);
 
 	/* Enable USB ports in S3 */
 	gnvs->s3u0 = 1;
@@ -52,12 +50,6 @@ static void acpi_create_gnvs(global_nvs_t *gnvs)
 	gnvs->s5u0 = 0;
 	gnvs->s5u1 = 0;
 
-	/* CBMEM TOC */
-	gnvs->cmem = 0;
-
-	/* Top of Low Memory (start of resource allocation) */
-	gnvs->tolm = nc_read_top_of_low_memory();
-
 	/* TPM Present */
 	gnvs->tpmp = 1;
 
@@ -66,15 +58,6 @@ static void acpi_create_gnvs(global_nvs_t *gnvs)
 	gnvs->tpsv = PASSIVE_TEMPERATURE;
 	gnvs->tact = ACTIVE_TEMPERATURE;
 	gnvs->dpte = 1;
-
-#if CONFIG_CHROMEOS
-	chromeos_init_vboot(&(gnvs->chromeos));
-	gnvs->chromeos.vbt2 = google_ec_running_ro() ?
-		ACTIVE_ECFW_RO : ACTIVE_ECFW_RW;
-#endif
-
-	/* Update the mem console pointer. */
-	gnvs->cbmc = (u32)cbmem_find(CBMEM_ID_CONSOLE);
 }
 
 unsigned long acpi_fill_madt(unsigned long current)
diff --git a/src/soc/intel/baytrail/acpi.c b/src/soc/intel/baytrail/acpi.c
index 89ab929..57233a9 100644
--- a/src/soc/intel/baytrail/acpi.c
+++ b/src/soc/intel/baytrail/acpi.c
@@ -22,6 +22,7 @@
 #include <arch/acpigen.h>
 #include <arch/io.h>
 #include <arch/smp/mpspec.h>
+#include <cbmem.h>
 #include <console/console.h>
 #include <cpu/x86/smm.h>
 #include <console/console.h>
@@ -39,6 +40,9 @@
 #include <baytrail/pattrs.h>
 #include <baytrail/pmc.h>
 
+#include <ec/google/chromeec/ec.h>
+#include <vendorcode/google/chromeos/gnvs.h>
+
 #define MWAIT_RES(state, sub_state)                         \
 	{                                                   \
 		.addrl = (((state) << 4) | (sub_state)),    \
@@ -74,6 +78,29 @@ static acpi_cstate_t cstate_map[] = {
 	}
 };
 
+void acpi_init_gnvs(global_nvs_t *gnvs)
+{
+	/* CPU core count */
+	gnvs->pcnt = dev_count_cpu();
+
+	/* Top of Low Memory (start of resource allocation) */
+	gnvs->tolm = nc_read_top_of_low_memory();
+
+#if CONFIG_CONSOLE_CBMEM
+	/* Update the mem console pointer. */
+	gnvs->cbmc = (u32)cbmem_find(CBMEM_ID_CONSOLE);
+#endif
+
+#if CONFIG_CHROMEOS
+	/* Initialize Verified Boot data */
+	chromeos_init_vboot(&(gnvs->chromeos));
+#if CONFIG_EC_GOOGLE_CHROMEEC
+	gnvs->chromeos.vbt2 = google_ec_running_ro() ?
+		ACTIVE_ECFW_RO : ACTIVE_ECFW_RW;
+#endif
+#endif
+}
+
 static int acpi_sci_irq(void)
 {
 	const unsigned long actl = ILB_BASE_ADDRESS + ACTL;
diff --git a/src/soc/intel/baytrail/baytrail/acpi.h b/src/soc/intel/baytrail/baytrail/acpi.h
index da5f406..a7ee82c 100644
--- a/src/soc/intel/baytrail/baytrail/acpi.h
+++ b/src/soc/intel/baytrail/baytrail/acpi.h
@@ -21,10 +21,12 @@
 #define _BAYTRAIL_ACPI_H_
 
 #include <arch/acpi.h>
+#include <baytrail/nvs.h>
 
 void acpi_create_intel_hpet(acpi_hpet_t * hpet);
 void acpi_fill_in_fadt(acpi_fadt_t *fadt);
 unsigned long acpi_madt_irq_overrides(unsigned long current);
+void acpi_init_gnvs(global_nvs_t *gnvs);
 
 #endif /* _BAYTRAIL_ACPI_H_ */
 
diff --git a/src/soc/intel/baytrail/baytrail/nvs.h b/src/soc/intel/baytrail/baytrail/nvs.h
index e8849b9..5bc1b0e 100644
--- a/src/soc/intel/baytrail/baytrail/nvs.h
+++ b/src/soc/intel/baytrail/baytrail/nvs.h
@@ -18,6 +18,9 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  */
 
+#ifndef _BAYTRAIL_NVS_H_
+#define _BAYTRAIL_NVS_H_
+
 #include <vendorcode/google/chromeos/gnvs.h>
 #include <baytrail/device_nvs.h>
 
@@ -70,3 +73,5 @@ typedef struct {
 /* Used in SMM to find the ACPI GNVS address */
 global_nvs_t *smm_get_gnvs(void);
 #endif
+
+#endif /* _BAYTRAIL_NVS_H_ */