[coreboot-gerrit] New patch to review for coreboot: 06d1ad6 baytrail: add config option for disabling slp_x stretching
Aaron Durbin (adurbin@google.com)
gerrit at coreboot.org
Tue Jan 28 03:58:09 CET 2014
Aaron Durbin (adurbin at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5065
-gerrit
commit 06d1ad6bf755a5b0aa0d2cdc336ed69513a9ff0f
Author: Aaron Durbin <adurbin at chromium.org>
Date: Fri Jan 24 10:42:00 2014 -0600
baytrail: add config option for disabling slp_x stretching
Provide an option for the mainboard to set in its devicetree
to disable slp_x stretching on SUS power well failure. This
will allow for fast G3->S0 transition instead of waiting for
1-4 seconds.
BUG=chrome-os-partner:25269
BRANCH=baytrail
TEST=Manual. Enabled option. Put board in G3. Pressed power button
and noted startup time on the EC console.
Change-Id: I213525b3ad44fe4c95bfd014b614bbc80623cbb8
Signed-off-by: Aaron Durbin <adurbin at chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/183587
Reviewed-by: Duncan Laurie <dlaurie at chromium.org>
---
src/soc/intel/baytrail/chip.h | 3 +++
src/soc/intel/baytrail/southcluster.c | 12 ++++++++++++
2 files changed, 15 insertions(+)
diff --git a/src/soc/intel/baytrail/chip.h b/src/soc/intel/baytrail/chip.h
index 774f076..0a57885 100644
--- a/src/soc/intel/baytrail/chip.h
+++ b/src/soc/intel/baytrail/chip.h
@@ -35,6 +35,9 @@ struct soc_intel_baytrail_config {
int vnn_ps2_enable;
int vcc_ps2_enable;
+ /* Disable SLP_X stretching after SUS power well loss. */
+ int disable_slp_x_stretch_sus_fail;
+
/* USB Port Disable mask */
uint16_t usb2_port_disable_mask;
uint16_t usb3_port_disable_mask;
diff --git a/src/soc/intel/baytrail/southcluster.c b/src/soc/intel/baytrail/southcluster.c
index 1ee5edc..527ae64 100644
--- a/src/soc/intel/baytrail/southcluster.c
+++ b/src/soc/intel/baytrail/southcluster.c
@@ -35,6 +35,7 @@
#include <baytrail/pci_devs.h>
#include <baytrail/pmc.h>
#include <baytrail/ramstage.h>
+#include "chip.h"
static inline void
add_mmio_resource(device_t dev, int i, unsigned long addr, unsigned long size)
@@ -145,8 +146,10 @@ static void sc_init(device_t dev)
int i;
const unsigned long pr_base = ILB_BASE_ADDRESS + 0x08;
const unsigned long ir_base = ILB_BASE_ADDRESS + 0x20;
+ const unsigned long gen_pmcon1 = PMC_BASE_ADDRESS + GEN_PMCON1;
const unsigned long actl = ILB_BASE_ADDRESS + ACTL;
const struct baytrail_irq_route *ir = &global_baytrail_irq_route;
+ struct soc_intel_baytrail_config *config = dev->chip_info;
/* Set up the PIRQ PIC routing based on static config. */
for (i = 0; i < NUM_PIRQS; i++) {
@@ -161,6 +164,15 @@ static void sc_init(device_t dev)
write32(actl, (read32(actl) & ~SCIS_MASK) | SCIS_IRQ9);
sc_rtc_init();
+
+ if (config->disable_slp_x_stretch_sus_fail) {
+ printk(BIOS_DEBUG, "Disabling slp_x stretching.\n");
+ write32(gen_pmcon1,
+ read32(gen_pmcon1) | DIS_SLP_X_STRCH_SUS_UP);
+ } else {
+ write32(gen_pmcon1,
+ read32(gen_pmcon1) & ~DIS_SLP_X_STRCH_SUS_UP);
+ }
}
/*
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