[coreboot-gerrit] New patch to review for coreboot: d7e44ce rambi: use SERIRQ pad as keyboard irq in gpio mode

Aaron Durbin (adurbin@google.com) gerrit at coreboot.org
Tue Jan 28 03:56:50 CET 2014


Aaron Durbin (adurbin at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4979

-gerrit

commit d7e44ceaa7abc30842d6d451bb95d506acacd2a8
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Wed Nov 20 15:21:40 2013 -0600

    rambi: use SERIRQ pad as keyboard irq in gpio mode
    
    The level shifting between 3.3V and 1.8V for the SERIRQ
    signal is not working. Instead use the SERIRQ pad as
    a gpio which is used as a direct IRQ signal for the
    keyboard interupt.
    
    BUG=chrome-os-partner:23965
    BRANCH=None
    TEST=Built and booted rambi. Keyboard works with associated EC change.
    CQ-DEPEND=CL:177189
    
    Change-Id: Ifc270ca38207828a6d4711551d4bde9121559cca
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/177223
    Tested-by: Bernie Thompson <bhthompson at chromium.org>
---
 src/mainboard/google/rambi/acpi/superio.asl | 3 +++
 src/mainboard/google/rambi/gpio.c           | 3 ++-
 src/mainboard/google/rambi/irqroute.h       | 2 ++
 src/mainboard/google/rambi/onboard.h        | 2 ++
 4 files changed, 9 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/google/rambi/acpi/superio.asl b/src/mainboard/google/rambi/acpi/superio.asl
index f40611c..3199ed5 100644
--- a/src/mainboard/google/rambi/acpi/superio.asl
+++ b/src/mainboard/google/rambi/acpi/superio.asl
@@ -19,10 +19,13 @@
 
 /* mainboard configuration */
 #include <mainboard/google/rambi/ec.h>
+#include <mainboard/google/rambi/onboard.h>
 
 #define SIO_EC_MEMMAP_ENABLE     // EC Memory Map Resources
 #define SIO_EC_HOST_ENABLE       // EC Host Interface Resources
 #define SIO_EC_ENABLE_PS2K       // Enable PS/2 Keyboard
+// Override default IRQ settings
+#define SIO_EC_PS2K_IRQ Interrupt(ResourceConsumer, Edge, ActiveLow) {BOARD_I8042_IRQ}
 
 /* ACPI code for EC SuperIO functions */
 #include <ec/google/chromeec/acpi/superio.asl>
diff --git a/src/mainboard/google/rambi/gpio.c b/src/mainboard/google/rambi/gpio.c
index dfe880a..76002cf 100644
--- a/src/mainboard/google/rambi/gpio.c
+++ b/src/mainboard/google/rambi/gpio.c
@@ -106,7 +106,7 @@ static const struct soc_gpio_map gpscore_gpio_map[] = {
 	GPIO_FUNC1,	/* S0-SC047 - PCLK_TPM */
 	GPIO_FUNC1,	/* S0-SC048 - CLK_PCI_EC */
 	GPIO_FUNC1,	/* S0-SC049 - LPC_CLKRUN_L */
-	GPIO_FUNC(1, PULL_UP, 10K),	/* S0-SC050 - IRQ_SERIRQ */
+	GPIO_DIRQ,	/* S0-SC050 - IRQ_SERIRQ -- using for keyboard irq */
 	GPIO_NC,	/* S0-SC051 - SMB_SOC_DATA (XDP) */
 	GPIO_NC,	/* S0-SC052 - SMB_SOC_CLK (XDP) */
 	GPIO_NC,	/* S0-SC053 - SMB_SOC_ALERTB (NC) */
@@ -213,6 +213,7 @@ static const struct soc_gpio_map gpssus_gpio_map[] = {
 static const u8 core_dedicated_irq[GPIO_MAX_DIRQS] = {
 	[TPAD_IRQ_OFFSET] = TPAD_IRQ_GPIO,
 	[TOUCH_IRQ_OFFSET] = TOUCH_IRQ_GPIO,
+	[I8042_IRQ_OFFSET] = I8042_IRQ_GPIO,
 };
 
 static const u8 sus_dedicated_irq[GPIO_MAX_DIRQS] = {
diff --git a/src/mainboard/google/rambi/irqroute.h b/src/mainboard/google/rambi/irqroute.h
index eaafff9..ddf6a76 100644
--- a/src/mainboard/google/rambi/irqroute.h
+++ b/src/mainboard/google/rambi/irqroute.h
@@ -49,6 +49,8 @@
 /* CORE bank DIRQs - up to 16 supported */
 #define TPAD_IRQ_OFFSET		0
 #define TOUCH_IRQ_OFFSET	1
+#define I8042_IRQ_OFFSET	2
 /* Corresponding SCORE GPIO pins */
 #define TPAD_IRQ_GPIO		55
 #define TOUCH_IRQ_GPIO		72
+#define I8042_IRQ_GPIO		50
diff --git a/src/mainboard/google/rambi/onboard.h b/src/mainboard/google/rambi/onboard.h
index 6a8e751..7f5d885 100644
--- a/src/mainboard/google/rambi/onboard.h
+++ b/src/mainboard/google/rambi/onboard.h
@@ -34,4 +34,6 @@
 #define BOARD_TOUCHSCREEN_I2C_BUS       5
 #define BOARD_TOUCHSCREEN_I2C_ADDR      0x4a    /* TODO(shawnn): Check this */
 
+#define BOARD_I8042_IRQ                 GPIO_S0_DED_IRQ(I8042_IRQ_OFFSET)
+
 #endif



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