[coreboot-gerrit] Patch set updated for coreboot: ed128ea mc146818rtc: Disable read_option on non-romcc code

Vladimir Serbinenko (phcoder@gmail.com) gerrit at coreboot.org
Sun Jan 26 21:09:18 CET 2014


Vladimir Serbinenko (phcoder at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4824

-gerrit

commit ed128eacfbc81a8f28647ac182a8e1762ac8032f
Author: Vladimir Serbinenko <phcoder at gmail.com>
Date:   Sun Jan 26 20:25:49 2014 +0100

    mc146818rtc: Disable read_option on non-romcc code
    
    Do not commit.
    
    Change-Id: I903aab9490bd405b0dbbbe23d2ef1db29845392b
    Signed-off-by: Vladimir Serbinenko <phcoder at gmail.com>
---
 src/cpu/amd/dualcore/dualcore.c           |  6 +++++-
 src/cpu/amd/model_10xxx/init_cpus.c       |  7 ++++--
 src/cpu/amd/model_fxx/init_cpus.c         |  7 ++++--
 src/cpu/amd/quadcore/quadcore.c           |  6 +++++-
 src/include/pc80/mc146818rtc.h            |  5 +++++
 src/mainboard/getac/p470/romstage.c       |  7 +++++-
 src/mainboard/kontron/986lcd-m/romstage.c | 25 +++++++++++++++++----
 src/mainboard/msi/ms7135/romstage.c       |  9 ++++++--
 src/mainboard/roda/rk886ex/romstage.c     |  7 +++++-
 src/northbridge/amd/amdk8/coherent_ht.c   |  6 +++++-
 src/northbridge/amd/amdk8/raminit.c       | 19 +++++++++++++---
 src/northbridge/amd/amdk8/raminit_f.c     | 36 +++++++++++++++++--------------
 12 files changed, 106 insertions(+), 34 deletions(-)

diff --git a/src/cpu/amd/dualcore/dualcore.c b/src/cpu/amd/dualcore/dualcore.c
index 69ce56a..69dcf42 100644
--- a/src/cpu/amd/dualcore/dualcore.c
+++ b/src/cpu/amd/dualcore/dualcore.c
@@ -48,8 +48,12 @@ static inline void start_other_cores(void)
 {
 	unsigned nodes;
 	unsigned nodeid;
+	u8 multi_core;
 
-	if (read_option(multi_core, 0))  {
+	if (get_option(&multi_core, "multi_core") != CB_SUCCESS)
+		multi_core = 0; /* Enabled.  */
+
+	if (multi_core)  {
 		return; // disable multi_core
 	}
 
diff --git a/src/cpu/amd/model_10xxx/init_cpus.c b/src/cpu/amd/model_10xxx/init_cpus.c
index 10c0c8a..2567610 100644
--- a/src/cpu/amd/model_10xxx/init_cpus.c
+++ b/src/cpu/amd/model_10xxx/init_cpus.c
@@ -67,12 +67,15 @@ static void for_each_ap(u32 bsp_apicid, u32 core_range, process_ap_t process_ap,
 	u32 nb_cfg_54;
 	int i, j;
 	u32 ApicIdCoreIdSize;
+	u8 multi_core;
+
+	if (get_option(&multi_core, "multi_core") != CB_SUCCESS)
+		multi_core = 0; /* Enabled.  */
 
 	/* get_nodes define in ht_wrapper.c */
 	nodes = get_nodes();
 
-	if (!CONFIG_LOGICAL_CPUS ||
-	    read_option(multi_core, 0) != 0) {	// 0 means multi core
+	if (!CONFIG_LOGICAL_CPUS || multi_core != 0) {	// 0 means multi core
 		disable_siblings = 1;
 	} else {
 		disable_siblings = 0;
diff --git a/src/cpu/amd/model_fxx/init_cpus.c b/src/cpu/amd/model_fxx/init_cpus.c
index 12d3a95..c223906 100644
--- a/src/cpu/amd/model_fxx/init_cpus.c
+++ b/src/cpu/amd/model_fxx/init_cpus.c
@@ -22,12 +22,15 @@ static void for_each_ap(u32 bsp_apicid, u32 core_range, process_ap_t process_ap,
 	u32 e0_later_single_core;
 	u32 nb_cfg_54;
 	int i, j;
+	u8 multi_core;
+
+	if (get_option(&multi_core, "multi_core") != CB_SUCCESS)
+		multi_core = 0; /* Enabled.  */
 
 	/* get_nodes define in in_coherent_ht.c */
 	nodes = get_nodes();
 
-	if (!CONFIG_LOGICAL_CPUS ||
-	    read_option(multi_core, 0) != 0) {	// 0 means multi core
+	if (!CONFIG_LOGICAL_CPUS || multi_core != 0) {	// 0 means multi core
 		disable_siblings = 1;
 	} else {
 		disable_siblings = 0;
diff --git a/src/cpu/amd/quadcore/quadcore.c b/src/cpu/amd/quadcore/quadcore.c
index feff3e1..741d7a0 100644
--- a/src/cpu/amd/quadcore/quadcore.c
+++ b/src/cpu/amd/quadcore/quadcore.c
@@ -80,9 +80,13 @@ static void start_other_cores(void)
 {
 	u32 nodes;
 	u32 nodeid;
+	u8 multi_core;
+
+	if (get_option(&multi_core, "multi_core") != CB_SUCCESS)
+		multi_core = 0; /* Enabled.  */
 
 	// disable multi_core
-	if (read_option(multi_core, 0) != 0)  {
+	if (multi_core != 0)  {
 		printk(BIOS_DEBUG, "Skip additional core init\n");
 		return;
 	}
diff --git a/src/include/pc80/mc146818rtc.h b/src/include/pc80/mc146818rtc.h
index fd40308..11aed88 100644
--- a/src/include/pc80/mc146818rtc.h
+++ b/src/include/pc80/mc146818rtc.h
@@ -188,8 +188,12 @@ static inline enum cb_err get_option(void *dest __attribute__((unused)),
 #else
 #include <drivers/pc80/mc146818rtc_early.c>
 #endif
+
+#if defined(__ROMCC__)
 #define read_option(name, default) read_option_lowlevel(CMOS_VSTART_ ##name, CMOS_VLEN_ ##name, (default))
+#endif
 
+#if defined(__ROMCC__)
 #if CONFIG_CMOS_POST
 #if CONFIG_USE_OPTION_TABLE
 # include "option_table.h"
@@ -201,6 +205,7 @@ static inline enum cb_err get_option(void *dest __attribute__((unused)),
 #  error "Must define CONFIG_CMOS_POST_OFFSET"
 # endif
 #endif
+#endif
 
 /*
  *    0 = Bank Select Magic
diff --git a/src/mainboard/getac/p470/romstage.c b/src/mainboard/getac/p470/romstage.c
index a081a8a..4e5902b 100644
--- a/src/mainboard/getac/p470/romstage.c
+++ b/src/mainboard/getac/p470/romstage.c
@@ -82,7 +82,12 @@ void setup_ich7_gpios(void)
 static void ich7_enable_lpc(void)
 {
 	int lpt_en = 0;
-	if (read_option(lpt, 0) != 0) {
+	u8 val;
+
+	if (get_option(&val, "lpt") != CB_SUCCESS)
+		val = 0;
+
+	if (val != 0) {
 	       lpt_en = 1<<2; // enable LPT
 	}
 	// Enable Serial IRQ
diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c
index 549facd..39cbbf4 100644
--- a/src/mainboard/kontron/986lcd-m/romstage.c
+++ b/src/mainboard/kontron/986lcd-m/romstage.c
@@ -58,7 +58,12 @@ void setup_ich7_gpios(void)
 static void ich7_enable_lpc(void)
 {
 	int lpt_en = 0;
-	if (read_option(lpt, 0) != 0) {
+	u8 val;
+
+	if (get_option(&val, "lpt") != CB_SUCCESS)
+		val = 0;
+
+	if (val != 0) {
 		lpt_en = 1<<2; // enable LPT
 	}
 	// Enable Serial IRQ
@@ -222,23 +227,35 @@ static void rcba_config(void)
 	 * routing.
 	 */
 	int port_shuffle = 0;
+	u8 val;
 
 	/* Disable unused devices */
 	reg32 = FD_ACMOD|FD_ACAUD|FD_PATA;
 	reg32 |= FD_PCIE6|FD_PCIE5|FD_PCIE4;
 
-	if (read_option(ethernet1, 0) != 0) {
+	if (get_option(&val, "ethernet1") != CB_SUCCESS)
+		val = 0;
+
+	if (val != 0) {
 		printk(BIOS_DEBUG, "Disabling ethernet adapter 1.\n");
 		reg32 |= FD_PCIE1;
 	}
-	if (read_option(ethernet2, 0) != 0) {
+
+	if (get_option(&val, "ethernet2") != CB_SUCCESS)
+		val = 0;
+
+	if (val != 0) {
 		printk(BIOS_DEBUG, "Disabling ethernet adapter 2.\n");
 		reg32 |= FD_PCIE2;
 	} else {
 		if (reg32 & FD_PCIE1)
 			port_shuffle = 1;
 	}
-	if (read_option(ethernet3, 0) != 0) {
+
+	if (get_option(&val, "ethernet3") != CB_SUCCESS)
+		val = 0;
+
+	if (val != 0) {
 		printk(BIOS_DEBUG, "Disabling ethernet adapter 3.\n");
 		reg32 |= FD_PCIE3;
 	} else {
diff --git a/src/mainboard/msi/ms7135/romstage.c b/src/mainboard/msi/ms7135/romstage.c
index ebe2526..ba99388 100644
--- a/src/mainboard/msi/ms7135/romstage.c
+++ b/src/mainboard/msi/ms7135/romstage.c
@@ -69,7 +69,10 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 static void ms7135_set_ram_voltage(void)
 {
 	u8 b;
-	b = read_option(ram_voltage, 0);
+
+	if (get_option(&b, "ram_voltage") != CB_SUCCESS)
+		b = 0;
+
 	if (b > 4) /* default if above 2.70v */
 		b = 0;
 	printk(BIOS_INFO, "setting RAM voltage %08x\n", b);
@@ -79,7 +82,9 @@ static void ms7135_set_ram_voltage(void)
 static void ms7135_set_nf4_voltage(void)
 {
 	u8 b;
-	b = read_option(nf4_voltage, 0);
+	if (get_option(&b, "nf4_voltage") != CB_SUCCESS)
+		b = 0;
+
 	if (b > 2) /* default if above 1.60v */
 		b = 0;
 	b |= 0x10;
diff --git a/src/mainboard/roda/rk886ex/romstage.c b/src/mainboard/roda/rk886ex/romstage.c
index ad323f5..88c3de0 100644
--- a/src/mainboard/roda/rk886ex/romstage.c
+++ b/src/mainboard/roda/rk886ex/romstage.c
@@ -69,7 +69,12 @@ void setup_ich7_gpios(void)
 static void ich7_enable_lpc(void)
 {
 	int lpt_en = 0;
-	if (read_option(lpt, 0) != 0) {
+	u8 val;
+
+	if (get_option(&val, "lpt") != CB_SUCCESS)
+		val = 0;
+
+	if (val != 0) {
 	       lpt_en = 1<<2; // enable LPT
 	}
 	// Enable Serial IRQ
diff --git a/src/northbridge/amd/amdk8/coherent_ht.c b/src/northbridge/amd/amdk8/coherent_ht.c
index 22d74c2..72804ad 100644
--- a/src/northbridge/amd/amdk8/coherent_ht.c
+++ b/src/northbridge/amd/amdk8/coherent_ht.c
@@ -1598,8 +1598,12 @@ static void coherent_ht_finalize(unsigned nodes)
 #endif
 #if CONFIG_LOGICAL_CPUS
 	unsigned total_cpus;
+	u8 multi_core;
 
-	if (read_option(multi_core, 0) == 0) { /* multi_core */
+	if (get_option(&multi_core, "multi_core") != CB_SUCCESS)
+		multi_core = 0; /* Enabled.  */
+
+	if (multi_core == 0) { /* multi_core */
 		total_cpus = verify_dualcore(nodes);
 	}
 	else {
diff --git a/src/northbridge/amd/amdk8/raminit.c b/src/northbridge/amd/amdk8/raminit.c
index e4fe3df..ce2ec04 100644
--- a/src/northbridge/amd/amdk8/raminit.c
+++ b/src/northbridge/amd/amdk8/raminit.c
@@ -546,13 +546,17 @@ static void sdram_set_registers(const struct mem_controller *ctrl)
 static void hw_enable_ecc(const struct mem_controller *ctrl)
 {
 	uint32_t dcl, nbcap;
+	u8 ecc_memory;
 	nbcap = pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP);
 	dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
 	dcl &= ~DCL_DimmEccEn;
 	if (nbcap & NBCAP_ECC) {
 		dcl |= DCL_DimmEccEn;
 	}
-	if (read_option(ECC_memory, 1) == 0) {
+	if (get_option(&ecc_memory, "ECC_memory") != CB_SUCCESS)
+		ecc_memory = 1;
+
+	if (ecc_memory == 0) {
 		dcl &= ~DCL_DimmEccEn;
 	}
 	pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl);
@@ -1103,8 +1107,12 @@ static unsigned long memory_end_k(const struct mem_controller *ctrl, int max_nod
 static void order_dimms(const struct mem_controller *ctrl)
 {
 	unsigned long tom_k, base_k;
+	u8 val;
+
+	if (get_option(&val, "interleave_chip_selects") != CB_SUCCESS)
+		val = 1;
 
-	if (read_option(interleave_chip_selects, 1) != 0) {
+	if (val != 0) {
 		tom_k = interleave_chip_selects(ctrl);
 	} else {
 		printk(BIOS_DEBUG, "Interleaving disabled\n");
@@ -1582,6 +1590,7 @@ static struct spd_set_memclk_result spd_set_memclk(const struct mem_controller *
 	unsigned char cl_at_freq[NBCAP_MEMCLK_MASK + 1];
 	int dimm, freq, max_freq_bios, max_freq_dloading, max_freq_1t;
 	uint32_t value;
+	u8 val;
 
 	static const uint8_t spd_min_cycle_time_indices[] = { 9, 23, 25 };
 	static const unsigned char cycle_time_at_freq[] = {
@@ -1603,7 +1612,11 @@ static struct spd_set_memclk_result spd_set_memclk(const struct mem_controller *
 	memset(cl_at_freq, 0x00,
 		(pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP) >>
 		 NBCAP_MEMCLK_SHIFT) & NBCAP_MEMCLK_MASK);
-	max_freq_bios = read_option(max_mem_clock, 0);
+
+	if (get_option(&val, "max_mem_clock") != CB_SUCCESS)
+		val = 0;
+
+	max_freq_bios = val;
 	if (max_freq_bios <= NBCAP_MEMCLK_100MHZ)
 		memset(cl_at_freq, 0x00, max_freq_bios);
 	for (dimm = 0; dimm < DIMM_SOCKETS; dimm++) {
diff --git a/src/northbridge/amd/amdk8/raminit_f.c b/src/northbridge/amd/amdk8/raminit_f.c
index 9c99250..cf8befe 100644
--- a/src/northbridge/amd/amdk8/raminit_f.c
+++ b/src/northbridge/amd/amdk8/raminit_f.c
@@ -1112,7 +1112,12 @@ static unsigned long interleave_chip_selects(const struct mem_controller *ctrl,
 	 * and if so count them.
 	 */
 #if defined(CMOS_VSTART_interleave_chip_selects)
-	if (read_option(interleave_chip_selects, 1) == 0)
+	u8 val;
+
+	if (get_option(&val, "interleave_chip_selects") != CB_SUCCESS)
+		val = 1;
+
+	if (val == 0)
 		return 0;
 #else
 #if !defined(CONFIG_INTERLEAVE_CHIP_SELECTS) || !CONFIG_INTERLEAVE_CHIP_SELECTS
@@ -1808,17 +1813,18 @@ static struct spd_set_memclk_result spd_set_memclk(const struct mem_controller *
 
 	value = pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP);
 	min_cycle_time = min_cycle_times[(value >> NBCAP_MEMCLK_SHIFT) & NBCAP_MEMCLK_MASK];
-	bios_cycle_time = min_cycle_times[
-#ifdef CMOS_VSTART_max_mem_clock
-		read_option(max_mem_clock, 0)
-#else
+
+	u8 max_mem_clock;
+
+	if (get_option(&max_mem_clock, "max_mem_clock") != CB_SUCCESS) {
 #if defined(CONFIG_MAX_MEM_CLOCK)
-		CONFIG_MAX_MEM_CLOCK
+		max_mem_clock = CONFIG_MAX_MEM_CLOCK;
 #else
-		0 // use DDR400 as default
-#endif
+		max_mem_clock = 0; /* use DDR400 as default */
 #endif
-	];
+	}
+
+	bios_cycle_time = min_cycle_times[max_mem_clock];
 
 	if (bios_cycle_time > min_cycle_time) {
 		min_cycle_time = bios_cycle_time;
@@ -2370,6 +2376,7 @@ static void set_ecc(const struct mem_controller *ctrl,
 {
 	int i;
 	int value;
+	u8 ecc_memory;
 
 	uint32_t dcl, nbcap;
 	nbcap = pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP);
@@ -2378,15 +2385,12 @@ static void set_ecc(const struct mem_controller *ctrl,
 	if (nbcap & NBCAP_ECC) {
 		dcl |= DCL_DimmEccEn;
 	}
-#ifdef CMOS_VSTART_ECC_memory
-	if (read_option(ECC_memory, 1) == 0) {
+	if (get_option(&ecc_memory, "ECC_memory") != CB_SUCCESS)
+		ecc_memory = 1;
+
+	if (ecc_memory == 0) {
 		dcl &= ~DCL_DimmEccEn;
 	}
-#else // CMOS_VSTART_ECC_memory not defined
-#if !CONFIG_ECC_MEMORY
-	dcl &= ~DCL_DimmEccEn;
-#endif
-#endif
 	pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl);
 
 	meminfo->is_ecc = 1;



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