[coreboot-gerrit] New patch to review for coreboot: 9117d7c supermicro/h8qme_fam10/romstage.c: indent.
Vladimir Serbinenko (phcoder@gmail.com)
gerrit at coreboot.org
Sun Jan 26 02:51:33 CET 2014
Vladimir Serbinenko (phcoder at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4813
-gerrit
commit 9117d7cd977390ba98a4ba8ebb17d37abb499658
Author: Vladimir Serbinenko <phcoder at gmail.com>
Date: Fri Jan 24 08:34:17 2014 +0100
supermicro/h8qme_fam10/romstage.c: indent.
Change-Id: I46f2dee895932303023239c2d72eb60793ca07a8
Signed-off-by: Vladimir Serbinenko <phcoder at gmail.com>
---
src/mainboard/supermicro/h8qme_fam10/romstage.c | 192 ++++++++++++------------
1 file changed, 99 insertions(+), 93 deletions(-)
diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c
index 2c4a02e..2619606 100644
--- a/src/mainboard/supermicro/h8qme_fam10/romstage.c
+++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c
@@ -33,7 +33,7 @@
#include <lib.h>
#include <spd.h>
#include <cpu/amd/model_10xxx_rev.h>
-#include "southbridge/nvidia/mcp55/early_smbus.c" // for enable the FAN
+#include "southbridge/nvidia/mcp55/early_smbus.c" // for enable the FAN
#include "northbridge/amd/amdfam10/raminit.h"
#include "northbridge/amd/amdfam10/amdfam10.h"
#include "lib/delay.c"
@@ -76,23 +76,23 @@ static inline int spd_read_byte(unsigned device, unsigned address)
static void sio_setup(void)
{
- uint32_t dword;
- uint8_t byte;
- enable_smbus();
-// smbusx_write_byte(1, (0x58>>1), 0, 0x80); /* select bank0 */
- smbusx_write_byte(1, (0x58>>1), 0xb1, 0xff); /* set FAN ctrl to DC mode */
-
- byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b);
- byte |= 0x20;
- pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte);
-
- dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0);
- dword |= (1<<0);
- pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword);
-
- dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4);
- dword |= (1<<16);
- pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword);
+ uint32_t dword;
+ uint8_t byte;
+ enable_smbus();
+// smbusx_write_byte(1, (0x58>>1), 0, 0x80); /* select bank0 */
+ smbusx_write_byte(1, (0x58 >> 1), 0xb1, 0xff); /* set FAN ctrl to DC mode */
+
+ byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0x7b);
+ byte |= 0x20;
+ pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0x7b, byte);
+
+ dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0xa0);
+ dword |= (1 << 0);
+ pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0xa0, dword);
+
+ dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0xa4);
+ dword |= (1 << 16);
+ pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0xa4, dword);
}
static const u8 spd_addr[] = {
@@ -106,7 +106,7 @@ static const u8 spd_addr[] = {
//third node
RC02, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
//forth node
- RC03, DIMM4, DIMM6,0 , 0, DIMM5, DIMM7, 0, 0,
+ RC03, DIMM4, DIMM6, 0, 0, DIMM5, DIMM7, 0, 0,
#endif
};
@@ -157,23 +157,23 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
u32 bsp_apicid = 0, val, wants_reset;
msr_t msr;
- if (!cpu_init_detectedx && boot_cpu()) {
+ if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
set_bsp_node_CHtExtNodeCfgEn();
enumerate_ht_chain();
sio_setup();
- }
+ }
- post_code(0x30);
+ post_code(0x30);
- if (bist == 0)
+ if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
- post_code(0x32);
+ post_code(0x32);
- w83627hf_set_clksel_48(DUMMY_DEV);
- w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+ w83627hf_set_clksel_48(DUMMY_DEV);
+ w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init();
write_GPIO();
@@ -182,103 +182,106 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
- val = cpuid_eax(1);
- printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
- printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
- printk(BIOS_DEBUG, "bsp_apicid = %02x \n", bsp_apicid);
- printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
+ val = cpuid_eax(1);
+ printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
+ printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n", sysinfo, sysinfo + 1);
+ printk(BIOS_DEBUG, "bsp_apicid = %02x \n", bsp_apicid);
+ printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
- /* Setup sysinfo defaults */
- set_sysinfo_in_ram(0);
+ /* Setup sysinfo defaults */
+ set_sysinfo_in_ram(0);
- update_microcode(val);
+ update_microcode(val);
- post_code(0x33);
+ post_code(0x33);
- cpuSetAMDMSR();
- post_code(0x34);
+ cpuSetAMDMSR();
+ post_code(0x34);
- amd_ht_init(sysinfo);
- post_code(0x35);
+ amd_ht_init(sysinfo);
+ post_code(0x35);
- /* Setup nodes PCI space and start core 0 AP init. */
- finalize_node_setup(sysinfo);
+ /* Setup nodes PCI space and start core 0 AP init. */
+ finalize_node_setup(sysinfo);
- /* Setup any mainboard PCI settings etc. */
- setup_mb_resource_map();
- post_code(0x36);
+ /* Setup any mainboard PCI settings etc. */
+ setup_mb_resource_map();
+ post_code(0x36);
- /* wait for all the APs core0 started by finalize_node_setup. */
- /* FIXME: A bunch of cores are going to start output to serial at once.
- * It would be nice to fixup prink spinlocks for ROM XIP mode.
- * I think it could be done by putting the spinlock flag in the cache
- * of the BSP located right after sysinfo.
- */
+ /* wait for all the APs core0 started by finalize_node_setup. */
+ /* FIXME: A bunch of cores are going to start output to serial at once.
+ * It would be nice to fixup prink spinlocks for ROM XIP mode.
+ * I think it could be done by putting the spinlock flag in the cache
+ * of the BSP located right after sysinfo.
+ */
- wait_all_core0_started();
+ wait_all_core0_started();
#if CONFIG_LOGICAL_CPUS
- /* Core0 on each node is configured. Now setup any additional cores. */
- printk(BIOS_DEBUG, "start_other_cores()\n");
- start_other_cores();
- post_code(0x37);
- wait_all_other_cores_started(bsp_apicid);
+ /* Core0 on each node is configured. Now setup any additional cores. */
+ printk(BIOS_DEBUG, "start_other_cores()\n");
+ start_other_cores();
+ post_code(0x37);
+ wait_all_other_cores_started(bsp_apicid);
#endif
- post_code(0x38);
+ post_code(0x38);
#if CONFIG_SET_FIDVID
- msr = rdmsr(0xc0010071);
- printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
+ msr = rdmsr(0xc0010071);
+ printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n",
+ msr.hi, msr.lo);
- /* FIXME: The sb fid change may survive the warm reset and only
- * need to be done once.*/
+ /* FIXME: The sb fid change may survive the warm reset and only
+ * need to be done once.*/
- enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
- post_code(0x39);
+ enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
+ post_code(0x39);
- if (!warm_reset_detect(0)) { // BSP is node 0
- init_fidvid_bsp(bsp_apicid, sysinfo->nodes);
- } else {
- init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0
- }
+ if (!warm_reset_detect(0)) { // BSP is node 0
+ init_fidvid_bsp(bsp_apicid, sysinfo->nodes);
+ } else {
+ init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0
+ }
- post_code(0x3A);
+ post_code(0x3A);
- /* show final fid and vid */
- msr=rdmsr(0xc0010071);
- printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
+ /* show final fid and vid */
+ msr = rdmsr(0xc0010071);
+ printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi,
+ msr.lo);
#endif
- init_timer(); // Need to use TMICT to synconize FID/VID
+ init_timer(); // Need to use TMICT to synconize FID/VID
- wants_reset = mcp55_early_setup_x();
+ wants_reset = mcp55_early_setup_x();
- /* Reset for HT, FIDVID, PLL and errata changes to take affect. */
- if (!warm_reset_detect(0)) {
- print_info("...WARM RESET...\n\n\n");
- soft_reset();
- die("After soft_reset_x - shouldn't see this message!!!\n");
- }
+ /* Reset for HT, FIDVID, PLL and errata changes to take affect. */
+ if (!warm_reset_detect(0)) {
+ print_info("...WARM RESET...\n\n\n");
+ soft_reset();
+ die("After soft_reset_x - shouldn't see this message!!!\n");
+ }
- if (wants_reset)
- printk(BIOS_DEBUG, "mcp55_early_setup_x wanted additional reset!\n");
+ if (wants_reset)
+ printk(BIOS_DEBUG,
+ "mcp55_early_setup_x wanted additional reset!\n");
- post_code(0x3B);
+ post_code(0x3B);
/* It's the time to set ctrl in sysinfo now; */
-printk(BIOS_DEBUG, "fill_mem_ctrl()\n");
-fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
+ printk(BIOS_DEBUG, "fill_mem_ctrl()\n");
+ fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
-post_code(0x3D);
+ post_code(0x3D);
//printk(BIOS_DEBUG, "enable_smbus()\n");
// enable_smbus(); /* enable in sio_setup */
-post_code(0x40);
+ post_code(0x40);
- printk(BIOS_DEBUG, "raminit_amdmct()\n");
- raminit_amdmct(sysinfo);
- post_code(0x41);
+ printk(BIOS_DEBUG, "raminit_amdmct()\n");
+ raminit_amdmct(sysinfo);
+ post_code(0x41);
}
/**
@@ -300,11 +303,14 @@ post_code(0x40);
* @param[out] BOOL result = true to use a manual list
* false to initialize the link automatically
*/
-BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List)
+BOOL AMD_CB_ManualBUIDSwapList(u8 node, u8 link, const u8 ** List)
{
- static const u8 swaplist[] = { 0xFF, CONFIG_HT_CHAIN_UNITID_BASE, CONFIG_HT_CHAIN_END_UNITID_BASE, 0xFF };
+ static const u8 swaplist[] =
+ { 0xFF, CONFIG_HT_CHAIN_UNITID_BASE,
+CONFIG_HT_CHAIN_END_UNITID_BASE, 0xFF };
/* If the BUID was adjusted in early_ht we need to do the manual override */
- if ((CONFIG_HT_CHAIN_UNITID_BASE != 0) && (CONFIG_HT_CHAIN_END_UNITID_BASE != 0)) {
+ if ((CONFIG_HT_CHAIN_UNITID_BASE != 0)
+ && (CONFIG_HT_CHAIN_END_UNITID_BASE != 0)) {
printk(BIOS_DEBUG, "AMD_CB_ManualBUIDSwapList()\n");
if ((node == 0) && (link == 0)) { /* BSP SB link */
*List = swaplist;
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