[coreboot-gerrit] Patch set updated for coreboot: 82e6a71 X201: Enable expresscard hotplug.
Vladimir Serbinenko (phcoder@gmail.com)
gerrit at coreboot.org
Thu Jan 23 20:09:11 CET 2014
Vladimir Serbinenko (phcoder at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4643
-gerrit
commit 82e6a719141473a303bf7022c760dcfca4036848
Author: Vladimir Serbinenko <phcoder at gmail.com>
Date: Fri Jan 10 19:30:54 2014 +0100
X201: Enable expresscard hotplug.
Change-Id: Ieefc2ad775c16de9aa974b2602d55ee047c9f568
Signed-off-by: Vladimir Serbinenko <phcoder at gmail.com>
---
src/mainboard/lenovo/x201/acpi/gpe.asl | 14 ++++++++++++++
src/mainboard/lenovo/x201/devicetree.cb | 5 +++++
src/mainboard/lenovo/x201/dsdt.asl | 1 +
src/mainboard/lenovo/x201/mainboard.c | 8 ++++++++
src/southbridge/intel/bd82x6x/acpi/pcie.asl | 11 +++++++++++
5 files changed, 39 insertions(+)
diff --git a/src/mainboard/lenovo/x201/acpi/gpe.asl b/src/mainboard/lenovo/x201/acpi/gpe.asl
index b160b50..2f0ee16 100644
--- a/src/mainboard/lenovo/x201/acpi/gpe.asl
+++ b/src/mainboard/lenovo/x201/acpi/gpe.asl
@@ -27,4 +27,18 @@ Scope (\_GPE)
/* Read EC register to clear wake status */
Store(\_SB.PCI0.LPCB.EC.WAKE, Local0)
}
+
+ Method (_L01, 0, NotSerialized)
+ {
+ If (\_SB.PCI0.RP04.HPCS)
+ {
+ Sleep (100)
+ Store (0x01, \_SB.PCI0.RP04.HPCS)
+ If (\_SB.PCI0.RP04.PDC)
+ {
+ Store (0x01, \_SB.PCI0.RP04.PDC)
+ Notify (\_SB.PCI0.RP04, 0x00)
+ }
+ }
+ }
}
diff --git a/src/mainboard/lenovo/x201/devicetree.cb b/src/mainboard/lenovo/x201/devicetree.cb
index f45fadf..a8831c2 100644
--- a/src/mainboard/lenovo/x201/devicetree.cb
+++ b/src/mainboard/lenovo/x201/devicetree.cb
@@ -129,6 +129,11 @@ chip northbridge/intel/nehalem
device pci 1b.0 on # Audio Controller
subsystemid 0x17aa 0x215e
end
+
+ device pci 1c.0 on end # PCIe Port #1
+ device pci 1c.3 on end # PCIe Port #4 (Expresscard)
+ device pci 1c.4 on end # PCIe Port #4 (wlan)
+
device pci 1d.0 on # USB2 EHCI
subsystemid 0x17aa 0x2163
end
diff --git a/src/mainboard/lenovo/x201/dsdt.asl b/src/mainboard/lenovo/x201/dsdt.asl
index 783122e..0c921a6 100644
--- a/src/mainboard/lenovo/x201/dsdt.asl
+++ b/src/mainboard/lenovo/x201/dsdt.asl
@@ -23,6 +23,7 @@
#define BRIGHTNESS_UP \_SB.PCI0.GFX0.LCD0.INCB
#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.LCD0.DECB
#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0
+#define RP04_IS_EXPRESSCARD 1
DefinitionBlock(
"dsdt.aml",
diff --git a/src/mainboard/lenovo/x201/mainboard.c b/src/mainboard/lenovo/x201/mainboard.c
index 75e44f4..c16c3a4 100644
--- a/src/mainboard/lenovo/x201/mainboard.c
+++ b/src/mainboard/lenovo/x201/mainboard.c
@@ -163,6 +163,14 @@ static void mainboard_enable(device_t dev)
*/
pc_keyboard_init(0);
verb_setup();
+
+ /* Enable expresscard hotplug events. */
+ pci_write_config32(dev_find_slot(0, PCI_DEVFN(0x1c, 3)),
+ 0xd8,
+ pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x1c, 3)), 0xd8)
+ | (1 << 30));
+ pci_write_config16(dev_find_slot(0, PCI_DEVFN(0x1c, 3)),
+ 0x42, 0x142);
}
struct chip_operations mainboard_ops = {
diff --git a/src/southbridge/intel/bd82x6x/acpi/pcie.asl b/src/southbridge/intel/bd82x6x/acpi/pcie.asl
index 9cac321..14ae449 100644
--- a/src/southbridge/intel/bd82x6x/acpi/pcie.asl
+++ b/src/southbridge/intel/bd82x6x/acpi/pcie.asl
@@ -177,6 +177,17 @@ Device (RP04)
{
Return (IRQM (RPPN))
}
+
+#ifdef RP04_IS_EXPRESSCARD
+ Device (SLOT)
+ {
+ Name (_ADR, 0x00)
+ Method (_RMV, 0, NotSerialized)
+ {
+ Return (0x01)
+ }
+ }
+#endif
}
Device (RP05)
More information about the coreboot-gerrit
mailing list