[coreboot-gerrit] New patch to review for coreboot: ce74ebf Revert "Butterfly, Stout: Force SATA link speed to 3 Gbps"

[Alexandru Gagniuc (mr.nuke.me@gmail.com)]

Alexandru Gagniuc (mr.nuke.me at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4762

-gerrit

commit ce74ebf93a65dcee9b6b445cb59071cacbb0c3f5
Author: Alexandru Gagniuc <mr.nuke.me at gmail.com>
Date:   Mon Jan 20 22:26:05 2014 +0100

    Revert "Butterfly, Stout: Force SATA link speed to 3 Gbps"
    
    This reverts commit 7b8952c19d8d809b7aeec629b31e1c3d66f19884.
    This commit was a hack with no real usefulness, as there is no way to
    replace the shipping coreboot on a write-protected chromebook. As a
    result, this change was irrelevant, and only affects people who
    compiled and installed coreboot post-mortem. Kill it.
    
    Change-Id: Ia35f7e8a24f9cb701ce0e357d9b3e929c4e0a4fb
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>
---
 src/mainboard/google/butterfly/devicetree.cb | 5 +----
 src/mainboard/google/stout/devicetree.cb     | 2 --
 2 files changed, 1 insertion(+), 6 deletions(-)

diff --git a/src/mainboard/google/butterfly/devicetree.cb b/src/mainboard/google/butterfly/devicetree.cb
index e7a50c0..ca8118a 100644
--- a/src/mainboard/google/butterfly/devicetree.cb
+++ b/src/mainboard/google/butterfly/devicetree.cb
@@ -58,10 +58,7 @@ chip northbridge/intel/sandybridge
 
 			register "ide_legacy_combined" = "0x0"
 			register "sata_ahci" = "0x1"
-			# Enable SATA ports 0 & 1
-			register "sata_port_map" = "0x3"
-			# Set max SATA speed to 3.0 Gb/s
-			register "sata_interface_speed_support" = "0x2"
+			register "sata_port_map" = "0x3"	#enable SATA ports 0 & 1
 
 			# Enable EC Port 0x68/0x6C
 			register "gen1_dec" = "0x00040069"
diff --git a/src/mainboard/google/stout/devicetree.cb b/src/mainboard/google/stout/devicetree.cb
index 6e02020..c58a8d6 100644
--- a/src/mainboard/google/stout/devicetree.cb
+++ b/src/mainboard/google/stout/devicetree.cb
@@ -60,8 +60,6 @@ chip northbridge/intel/sandybridge
 			register "ide_legacy_combined" = "0x0"
 			register "sata_ahci" = "0x1"
 			register "sata_port_map" = "0x3"
-			# Set max SATA speed to 3.0 Gb/s
-			register "sata_interface_speed_support" = "0x2"
 
 			# Enable EC Port 0x68/0x6C
 			register "gen1_dec" = "0x00040069"