[coreboot-gerrit] New patch to review for coreboot: 25a382e cpu/allwinner/a10: Clarify positioning of boot stages
Alexandru Gagniuc (mr.nuke.me@gmail.com)
gerrit at coreboot.org
Tue Jan 14 07:53:39 CET 2014
Alexandru Gagniuc (mr.nuke.me at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4687
-gerrit
commit 25a382ec27d3e0e2a3edc3a6eaabb5895e6ab1de
Author: Alexandru Gagniuc <mr.nuke.me at gmail.com>
Date: Sat Dec 28 15:42:31 2013 -0500
cpu/allwinner/a10: Clarify positioning of boot stages
This fixes a number of potential issues, such as generating a build
failure if the bootblock is too large, and making sure romstage and
ramstage cannot overlap in memory.
Change-Id: I4ca9ad097b145445316bcd962e007731b08a7fda
Signed-off-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>
---
src/cpu/allwinner/a10/Kconfig | 10 ++++++----
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/src/cpu/allwinner/a10/Kconfig b/src/cpu/allwinner/a10/Kconfig
index b782b9a..347e315 100644
--- a/src/cpu/allwinner/a10/Kconfig
+++ b/src/cpu/allwinner/a10/Kconfig
@@ -34,14 +34,16 @@ config CBFS_HEADER_ROM_OFFSET
hex
default 0x10
+# This is the maximum size bootblock that the BROM will load. If the bootblock
+# gets larger, this will generate a build failure, rather than a silent
+# "coreboot won't run" failure.
config CBFS_ROM_OFFSET
- # Calculated by BL1 + max bootblock size.
- default 0x4c00
+ default 0x5fe0
-# FIXME: untested
+# 16 MiB above ramstage, so there is no overlap
config ROMSTAGE_BASE
hex
- default SYS_SDRAM_BASE
+ default 0x41000000
# Keep the stack in SRAM block A2.
# SRAM blocks A1 (0-16KiB) and A2 (16KiB-32KiB) are always accessible to the
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