[coreboot-gerrit] New patch to review for coreboot: 29fe00a cubieboard: Setup CPU clock in romstage and load ramstage
Alexandru Gagniuc (mr.nuke.me@gmail.com)
gerrit at coreboot.org
Tue Jan 14 07:43:07 CET 2014
Alexandru Gagniuc (mr.nuke.me at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4686
-gerrit
commit 29fe00a9915d1f8bf49a3cc1df38831b8d101cc9
Author: Alexandru Gagniuc <mr.nuke.me at gmail.com>
Date: Fri Jan 3 01:27:23 2014 -0500
cubieboard: Setup CPU clock in romstage and load ramstage
This completes the romstage for the cubieboard.
Change-Id: If3272d8a9e414f782892bc41b34b5e2dece5d7e1
Signed-off-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>
---
src/mainboard/cubietech/cubieboard/romstage.c | 28 ++++++++++++++++++++++++---
1 file changed, 25 insertions(+), 3 deletions(-)
diff --git a/src/mainboard/cubietech/cubieboard/romstage.c b/src/mainboard/cubietech/cubieboard/romstage.c
index 1b4d886..199842b 100644
--- a/src/mainboard/cubietech/cubieboard/romstage.c
+++ b/src/mainboard/cubietech/cubieboard/romstage.c
@@ -1,10 +1,17 @@
/*
- * Placeholder for Cubieboard romstage
+ * Basic romstage for Cubieboard
+ *
+ * Set up system voltages, then increase the CPU clock, before turning control
+ * to ramstage. The CPU VDD needs to be properly set before it can run at full
+ * speed. Setting the CPU at full speed helps lzma-decompress ramstage a lot
+ * faster.
*
* Copyright (C) 2013 Alexandru Gagniuc <mr.nuke.me at gmail.com>
* Subject to the GNU GPL v2, or (at your option) any later version.
*/
+#include <arch/stages.h>
+#include <cbfs.h>
#include <console/console.h>
#include <cpu/allwinner/a10/clock.h>
#include <cpu/allwinner/a10/gpio.h>
@@ -63,10 +70,25 @@ static enum cb_err cubieboard_setup_power(void)
void main(void)
{
+ void *entry;
+ enum cb_err err;
+
console_init();
- printk(BIOS_INFO, "You have managed to succesfully load romstage.\n");
/* Configure power rails */
- cubieboard_setup_power();
+ err = cubieboard_setup_power();
+
+ if (err == CB_SUCCESS) {
+ /* TODO: Get this clock from devicetree.cb */
+ a1x_set_cpu_clock(1008);
+ } else {
+ /* cubieboard_setup_power() prints more details */
+ printk(BIOS_WARNING, "Will run CPU at reduced speed\n");
+ a1x_set_cpu_clock(384);
+ }
+
+ entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/coreboot_ram");
+ printk(BIOS_INFO, "entry is 0x%p, leaving romstage.\n", entry);
+ stage_exit(entry);
}
More information about the coreboot-gerrit
mailing list