[coreboot-gerrit] Patch set updated for coreboot: 544e59a Lenovo ThinkPad T60: Formatting and spelling fixes in `romstage.c`

[Ronald G. Minnich (rminnich@gmail.com)]

Ronald G. Minnich (rminnich at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3588

-gerrit

commit 544e59a7d8a13f1332ea622bb67be21b94d551ab
Author: Paul Menzel <paulepanter at users.sourceforge.net>
Date:   Mon Apr 29 23:16:27 2013 +0200

    Lenovo ThinkPad T60: Formatting and spelling fixes in `romstage.c`
    
    
    Change-Id: I507dc8c824860e4606b90e8ab11fa1bb85d8c001
    Signed-off-by: Paul Menzel <paulepanter at users.sourceforge.net>
---
 src/mainboard/lenovo/t60/romstage.c | 58 ++++++++++++++++++++-----------------
 1 file changed, 31 insertions(+), 27 deletions(-)

diff --git a/src/mainboard/lenovo/t60/romstage.c b/src/mainboard/lenovo/t60/romstage.c
index 5bb7ac1..0ef8d09 100644
--- a/src/mainboard/lenovo/t60/romstage.c
+++ b/src/mainboard/lenovo/t60/romstage.c
@@ -44,22 +44,22 @@ void setup_ich7_gpios(void)
 	printk(BIOS_DEBUG, " GPIOS...");
 
 	/* T60 GPIO:
-	    6: LEGACYIO#
-	    7: BDC_PRESENCE#
-	    8: H8_WAKE#
-	   10: MDI_DETECT
-	   12: H8SCI#
-	   14: CPUSB#
-	   15: CPPE#
-	   25: MDC_KILL#
-	   27: EXC_PWR_CTRL
-	   28: EXC_AUX_CTRL
-	   35: CLKREQ_SATA#
-	   36: PLANARID0
-	   37: PLANARID1
-	   38: PLANARID2
-	   39: PLANARID3
-	*/
+	 * 6: LEGACYIO#
+	 * 7: BDC_PRESENCE#
+	 * 8: H8_WAKE#
+	 * 10: MDI_DETECT
+	 * 12: H8SCI#
+	 * 14: CPUSB#
+	 * 15: CPPE#
+	 * 25: MDC_KILL#
+	 * 27: EXC_PWR_CTRL
+	 * 28: EXC_AUX_CTRL
+	 * 35: CLKREQ_SATA#
+	 * 36: PLANARID0
+	 * 37: PLANARID1
+	 * 38: PLANARID2
+	 * 39: PLANARID3
+	 */
 	outl(0x1f48f7c2, DEFAULT_GPIOBASE + 0x00);	/* GPIO_USE_SEL */
 	outl(0xe0e0ffc3, DEFAULT_GPIOBASE + 0x04);	/* GP_IO_SEL */
 	outl(0xfbfefb7d, DEFAULT_GPIOBASE + 0x0c);	/* GP_LVL */
@@ -101,7 +101,7 @@ static void early_superio_config(void)
 
 	pnp_write_config(dev, 0x29, 0xa0);
 
-	while(!(pnp_read_config(dev, 0x29) & 0x10) && timeout--)
+	while (!(pnp_read_config(dev, 0x29) & 0x10) && timeout--)
 		udelay(1000);
 
 	/* Enable COM1 */
@@ -140,7 +140,7 @@ static void rcba_config(void)
 
 	/* Disable unused devices */
 	RCBA32(0x3418) = FD_PCIE6 | FD_PCIE5 | FD_INTLAN | FD_ACMOD | FD_ACAUD;
-	RCBA32(0x3418) |= (1 << 0); // Required.
+	RCBA32(0x3418) |= (1 << 0);	// Required.
 
 	/* Set up I/O Trap #0 for 0xfe00 (SMIC) */
 	RCBA32(0x1e84) = 0x00020001;
@@ -253,16 +253,18 @@ void main(unsigned long bist)
 		early_superio_config();
 	}
 
-	/* Setup the console */
+	/* Set up the console */
 	console_init();
 
 	/* Halt if there was a built in self test failure */
 	report_bist_failure(bist);
 
 	if (MCHBAR16(SSKPD) == 0xCAFE) {
-		printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n");
+		printk(BIOS_DEBUG,
+		       "Soft reset detected, rebooting properly.\n");
 		outb(0x6, 0xcf9);
-		while (1) asm("hlt");
+		while (1)
+			asm("hlt");
 	}
 
 	/* Perform some early chipset initialization required
@@ -323,7 +325,7 @@ void main(unsigned long bist)
 
 	{
 		/* This will not work if TSEG is in place! */
-		u32 tom = pci_read_config32(PCI_DEV(0,2,0), 0x5c);
+		u32 tom = pci_read_config32(PCI_DEV(0, 2, 0), 0x5c);
 
 		printk(BIOS_DEBUG, "TOM: 0x%08x\n", tom);
 		ram_check(0x00000000, 0x000a0000);
@@ -350,18 +352,20 @@ void main(unsigned long bist)
 		 * day.
 		 */
 		if (resume_backup_memory)
-			memcpy(resume_backup_memory, (void *)CONFIG_RAMBASE, HIGH_MEMORY_SAVE);
+			memcpy(resume_backup_memory, (void *)CONFIG_RAMBASE,
+			       HIGH_MEMORY_SAVE);
 
 		/* Magic for S3 resume */
-		pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, SKPAD_ACPI_S3_MAGIC);
+		pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD,
+				   SKPAD_ACPI_S3_MAGIC);
 	}
 #endif
 
 #if CONFIG_COLLECT_TIMESTAMPS
 	timestamp_init(base_time);
-	timestamp_add(TS_START_ROMSTAGE, start_romstage_time );
-	timestamp_add(TS_BEFORE_INITRAM, before_dram_time );
-	timestamp_add(TS_AFTER_INITRAM, after_dram_time );
+	timestamp_add(TS_START_ROMSTAGE, start_romstage_time);
+	timestamp_add(TS_BEFORE_INITRAM, before_dram_time);
+	timestamp_add(TS_AFTER_INITRAM, after_dram_time);
 	timestamp_add_now(TS_END_ROMSTAGE);
 #endif