[coreboot-gerrit] New patch to review for coreboot: 992eac2 ibexpeak / bd82x6x: Make SATA mode user-visible option.
Vladimir Serbinenko (phcoder@gmail.com)
gerrit at coreboot.org
Sat Jan 11 07:50:12 CET 2014
Vladimir Serbinenko (phcoder at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4658
-gerrit
commit 992eac2c5d167754e78b9999eae98c553998e2f0
Author: Vladimir Serbinenko <phcoder at gmail.com>
Date: Sat Jan 11 07:46:50 2014 +0100
ibexpeak / bd82x6x: Make SATA mode user-visible option.
Ability to choose compatibility mode is interesting for testing payloads and
OS for compatibility with older systems.
As per comments
"ide_legacy_combined # TODO: Does nothing since generations, remove from sb code?"
The "combined" mode was removed. It wasn't used by any mobo and the code for
it is almost identical to IDE one other than few bits relating to interrupt
handling and ISA mode.
Change-Id: I407a8fac753b513812a86bef5abcf39c6d81472e
Signed-off-by: Vladimir Serbinenko <phcoder at gmail.com>
---
src/mainboard/google/butterfly/cmos.layout | 3 ++
src/mainboard/google/link/cmos.layout | 3 ++
src/mainboard/google/link/devicetree.cb | 2 -
src/mainboard/google/parrot/cmos.layout | 3 ++
src/mainboard/google/parrot/devicetree.cb | 2 -
src/mainboard/google/stout/cmos.layout | 3 ++
src/mainboard/google/stout/devicetree.cb | 2 -
src/mainboard/intel/cougar_canyon2/cmos.layout | 3 ++
src/mainboard/intel/cougar_canyon2/devicetree.cb | 2 -
src/mainboard/intel/emeraldlake2/cmos.layout | 3 ++
src/mainboard/intel/emeraldlake2/devicetree.cb | 2 -
src/mainboard/kontron/ktqm77/cmos.layout | 5 ++-
src/mainboard/kontron/ktqm77/devicetree.cb | 2 -
src/mainboard/lenovo/x201/cmos.default | 1 +
src/mainboard/lenovo/x201/cmos.layout | 5 ++-
src/mainboard/lenovo/x201/devicetree.cb | 1 -
src/mainboard/samsung/lumpy/cmos.layout | 3 ++
src/mainboard/samsung/lumpy/devicetree.cb | 2 -
src/mainboard/samsung/stumpy/cmos.layout | 3 ++
src/mainboard/samsung/stumpy/devicetree.cb | 2 -
src/southbridge/intel/bd82x6x/chip.h | 2 -
src/southbridge/intel/bd82x6x/sata.c | 51 ++++++------------------
src/southbridge/intel/ibexpeak/sata.c | 51 ++++++------------------
23 files changed, 59 insertions(+), 97 deletions(-)
diff --git a/src/mainboard/google/butterfly/cmos.layout b/src/mainboard/google/butterfly/cmos.layout
index 05de624..a40e66e 100644
--- a/src/mainboard/google/butterfly/cmos.layout
+++ b/src/mainboard/google/butterfly/cmos.layout
@@ -85,6 +85,7 @@ entries
# coreboot config options: southbridge
408 1 e 1 nmi
409 2 e 7 power_on_after_fail
+410 1 e 8 sata_mode
#411 5 r 0 unused
# coreboot config options: bootloader
@@ -132,6 +133,8 @@ enumerations
7 0 Disable
7 1 Enable
7 2 Keep
+8 0 AHCI
+8 1 Compatible
# -----------------------------------------------------------------
checksums
diff --git a/src/mainboard/google/link/cmos.layout b/src/mainboard/google/link/cmos.layout
index afdd3c6..17d205c 100644
--- a/src/mainboard/google/link/cmos.layout
+++ b/src/mainboard/google/link/cmos.layout
@@ -85,6 +85,7 @@ entries
# coreboot config options: southbridge
408 1 e 1 nmi
409 2 e 7 power_on_after_fail
+410 1 e 8 sata_mode
#411 5 r 0 unused
# coreboot config options: bootloader
@@ -131,6 +132,8 @@ enumerations
7 0 Disable
7 1 Enable
7 2 Keep
+8 0 AHCI
+8 1 Compatible
# -----------------------------------------------------------------
checksums
diff --git a/src/mainboard/google/link/devicetree.cb b/src/mainboard/google/link/devicetree.cb
index 15f420d..8f0ed3c 100644
--- a/src/mainboard/google/link/devicetree.cb
+++ b/src/mainboard/google/link/devicetree.cb
@@ -59,8 +59,6 @@ chip northbridge/intel/sandybridge
register "gpi7_routing" = "2"
register "gpi8_routing" = "1"
- register "ide_legacy_combined" = "0x0"
- register "sata_ahci" = "0x1"
register "sata_port_map" = "0x1"
register "sata_port0_gen3_tx" = "0x00880a7f"
diff --git a/src/mainboard/google/parrot/cmos.layout b/src/mainboard/google/parrot/cmos.layout
index afdd3c6..17d205c 100644
--- a/src/mainboard/google/parrot/cmos.layout
+++ b/src/mainboard/google/parrot/cmos.layout
@@ -85,6 +85,7 @@ entries
# coreboot config options: southbridge
408 1 e 1 nmi
409 2 e 7 power_on_after_fail
+410 1 e 8 sata_mode
#411 5 r 0 unused
# coreboot config options: bootloader
@@ -131,6 +132,8 @@ enumerations
7 0 Disable
7 1 Enable
7 2 Keep
+8 0 AHCI
+8 1 Compatible
# -----------------------------------------------------------------
checksums
diff --git a/src/mainboard/google/parrot/devicetree.cb b/src/mainboard/google/parrot/devicetree.cb
index cd65fbf..59586cc 100644
--- a/src/mainboard/google/parrot/devicetree.cb
+++ b/src/mainboard/google/parrot/devicetree.cb
@@ -61,8 +61,6 @@ chip northbridge/intel/sandybridge
register "gpi8_routing" = "1"
register "gpi15_routing" = "1" #lid switch gpe
- register "ide_legacy_combined" = "0x0"
- register "sata_ahci" = "0x1"
register "sata_port_map" = "0x1"
# EC range is 0xFD60 (EC_IO) and 0x68/0x6C
diff --git a/src/mainboard/google/stout/cmos.layout b/src/mainboard/google/stout/cmos.layout
index afdd3c6..17d205c 100644
--- a/src/mainboard/google/stout/cmos.layout
+++ b/src/mainboard/google/stout/cmos.layout
@@ -85,6 +85,7 @@ entries
# coreboot config options: southbridge
408 1 e 1 nmi
409 2 e 7 power_on_after_fail
+410 1 e 8 sata_mode
#411 5 r 0 unused
# coreboot config options: bootloader
@@ -131,6 +132,8 @@ enumerations
7 0 Disable
7 1 Enable
7 2 Keep
+8 0 AHCI
+8 1 Compatible
# -----------------------------------------------------------------
checksums
diff --git a/src/mainboard/google/stout/devicetree.cb b/src/mainboard/google/stout/devicetree.cb
index 6e02020..653d3fe 100644
--- a/src/mainboard/google/stout/devicetree.cb
+++ b/src/mainboard/google/stout/devicetree.cb
@@ -57,8 +57,6 @@ chip northbridge/intel/sandybridge
register "gpi1_routing" = "1"
register "gpi6_routing" = "2"
- register "ide_legacy_combined" = "0x0"
- register "sata_ahci" = "0x1"
register "sata_port_map" = "0x3"
# Set max SATA speed to 3.0 Gb/s
register "sata_interface_speed_support" = "0x2"
diff --git a/src/mainboard/intel/cougar_canyon2/cmos.layout b/src/mainboard/intel/cougar_canyon2/cmos.layout
index afdd3c6..17d205c 100644
--- a/src/mainboard/intel/cougar_canyon2/cmos.layout
+++ b/src/mainboard/intel/cougar_canyon2/cmos.layout
@@ -85,6 +85,7 @@ entries
# coreboot config options: southbridge
408 1 e 1 nmi
409 2 e 7 power_on_after_fail
+410 1 e 8 sata_mode
#411 5 r 0 unused
# coreboot config options: bootloader
@@ -131,6 +132,8 @@ enumerations
7 0 Disable
7 1 Enable
7 2 Keep
+8 0 AHCI
+8 1 Compatible
# -----------------------------------------------------------------
checksums
diff --git a/src/mainboard/intel/cougar_canyon2/devicetree.cb b/src/mainboard/intel/cougar_canyon2/devicetree.cb
index e66574e..c499a56 100644
--- a/src/mainboard/intel/cougar_canyon2/devicetree.cb
+++ b/src/mainboard/intel/cougar_canyon2/devicetree.cb
@@ -41,8 +41,6 @@ chip northbridge/intel/fsp_sandybridge
register "pirqg_routing" = "0x80"
register "pirqh_routing" = "0x80"
- register "ide_legacy_combined" = "0x0"
- register "sata_ahci" = "0x1"
register "sata_port_map" = "0x3f"
device pci 14.0 on end # XHCI
diff --git a/src/mainboard/intel/emeraldlake2/cmos.layout b/src/mainboard/intel/emeraldlake2/cmos.layout
index afdd3c6..17d205c 100644
--- a/src/mainboard/intel/emeraldlake2/cmos.layout
+++ b/src/mainboard/intel/emeraldlake2/cmos.layout
@@ -85,6 +85,7 @@ entries
# coreboot config options: southbridge
408 1 e 1 nmi
409 2 e 7 power_on_after_fail
+410 1 e 8 sata_mode
#411 5 r 0 unused
# coreboot config options: bootloader
@@ -131,6 +132,8 @@ enumerations
7 0 Disable
7 1 Enable
7 2 Keep
+8 0 AHCI
+8 1 Compatible
# -----------------------------------------------------------------
checksums
diff --git a/src/mainboard/intel/emeraldlake2/devicetree.cb b/src/mainboard/intel/emeraldlake2/devicetree.cb
index 0bb42d6..0d81502 100644
--- a/src/mainboard/intel/emeraldlake2/devicetree.cb
+++ b/src/mainboard/intel/emeraldlake2/devicetree.cb
@@ -50,8 +50,6 @@ chip northbridge/intel/sandybridge
register "alt_gp_smi_en" = "0x0002"
register "gpe0_en" = "0x4000"
- register "ide_legacy_combined" = "0x0"
- register "sata_ahci" = "0x1"
register "sata_port_map" = "0x3f"
# SuperIO range is 0x700-0x73f
diff --git a/src/mainboard/kontron/ktqm77/cmos.layout b/src/mainboard/kontron/ktqm77/cmos.layout
index 47cd60f..5c17a59 100644
--- a/src/mainboard/kontron/ktqm77/cmos.layout
+++ b/src/mainboard/kontron/ktqm77/cmos.layout
@@ -85,7 +85,8 @@ entries
# coreboot config options: southbridge
408 1 e 1 nmi
409 2 e 7 power_on_after_fail
-#411 5 r 0 unused
+410 1 e 11 sata_mode
+#412 4 r 0 unused
# coreboot config options: additional mainboard options
416 4 e 10 systemp_type
@@ -162,6 +163,8 @@ enumerations
10 2 LM75 at 90
10 3 GPIO16
10 4 LM75 at 9e
+11 0 AHCI
+11 1 Compatible
# -----------------------------------------------------------------
checksums
diff --git a/src/mainboard/kontron/ktqm77/devicetree.cb b/src/mainboard/kontron/ktqm77/devicetree.cb
index 65c03c4..f6390ac 100644
--- a/src/mainboard/kontron/ktqm77/devicetree.cb
+++ b/src/mainboard/kontron/ktqm77/devicetree.cb
@@ -36,8 +36,6 @@ chip northbridge/intel/sandybridge
register "pirqg_routing" = "0x8b"
register "pirqh_routing" = "0x8b"
- register "ide_legacy_combined" = "0x0" # TODO: Does nothing since generations, remove from sb code?
- register "sata_ahci" = "0x1"
# Enable all SATA ports 0-5
register "sata_port_map" = "0x3f"
# Set max SATA speed to 6.0 Gb/s (should be the default, anyway)
diff --git a/src/mainboard/lenovo/x201/cmos.default b/src/mainboard/lenovo/x201/cmos.default
index 4577e70..858f203 100644
--- a/src/mainboard/lenovo/x201/cmos.default
+++ b/src/mainboard/lenovo/x201/cmos.default
@@ -9,3 +9,4 @@ first_battery=Primary
bluetooth=Enable
wwan=Enable
touchpad=Enable
+sata_mode=AHCI
diff --git a/src/mainboard/lenovo/x201/cmos.layout b/src/mainboard/lenovo/x201/cmos.layout
index 3959178..9e9942e 100644
--- a/src/mainboard/lenovo/x201/cmos.layout
+++ b/src/mainboard/lenovo/x201/cmos.layout
@@ -90,7 +90,8 @@ entries
412 1 e 1 bluetooth
413 1 e 1 wwan
414 1 e 1 touchpad
-#415 569 r 0 unused
+417 1 e 9 sata_mode
+#418 566 r 0 unused
# coreboot config options: check sums
984 16 h 0 check_sum
@@ -129,6 +130,8 @@ enumerations
7 2 Keep
8 0 Secondary
8 1 Primary
+9 0 AHCI
+9 1 Compatible
# -----------------------------------------------------------------
checksums
diff --git a/src/mainboard/lenovo/x201/devicetree.cb b/src/mainboard/lenovo/x201/devicetree.cb
index f800f9a..5549327 100644
--- a/src/mainboard/lenovo/x201/devicetree.cb
+++ b/src/mainboard/lenovo/x201/devicetree.cb
@@ -107,7 +107,6 @@ chip northbridge/intel/nehalem
register "gpi1_routing" = "2"
register "gpi13_routing" = "2"
- register "sata_ahci" = "0x1"
register "sata_port_map" = "0x33"
register "gpe0_en" = "0x20022046"
diff --git a/src/mainboard/samsung/lumpy/cmos.layout b/src/mainboard/samsung/lumpy/cmos.layout
index 9552021..a14a8de 100644
--- a/src/mainboard/samsung/lumpy/cmos.layout
+++ b/src/mainboard/samsung/lumpy/cmos.layout
@@ -85,6 +85,7 @@ entries
# coreboot config options: southbridge
408 1 e 1 nmi
#409 2 e 7 power_on_after_fail
+410 1 e 8 sata_mode
#411 5 r 0 unused
# coreboot config options: bootloader
@@ -131,6 +132,8 @@ enumerations
7 0 Disable
7 1 Enable
7 2 Keep
+8 0 AHCI
+8 1 Compatible
# -----------------------------------------------------------------
checksums
diff --git a/src/mainboard/samsung/lumpy/devicetree.cb b/src/mainboard/samsung/lumpy/devicetree.cb
index cdd7a5c..69729d7 100644
--- a/src/mainboard/samsung/lumpy/devicetree.cb
+++ b/src/mainboard/samsung/lumpy/devicetree.cb
@@ -59,8 +59,6 @@ chip northbridge/intel/sandybridge
register "gpi1_routing" = "1"
register "gpi7_routing" = "2"
- register "ide_legacy_combined" = "0x0"
- register "sata_ahci" = "0x1"
register "sata_port_map" = "0x1"
# EC range is 0xa00-0xa3f
diff --git a/src/mainboard/samsung/stumpy/cmos.layout b/src/mainboard/samsung/stumpy/cmos.layout
index 6d2ac45..e506295 100644
--- a/src/mainboard/samsung/stumpy/cmos.layout
+++ b/src/mainboard/samsung/stumpy/cmos.layout
@@ -84,6 +84,7 @@ entries
# coreboot config options: southbridge
408 1 e 1 nmi
409 2 e 7 power_on_after_fail
+410 1 e 8 sata_mode
#411 5 r 0 unused
# coreboot config options: bootloader
@@ -131,6 +132,8 @@ enumerations
7 0 Disable
7 1 Enable
7 2 Keep
+8 0 AHCI
+8 1 Compatible
# -----------------------------------------------------------------
checksums
diff --git a/src/mainboard/samsung/stumpy/devicetree.cb b/src/mainboard/samsung/stumpy/devicetree.cb
index ee01e8a..ab03c79 100644
--- a/src/mainboard/samsung/stumpy/devicetree.cb
+++ b/src/mainboard/samsung/stumpy/devicetree.cb
@@ -49,8 +49,6 @@ chip northbridge/intel/sandybridge
register "gpi1_routing" = "0"
register "gpi14_routing" = "2"
- register "ide_legacy_combined" = "0x0"
- register "sata_ahci" = "0x1"
register "sata_port_map" = "0x3"
# SuperIO range is 0x700-0x73f
diff --git a/src/southbridge/intel/bd82x6x/chip.h b/src/southbridge/intel/bd82x6x/chip.h
index 828466c..0f2f0e9 100644
--- a/src/southbridge/intel/bd82x6x/chip.h
+++ b/src/southbridge/intel/bd82x6x/chip.h
@@ -64,8 +64,6 @@ struct southbridge_intel_bd82x6x_config {
uint16_t alt_gp_smi_en;
/* IDE configuration */
- uint32_t ide_legacy_combined;
- uint32_t sata_ahci;
uint8_t sata_port_map;
uint32_t sata_port0_gen3_tx;
uint32_t sata_port1_gen3_tx;
diff --git a/src/southbridge/intel/bd82x6x/sata.c b/src/southbridge/intel/bd82x6x/sata.c
index 594b09d..5d5fdbd 100644
--- a/src/southbridge/intel/bd82x6x/sata.c
+++ b/src/southbridge/intel/bd82x6x/sata.c
@@ -24,6 +24,7 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include "pch.h"
+#include <pc80/mc146818rtc.h>
typedef struct southbridge_intel_bd82x6x_config config_t;
@@ -45,6 +46,7 @@ static void sata_init(struct device *dev)
u16 reg16;
/* Get the chip configuration */
config_t *config = dev->chip_info;
+ u8 sata_mode;
printk(BIOS_DEBUG, "SATA: Initializing...\n");
@@ -53,48 +55,16 @@ static void sata_init(struct device *dev)
return;
}
+ if (get_option(&sata_mode, "sata_mode") != CB_SUCCESS)
+ sata_mode = 0;
+
/* SATA configuration */
/* Enable BARs */
pci_write_config16(dev, PCI_COMMAND, 0x0007);
- if (config->ide_legacy_combined) {
- printk(BIOS_DEBUG, "SATA: Controller in combined mode.\n");
-
- /* No AHCI: clear AHCI base */
- pci_write_config32(dev, 0x24, 0x00000000);
- /* And without AHCI BAR no memory decoding */
- reg16 = pci_read_config16(dev, PCI_COMMAND);
- reg16 &= ~PCI_COMMAND_MEMORY;
- pci_write_config16(dev, PCI_COMMAND, reg16);
-
- pci_write_config8(dev, 0x09, 0x80);
-
- /* Set timings */
- pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE |
- IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS);
- pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE |
- IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS |
- IDE_PPE0 | IDE_IE0 | IDE_TIME0);
-
- /* Sync DMA */
- pci_write_config16(dev, IDE_SDMA_CNT, IDE_SSDE0);
- pci_write_config16(dev, IDE_SDMA_TIM, 0x0200);
-
- /* Set IDE I/O Configuration */
- reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0;
- pci_write_config32(dev, IDE_CONFIG, reg32);
-
- /* Port enable */
- reg16 = pci_read_config16(dev, 0x92);
- reg16 &= ~0x3f;
- reg16 |= config->sata_port_map;
- pci_write_config16(dev, 0x92, reg16);
-
- /* SATA Initialization register */
- pci_write_config32(dev, 0x94,
- ((config->sata_port_map ^ 0x3f) << 24) | 0x183);
- } else if(config->sata_ahci) {
+ /* AHCI */
+ if (sata_mode == 0) {
u32 abar;
printk(BIOS_DEBUG, "SATA: Controller in AHCI mode.\n");
@@ -156,6 +126,7 @@ static void sata_init(struct device *dev)
reg32 &= ~0x00000005;
write32(abar + 0xa0, reg32);
} else {
+ /* IDE */
printk(BIOS_DEBUG, "SATA: Controller in plain mode.\n");
/* No AHCI: clear AHCI base */
@@ -244,15 +215,19 @@ static void sata_enable(device_t dev)
/* Get the chip configuration */
config_t *config = dev->chip_info;
u16 map = 0;
+ u8 sata_mode;
if (!config)
return;
+ if (get_option(&sata_mode, "sata_mode") != CB_SUCCESS)
+ sata_mode = 0;
+
/*
* Set SATA controller mode early so the resource allocator can
* properly assign IO/Memory resources for the controller.
*/
- if (config->sata_ahci)
+ if (sata_mode == 0)
map = 0x0060;
map |= (config->sata_port_map ^ 0x3f) << 8;
diff --git a/src/southbridge/intel/ibexpeak/sata.c b/src/southbridge/intel/ibexpeak/sata.c
index d30fae2..bf884aa 100644
--- a/src/southbridge/intel/ibexpeak/sata.c
+++ b/src/southbridge/intel/ibexpeak/sata.c
@@ -25,6 +25,7 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include "pch.h"
+#include <pc80/mc146818rtc.h>
typedef struct southbridge_intel_ibexpeak_config config_t;
@@ -46,6 +47,7 @@ static void sata_init(struct device *dev)
u16 reg16;
/* Get the chip configuration */
config_t *config = dev->chip_info;
+ u8 sata_mode;
printk(BIOS_DEBUG, "SATA: Initializing...\n");
@@ -54,48 +56,16 @@ static void sata_init(struct device *dev)
return;
}
+ if (get_option(&sata_mode, "sata_mode") != CB_SUCCESS)
+ sata_mode = 0;
+
/* SATA configuration */
/* Enable BARs */
pci_write_config16(dev, PCI_COMMAND, 0x0007);
- if (config->ide_legacy_combined) {
- printk(BIOS_DEBUG, "SATA: Controller in combined mode.\n");
-
- /* No AHCI: clear AHCI base */
- pci_write_config32(dev, 0x24, 0x00000000);
- /* And without AHCI BAR no memory decoding */
- reg16 = pci_read_config16(dev, PCI_COMMAND);
- reg16 &= ~PCI_COMMAND_MEMORY;
- pci_write_config16(dev, PCI_COMMAND, reg16);
-
- pci_write_config8(dev, 0x09, 0x80);
-
- /* Set timings */
- pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE |
- IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS);
- pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE |
- IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS);
-
- /* Sync DMA */
- pci_write_config16(dev, IDE_SDMA_CNT, 0);
- pci_write_config16(dev, IDE_SDMA_TIM, 0);
-
- /* Set IDE I/O Configuration */
- reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0;
- pci_write_config32(dev, IDE_CONFIG, reg32);
-
- /* Port enable */
- reg16 = pci_read_config16(dev, 0x92);
- reg16 &= ~0x3f;
- reg16 |= config->sata_port_map;
- pci_write_config16(dev, 0x92, reg16);
-
- /* SATA Initialization register */
- pci_write_config32(dev, 0x94,
- ((config->
- sata_port_map ^ 0x3f) << 24) | 0x183);
- } else if (config->sata_ahci) {
+ if (sata_mode == 0) {
+ /* AHCI */
u32 abar;
printk(BIOS_DEBUG, "SATA: Controller in AHCI mode.\n");
@@ -158,6 +128,7 @@ static void sata_init(struct device *dev)
reg32 &= ~0x00000005;
write32(abar + 0xa0, reg32);
} else {
+ /* IDE */
printk(BIOS_DEBUG, "SATA: Controller in plain mode.\n");
/* No AHCI: clear AHCI base */
@@ -245,15 +216,19 @@ static void sata_enable(device_t dev)
/* Get the chip configuration */
config_t *config = dev->chip_info;
u16 map = 0;
+ u8 sata_mode;
if (!config)
return;
+ if (get_option(&sata_mode, "sata_mode") != CB_SUCCESS)
+ sata_mode = 0;
+
/*
* Set SATA controller mode early so the resource allocator can
* properly assign IO/Memory resources for the controller.
*/
- if (config->sata_ahci)
+ if (sata_mode == 0)
map = 0x0060;
map |= (config->sata_port_map ^ 0x3f) << 8;
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