[coreboot-gerrit] New patch to review for coreboot: 6d285f7 nehalem/sandy/ivy/haswell: Enable WRPROT cache for all of flash

[Kyösti Mälkki (kyosti.malkki@gmail.com)]

Kyösti Mälkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4626

-gerrit

commit 6d285f72f129ced1e160930f3a40f869f3f0888b
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date:   Mon Jan 6 11:08:01 2014 +0200

    nehalem/sandy/ivy/haswell: Enable WRPROT cache for all of flash
    
    CBFS could start from below 4MB, and should be cacheable for the
    purpose of early microcode update and CBFS searh for romstage file.
    
    Change-Id: Ia2a1c6e5fdcc3201fafc8cf5c841cebbbf0b30c9
    Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
---
 src/cpu/intel/haswell/bootblock.c     | 3 +--
 src/cpu/intel/model_2065x/bootblock.c | 2 +-
 src/cpu/intel/model_206ax/bootblock.c | 2 +-
 3 files changed, 3 insertions(+), 4 deletions(-)

diff --git a/src/cpu/intel/haswell/bootblock.c b/src/cpu/intel/haswell/bootblock.c
index e502cfa..4857f23 100644
--- a/src/cpu/intel/haswell/bootblock.c
+++ b/src/cpu/intel/haswell/bootblock.c
@@ -54,8 +54,7 @@ static void enable_rom_caching(void)
 	msr_t msr;
 
 	disable_cache();
-	/* Why only top 4MiB ? */
-	set_var_mtrr(1, 0xffc00000, 4*1024*1024, MTRR_TYPE_WRPROT);
+	set_var_mtrr(1, CACHE_ROM_BASE, CACHE_ROM_SIZE, MTRR_TYPE_WRPROT);
 	enable_cache();
 
 	/* Enable Variable MTRRs */
diff --git a/src/cpu/intel/model_2065x/bootblock.c b/src/cpu/intel/model_2065x/bootblock.c
index 3fd3d14..fa8e137 100644
--- a/src/cpu/intel/model_2065x/bootblock.c
+++ b/src/cpu/intel/model_2065x/bootblock.c
@@ -53,7 +53,7 @@ static void enable_rom_caching(void)
 	msr_t msr;
 
 	disable_cache();
-	set_var_mtrr(1, 0xffc00000, 4*1024*1024, MTRR_TYPE_WRPROT);
+	set_var_mtrr(1, CACHE_ROM_BASE, CACHE_ROM_SIZE, MTRR_TYPE_WRPROT);
 	enable_cache();
 
 	/* Enable Variable MTRRs */
diff --git a/src/cpu/intel/model_206ax/bootblock.c b/src/cpu/intel/model_206ax/bootblock.c
index d3579f7..49c4012 100644
--- a/src/cpu/intel/model_206ax/bootblock.c
+++ b/src/cpu/intel/model_206ax/bootblock.c
@@ -54,7 +54,7 @@ static void enable_rom_caching(void)
 	msr_t msr;
 
 	disable_cache();
-	set_var_mtrr(1, 0xffc00000, 4*1024*1024, MTRR_TYPE_WRPROT);
+	set_var_mtrr(1, CACHE_ROM_BASE, CACHE_ROM_SIZE, MTRR_TYPE_WRPROT);
 	enable_cache();
 
 	/* Enable Variable MTRRs */