[coreboot-gerrit] Patch set updated for coreboot: 0f9d696 sandy/ivy/nehalem: Make DRAM gate GPIO configurable

[Vladimir Serbinenko (phcoder@gmail.com)]

Vladimir Serbinenko (phcoder at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4622

-gerrit

commit 0f9d696cbe6643a2d270833b31c03e8f2a963482
Author: Vladimir Serbinenko <phcoder at gmail.com>
Date:   Sun Jan 5 11:37:32 2014 +0100

    sandy/ivy/nehalem: Make DRAM gate GPIO configurable
    
    DRAM gate GPIO is different on different mobos move it to hidden config
    with 60 (current value) as default.
    
    Set it to 10 for Lenovo X201.
    
    Change-Id: I4f3b6876d7c33d4966315091b63a76a9a0064c16
    Signed-off-by: Vladimir Serbinenko <phcoder at gmail.com>
---
 src/mainboard/lenovo/x201/Kconfig           |  4 ++++
 src/southbridge/intel/bd82x6x/Kconfig       |  4 ++++
 src/southbridge/intel/bd82x6x/smihandler.c  | 32 +++++++++++++++++++----------
 src/southbridge/intel/ibexpeak/Kconfig      |  4 ++++
 src/southbridge/intel/ibexpeak/smihandler.c | 32 +++++++++++++++++++----------
 5 files changed, 54 insertions(+), 22 deletions(-)

diff --git a/src/mainboard/lenovo/x201/Kconfig b/src/mainboard/lenovo/x201/Kconfig
index a2d66b3..dbc80c5 100644
--- a/src/mainboard/lenovo/x201/Kconfig
+++ b/src/mainboard/lenovo/x201/Kconfig
@@ -43,6 +43,10 @@ config IRQ_SLOT_COUNT
 	int
 	default 18
 
+config CONFIG_DRAM_GATE_GPIO
+	int
+	default 10
+
 config MAX_CPUS
 	int
 	default 4
diff --git a/src/southbridge/intel/bd82x6x/Kconfig b/src/southbridge/intel/bd82x6x/Kconfig
index c2720ef..6a96c5e 100644
--- a/src/southbridge/intel/bd82x6x/Kconfig
+++ b/src/southbridge/intel/bd82x6x/Kconfig
@@ -45,6 +45,10 @@ config EHCI_DEBUG_OFFSET
 	hex
 	default 0xa0
 
+config DRAM_GATE_GPIO
+	int
+	default 60
+
 config BOOTBLOCK_SOUTHBRIDGE_INIT
 	string
 	default "southbridge/intel/bd82x6x/bootblock.c"
diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c
index 99f6b51..dc8bf8b 100644
--- a/src/southbridge/intel/bd82x6x/smihandler.c
+++ b/src/southbridge/intel/bd82x6x/smihandler.c
@@ -305,24 +305,34 @@ static void southbridge_gate_memory_reset(void)
 	if (!gpiobase)
 		return;
 
+#if CONFIG_DRAM_GATE_GPIO >= 32
+#define SUFFIX(x) x ## 2
+#define OFFSET (CONFIG_DRAM_GATE_GPIO - 32)
+#else
+#define SUFFIX(x) x
+#define OFFSET (CONFIG_DRAM_GATE_GPIO)
+#endif
+
 	/* Make sure it is set as GPIO */
-	reg32 = inl(gpiobase + GPIO_USE_SEL2);
-	if (!(reg32 & (1 << 28))) {
-		reg32 |= (1 << 28);
-		outl(reg32, gpiobase + GPIO_USE_SEL2);
+	reg32 = inl(gpiobase + SUFFIX(GPIO_USE_SEL));
+	if (!(reg32 & (1 << OFFSET))) {
+		reg32 |= (1 << OFFSET);
+		outl(reg32, gpiobase + SUFFIX(GPIO_USE_SEL));
 	}
 
 	/* Make sure it is set as output */
-	reg32 = inl(gpiobase + GP_IO_SEL2);
-	if (reg32 & (1 << 28)) {
-		reg32 &= ~(1 << 28);
-		outl(reg32, gpiobase + GP_IO_SEL2);
+	reg32 = inl(gpiobase + SUFFIX(GP_IO_SEL));
+	if (reg32 & (1 << OFFSET)) {
+		reg32 &= ~(1 << OFFSET);
+		outl(reg32, gpiobase + SUFFIX(GP_IO_SEL));
 	}
 
 	/* Drive the output low */
-	reg32 = inl(gpiobase + GP_LVL2);
-	reg32 &= ~(1 << 28);
-	outl(reg32, gpiobase + GP_LVL2);
+	reg32 = inl(gpiobase + SUFFIX(GP_LVL));
+	reg32 &= ~(1 << OFFSET);
+	outl(reg32, gpiobase + SUFFIX(GP_LVL));
+#undef OFFSET
+#undef SUFFIX
 }
 
 static void xhci_sleep(u8 slp_typ)
diff --git a/src/southbridge/intel/ibexpeak/Kconfig b/src/southbridge/intel/ibexpeak/Kconfig
index 07e714b..7e1c4e0 100644
--- a/src/southbridge/intel/ibexpeak/Kconfig
+++ b/src/southbridge/intel/ibexpeak/Kconfig
@@ -43,6 +43,10 @@ config EHCI_DEBUG_OFFSET
 	hex
 	default 0xa0
 
+config DRAM_GATE_GPIO
+	int
+	default 60
+
 config BOOTBLOCK_SOUTHBRIDGE_INIT
 	string
 	default "southbridge/intel/bd82x6x/bootblock.c"
diff --git a/src/southbridge/intel/ibexpeak/smihandler.c b/src/southbridge/intel/ibexpeak/smihandler.c
index 5ee8ef9..088c5c2 100644
--- a/src/southbridge/intel/ibexpeak/smihandler.c
+++ b/src/southbridge/intel/ibexpeak/smihandler.c
@@ -305,24 +305,34 @@ static void southbridge_gate_memory_reset(void)
 	if (!gpiobase)
 		return;
 
+#if CONFIG_DRAM_GATE_GPIO >= 32
+#define SUFFIX(x) x ## 2
+#define OFFSET (CONFIG_DRAM_GATE_GPIO - 32)
+#else
+#define SUFFIX(x) x
+#define OFFSET (CONFIG_DRAM_GATE_GPIO)
+#endif
+
 	/* Make sure it is set as GPIO */
-	reg32 = inl(gpiobase + GPIO_USE_SEL2);
-	if (!(reg32 & (1 << 28))) {
-		reg32 |= (1 << 28);
-		outl(reg32, gpiobase + GPIO_USE_SEL2);
+	reg32 = inl(gpiobase + SUFFIX(GPIO_USE_SEL));
+	if (!(reg32 & (1 << OFFSET))) {
+		reg32 |= (1 << OFFSET);
+		outl(reg32, gpiobase + SUFFIX(GPIO_USE_SEL));
 	}
 
 	/* Make sure it is set as output */
-	reg32 = inl(gpiobase + GP_IO_SEL2);
-	if (reg32 & (1 << 28)) {
-		reg32 &= ~(1 << 28);
-		outl(reg32, gpiobase + GP_IO_SEL2);
+	reg32 = inl(gpiobase + SUFFIX(GP_IO_SEL));
+	if (reg32 & (1 << OFFSET)) {
+		reg32 &= ~(1 << OFFSET);
+		outl(reg32, gpiobase + SUFFIX(GP_IO_SEL));
 	}
 
 	/* Drive the output low */
-	reg32 = inl(gpiobase + GP_LVL2);
-	reg32 &= ~(1 << 28);
-	outl(reg32, gpiobase + GP_LVL2);
+	reg32 = inl(gpiobase + SUFFIX(GP_LVL));
+	reg32 &= ~(1 << OFFSET);
+	outl(reg32, gpiobase + SUFFIX(GP_LVL));
+#undef OFFSET
+#undef SUFFIX
 }
 
 static void xhci_sleep(u8 slp_typ)