[coreboot-gerrit] Patch set updated for coreboot: 145e1b8 baytrail: Add IOSF functions for USBPHY and USHPHY

Aaron Durbin (adurbin@google.com) gerrit at coreboot.org
Tue Feb 25 20:52:22 CET 2014


Aaron Durbin (adurbin at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4916

-gerrit

commit 145e1b87dd086691e564fc7c7df1ef19c28eefc1
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Thu Oct 31 08:20:48 2013 -0700

    baytrail: Add IOSF functions for USBPHY and USHPHY
    
    These are needed for USB2 and USB3 PHY init sequences.
    
    BUG=chrome-os-partner:23635
    BRANCH=rambi
    TEST=emerge-rambi chromeos-coreboot-rambi
    
    Change-Id: Id284d882034e15eceeaa910b8b73bc0d8d895199
    Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/175227
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 src/soc/intel/baytrail/baytrail/iosf.h |  7 ++++++
 src/soc/intel/baytrail/iosf.c          | 44 ++++++++++++++++++++++++++++++++++
 2 files changed, 51 insertions(+)

diff --git a/src/soc/intel/baytrail/baytrail/iosf.h b/src/soc/intel/baytrail/baytrail/iosf.h
index 7f0c7f5..b234552 100644
--- a/src/soc/intel/baytrail/baytrail/iosf.h
+++ b/src/soc/intel/baytrail/baytrail/iosf.h
@@ -64,6 +64,10 @@ uint32_t iosf_dunit_ch0_read(int reg);
 uint32_t iosf_dunit_ch1_read(int reg);
 uint32_t iosf_punit_read(int reg);
 void iosf_punit_write(int reg, uint32_t val);
+uint32_t iosf_usbphy_read(int reg);
+void iosf_usbphy_write(int reg, uint32_t val);
+uint32_t iosf_ushphy_read(int reg);
+void iosf_ushphy_write(int reg, uint32_t val);
 
 /* IOSF ports. */
 #define IOSF_PORT_AUNIT		0x00 /* IO Arbiter unit */
@@ -76,6 +80,7 @@ void iosf_punit_write(int reg, uint32_t val);
 #define IOSF_PORT_DUNIT_CH1	0x07 /* DUNIT Channel 1 */
 #define IOSF_PORT_SYSMEMIO	0x0c /* System Memory IO */
 #define IOSF_PORT_USBPHY	0x43 /* USB PHY */
+#define IOSF_PORT_USHPHY	0x61 /* USB XHCI PHY */
 #define IOSF_PORT_SATAPHY	0xa3 /* SATA PHY */
 #define IOSF_PORT_PCIEPHY	0xa3 /* PCIE PHY */
 
@@ -96,6 +101,8 @@ void iosf_punit_write(int reg, uint32_t val);
 #define IOSF_OP_WRITE_SYSMEMIO	(IOSF_OP_READ_SYSMEMIO | 1)
 #define IOSF_OP_READ_USBPHY	0x06
 #define IOSF_OP_WRITE_USBPHY	(IOSF_OP_READ_USBPHY | 1)
+#define IOSF_OP_READ_USHPHY	0x06
+#define IOSF_OP_WRITE_USHPHY	(IOSF_OP_READ_USHPHY | 1)
 #define IOSF_OP_READ_SATAPHY	0x00
 #define IOSF_OP_WRITE_SATAPHY	(IOSF_OP_READ_SATAPHY | 1)
 #define IOSF_OP_READ_PCIEPHY	0x00
diff --git a/src/soc/intel/baytrail/iosf.c b/src/soc/intel/baytrail/iosf.c
index b050eba..7d420cc 100644
--- a/src/soc/intel/baytrail/iosf.c
+++ b/src/soc/intel/baytrail/iosf.c
@@ -121,3 +121,47 @@ void iosf_punit_write(int reg, uint32_t val)
 	write_iosf_reg(MCRX_REG, IOSF_REG_UPPER(reg));
 	write_iosf_reg(MCR_REG, cr);
 }
+
+uint32_t iosf_usbphy_read(int reg)
+{
+	uint32_t cr = IOSF_OPCODE(IOSF_OP_READ_USBPHY) |
+	              IOSF_PORT(IOSF_PORT_USBPHY) | IOSF_REG(reg) |
+	              IOSF_BYTE_EN;
+
+	write_iosf_reg(MCRX_REG, IOSF_REG_UPPER(reg));
+	write_iosf_reg(MCR_REG, cr);
+	return read_iosf_reg(MDR_REG);
+}
+
+void iosf_usbphy_write(int reg, uint32_t val)
+{
+	uint32_t cr = IOSF_OPCODE(IOSF_OP_WRITE_USBPHY) |
+	              IOSF_PORT(IOSF_PORT_USBPHY) | IOSF_REG(reg) |
+	              IOSF_BYTE_EN;
+
+	write_iosf_reg(MDR_REG, val);
+	write_iosf_reg(MCRX_REG, IOSF_REG_UPPER(reg));
+	write_iosf_reg(MCR_REG, cr);
+}
+
+uint32_t iosf_ushphy_read(int reg)
+{
+	uint32_t cr = IOSF_OPCODE(IOSF_OP_READ_USHPHY) |
+	              IOSF_PORT(IOSF_PORT_USHPHY) | IOSF_REG(reg) |
+	              IOSF_BYTE_EN;
+
+	write_iosf_reg(MCRX_REG, IOSF_REG_UPPER(reg));
+	write_iosf_reg(MCR_REG, cr);
+	return read_iosf_reg(MDR_REG);
+}
+
+void iosf_ushphy_write(int reg, uint32_t val)
+{
+	uint32_t cr = IOSF_OPCODE(IOSF_OP_WRITE_USHPHY) |
+	              IOSF_PORT(IOSF_PORT_USHPHY) | IOSF_REG(reg) |
+	              IOSF_BYTE_EN;
+
+	write_iosf_reg(MDR_REG, val);
+	write_iosf_reg(MCRX_REG, IOSF_REG_UPPER(reg));
+	write_iosf_reg(MCR_REG, cr);
+}



More information about the coreboot-gerrit mailing list