[coreboot-gerrit] Patch set updated for coreboot: c7931d8 NOTFORMERGE: Fix for SeaBIOS
Vladimir Serbinenko (phcoder@gmail.com)
gerrit at coreboot.org
Sat Feb 22 10:01:34 CET 2014
Vladimir Serbinenko (phcoder at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5279
-gerrit
commit c7931d8b27f56bb40c7ff7617ee11247e330105d
Author: Vladimir Serbinenko <phcoder at gmail.com>
Date: Thu Feb 20 17:50:33 2014 +0100
NOTFORMERGE: Fix for SeaBIOS
Change-Id: Ib2ea3742b831178ee6dba8be73e8d7fa96952327
Signed-off-by: Vladimir Serbinenko <phcoder at gmail.com>
---
src/southbridge/intel/bd82x6x/usb_ehci.c | 1 +
src/southbridge/intel/ibexpeak/usb_ehci.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/src/southbridge/intel/bd82x6x/usb_ehci.c b/src/southbridge/intel/bd82x6x/usb_ehci.c
index 78f92d9..4162562 100644
--- a/src/southbridge/intel/bd82x6x/usb_ehci.c
+++ b/src/southbridge/intel/bd82x6x/usb_ehci.c
@@ -38,6 +38,7 @@ static void usb_ehci_init(struct device *dev)
printk(BIOS_DEBUG, "EHCI: Setting up controller.. ");
reg32 = pci_read_config32(dev, PCI_COMMAND);
reg32 |= PCI_COMMAND_MASTER;
+ reg32 |= PCI_COMMAND_MEMORY;
//reg32 |= PCI_COMMAND_SERR;
pci_write_config32(dev, PCI_COMMAND, reg32);
diff --git a/src/southbridge/intel/ibexpeak/usb_ehci.c b/src/southbridge/intel/ibexpeak/usb_ehci.c
index 7dc7b03..4d1183d 100644
--- a/src/southbridge/intel/ibexpeak/usb_ehci.c
+++ b/src/southbridge/intel/ibexpeak/usb_ehci.c
@@ -47,6 +47,7 @@ static void usb_ehci_init(struct device *dev)
reg32 = pci_read_config32(dev, PCI_COMMAND);
reg32 |= PCI_COMMAND_MASTER;
+ reg32 |= PCI_COMMAND_MEMORY;
//reg32 |= PCI_COMMAND_SERR;
pci_write_config32(dev, PCI_COMMAND, reg32);
More information about the coreboot-gerrit
mailing list