[coreboot-gerrit] Patch set updated for coreboot: fa7a741 OxPCIe uart: Split PCI bridge control
Kyösti Mälkki (kyosti.malkki@gmail.com)
gerrit at coreboot.org
Sun Feb 16 06:08:41 CET 2014
Kyösti Mälkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5237
-gerrit
commit fa7a74163f434c3a67f5880c3f08ff9f669fad6b
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date: Fri Feb 14 12:45:09 2014 +0200
OxPCIe uart: Split PCI bridge control
None of the bridge management here is specific to the PCI UART
device/function. Also the Kconfig variable defaults are not globally
valid but originate from lumpy and/or stumpy devices.
Change-Id: Id22631412379af1d6bf62c996357d36d7ec47ca3
Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
---
src/device/pci_early.c | 45 ++++++++++++++++++
src/drivers/Kconfig | 1 +
src/drivers/oxford/oxpcie/Kconfig | 64 ++-----------------------
src/drivers/oxford/oxpcie/oxpcie_early.c | 81 ++++++--------------------------
src/drivers/pci/Kconfig | 31 ++++++++++++
src/drivers/pci/pci_early.c | 58 +++++++++++++++++++++++
src/include/device/pci.h | 6 +++
src/southbridge/intel/bd82x6x/Kconfig | 20 ++++++++
8 files changed, 179 insertions(+), 127 deletions(-)
diff --git a/src/device/pci_early.c b/src/device/pci_early.c
index c15a4d0..d7c48de 100644
--- a/src/device/pci_early.c
+++ b/src/device/pci_early.c
@@ -1,6 +1,8 @@
/*
* This file is part of the coreboot project.
*
+ * Copyright (C) 2011 Google Inc
+ *
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
@@ -66,3 +68,46 @@ unsigned pci_find_capability(device_t dev, unsigned cap)
{
return pci_find_next_capability(dev, cap, 0);
}
+
+void pci_bridge_reset_secondary(device_t p2p_bridge)
+{
+ u16 reg16;
+ /* Disable all access through bridge. */
+ reg16 = pci_read_config16(p2p_bridge, PCI_COMMAND);
+ reg16 &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
+ pci_write_config16(p2p_bridge, PCI_COMMAND, reg16);
+
+ /* First we reset the secondary bus. */
+ reg16 = pci_read_config16(p2p_bridge, PCI_BRIDGE_CONTROL);
+ reg16 |= (1 << 6); /* SRESET */
+ pci_write_config16(p2p_bridge, PCI_BRIDGE_CONTROL, reg16);
+
+ /* Assume we don't have to wait here forever */
+
+ /* Read back and clear reset bit. */
+ reg16 = pci_read_config16(p2p_bridge, PCI_BRIDGE_CONTROL);
+ reg16 &= ~(1 << 6); /* SRESET */
+ pci_write_config16(p2p_bridge, PCI_BRIDGE_CONTROL, reg16);
+}
+
+void pci_bridge_set_secondary(device_t p2p_bridge, u8 secondary)
+{
+ /* Disable config transaction forwarding. */
+ pci_write_config8(p2p_bridge, PCI_SUBORDINATE_BUS, 0x00);
+ pci_write_config8(p2p_bridge, PCI_SECONDARY_BUS, 0x00);
+ /* Enable config transaction forwarding. */
+ pci_write_config8(p2p_bridge, PCI_SECONDARY_BUS, secondary);
+ pci_write_config8(p2p_bridge, PCI_SUBORDINATE_BUS, secondary);
+}
+
+void pci_bridge_enable_mmio(device_t p2p_bridge, u32 base)
+{
+ /* MMIO window behind the bridge. */
+ pci_write_config32(p2p_bridge, PCI_MEMORY_BASE,
+ ((base & 0xffff0000) | ((base >> 16) & 0xff00)));
+
+ /* Enable memory access through bridge */
+ reg16 = pci_read_config16(p2p_bridge, PCI_COMMAND);
+ reg16 |= PCI_COMMAND_MEMORY;
+ pci_write_config16(p2p_bridge, PCI_COMMAND, reg16);
+}
diff --git a/src/drivers/Kconfig b/src/drivers/Kconfig
index 01bed21..5d9a801 100644
--- a/src/drivers/Kconfig
+++ b/src/drivers/Kconfig
@@ -32,6 +32,7 @@ source src/drivers/parade/Kconfig
if PC80_SYSTEM
source src/drivers/pc80/Kconfig
endif
+source src/drivers/pci/Kconfig
source src/drivers/realtek/Kconfig
source src/drivers/sil/Kconfig
source src/drivers/spi/Kconfig
diff --git a/src/drivers/oxford/oxpcie/Kconfig b/src/drivers/oxford/oxpcie/Kconfig
index 899a153..bd5001c 100644
--- a/src/drivers/oxford/oxpcie/Kconfig
+++ b/src/drivers/oxford/oxpcie/Kconfig
@@ -1,68 +1,10 @@
config DRIVERS_OXFORD_OXPCIE
bool "Oxford OXPCIe952"
default n
+ depends on PCI
select HAVE_UART_MEMORY_MAPPED
+ select EARLY_PCI_BRIDGE
help
Support for Oxford OXPCIe952 serial port PCIe cards.
Currently only devices with the vendor ID 0x1415 and device ID
- 0xc158 will work.
- NOTE: Right now you have to set the base address of your OXPCIe952
- card to exactly the value that the device allocator would set them
- later on, or serial console functionality will stop as soon as the
- resource allocator assigns a new base address to the device.
-
-config OXFORD_OXPCIE_BRIDGE_BUS
- hex "OXPCIe's PCIe bridge bus number"
- default 0x0
- depends on DRIVERS_OXFORD_OXPCIE
- help
- While coreboot is executing code from ROM, the coreboot resource
- allocator has not been running yet. Hence PCI devices living behind
- a bridge are not yet visible to the system. In order to use an
- OXPCIe952 based PCIe card, coreboot has to set up the PCIe bridge
- that controls the OXPCIe952 controller first.
-
-config OXFORD_OXPCIE_BRIDGE_DEVICE
- hex "OXPCIe's PCIe bridge device number"
- default 0x1c
- depends on DRIVERS_OXFORD_OXPCIE
- help
- While coreboot is executing code from ROM, the coreboot resource
- allocator has not been running yet. Hence PCI devices living behind
- a bridge are not yet visible to the system. In order to use an
- OXPCIe952 based PCIe card, coreboot has to set up the PCIe bridge
- that controls the OXPCIe952 controller first.
-
-config OXFORD_OXPCIE_BRIDGE_FUNCTION
- hex "OXPCIe's PCIe bridge function number"
- default 0x2
- depends on DRIVERS_OXFORD_OXPCIE
- help
- While coreboot is executing code from ROM, the coreboot resource
- allocator has not been running yet. Hence PCI devices living behind
- a bridge are not yet visible to the system. In order to use an
- OXPCIe952 based PCIe card, coreboot has to set up the PCIe bridge
- that controls the OXPCIe952 controller first.
-
-config OXFORD_OXPCIE_BRIDGE_SUBORDINATE
- hex "OXPCIe's PCIe bridge subordinate bus"
- default 0x3
- depends on DRIVERS_OXFORD_OXPCIE
- help
- While coreboot is executing code from ROM, the coreboot resource
- allocator has not been running yet. Hence PCI devices living behind
- a bridge are not yet visible to the system. In order to use an
- OXPCIe952 based PCIe card, coreboot has to set up the PCIe bridge
- that controls the OXPCIe952 controller first.
-
-config OXFORD_OXPCIE_BASE_ADDRESS
- hex "Base address for rom stage console"
- default 0xe0400000
- depends on DRIVERS_OXFORD_OXPCIE
- help
- While coreboot is executing code from ROM, the coreboot resource
- allocator has not been running yet. Hence PCI devices living behind
- a bridge are not yet visible to the system. In order to use an
- OXPCIe952 based PCIe card, coreboot has to set up a temporary address
- for the OXPCIe952 controller.
-
+ 0xc158 or 0xc11b will work.
diff --git a/src/drivers/oxford/oxpcie/oxpcie_early.c b/src/drivers/oxford/oxpcie/oxpcie_early.c
index b2004c4..122f3a4 100644
--- a/src/drivers/oxford/oxpcie/oxpcie_early.c
+++ b/src/drivers/oxford/oxpcie/oxpcie_early.c
@@ -25,94 +25,43 @@
#include <device/pci_def.h>
static unsigned int oxpcie_present CAR_GLOBAL;
-static ROMSTAGE_CONST u32 uart0_base = CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x1000;
-static ROMSTAGE_CONST u32 uart1_base = CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x2000;
+static ROMSTAGE_CONST u32 uart0_base = CONFIG_EARLY_PCI_MMIO_BASE + 0x1000;
+static ROMSTAGE_CONST u32 uart1_base = CONFIG_EARLY_PCI_MMIO_BASE + 0x2000;
-#define PCIE_BRIDGE \
- PCI_DEV(CONFIG_OXFORD_OXPCIE_BRIDGE_BUS, \
- CONFIG_OXFORD_OXPCIE_BRIDGE_DEVICE, \
- CONFIG_OXFORD_OXPCIE_BRIDGE_FUNCTION)
-
-#define OXPCIE_DEVICE \
- PCI_DEV(CONFIG_OXFORD_OXPCIE_BRIDGE_SUBORDINATE, 0, 0)
-
-#define OXPCIE_DEVICE_3 \
- PCI_DEV(CONFIG_OXFORD_OXPCIE_BRIDGE_SUBORDINATE, 0, 3)
-
-static void oxpcie_init_bridge(void)
+static int oxpcie_probe(u8 bus, u8 dev, u32 mmio_base, u16 io_base)
{
- u16 reg16;
-
- /* First we reset the secondary bus */
- reg16 = pci_read_config16(PCIE_BRIDGE, PCI_BRIDGE_CONTROL);
- reg16 |= (1 << 6); /* SRESET */
- pci_write_config16(PCIE_BRIDGE, PCI_BRIDGE_CONTROL, reg16);
-
- /* Assume we don't have to wait here forever */
-
- /* Read back and clear reset bit. */
- reg16 = pci_read_config16(PCIE_BRIDGE, PCI_BRIDGE_CONTROL);
- reg16 &= ~(1 << 6); /* SRESET */
- pci_write_config16(PCIE_BRIDGE, PCI_BRIDGE_CONTROL, reg16);
-
- /* Set up subordinate bus number */
- pci_write_config8(PCIE_BRIDGE, PCI_SECONDARY_BUS, 0x00);
- pci_write_config8(PCIE_BRIDGE, PCI_SUBORDINATE_BUS, 0x00);
- pci_write_config8(PCIE_BRIDGE, PCI_SECONDARY_BUS,
- CONFIG_OXFORD_OXPCIE_BRIDGE_SUBORDINATE);
- pci_write_config8(PCIE_BRIDGE, PCI_SUBORDINATE_BUS,
- CONFIG_OXFORD_OXPCIE_BRIDGE_SUBORDINATE);
+ pci_devfn_t device = PCI_DEV(bus, dev, 0);
- /* Memory window for the OXPCIe952 card */
- // XXX is the calculation of base and limit correct?
- pci_write_config32(PCIE_BRIDGE, PCI_MEMORY_BASE,
- ((CONFIG_OXFORD_OXPCIE_BASE_ADDRESS & 0xffff0000) |
- ((CONFIG_OXFORD_OXPCIE_BASE_ADDRESS >> 16) & 0xff00)));
-
- /* Enable memory access through bridge */
- reg16 = pci_read_config16(PCIE_BRIDGE, PCI_COMMAND);
- reg16 |= PCI_COMMAND_MEMORY;
- pci_write_config16(PCIE_BRIDGE, PCI_COMMAND, reg16);
-
- u32 timeout = 20000; // Timeout in 10s of microseconds.
- u32 id = 0;
- for (;;) {
- id = pci_read_config32(OXPCIE_DEVICE, PCI_VENDOR_ID);
- if (!timeout-- || (id != 0 && id != 0xffffffff))
- break;
- udelay(10);
- }
-
- u32 device = OXPCIE_DEVICE; /* unknown default */
+ u32 id = pci_read_config32(device, PCI_VENDOR_ID);
switch (id) {
- case 0xc1181415: /* e.g. Startech PEX1S1PMINI */
+ case 0xc1181415: /* e.g. Startech PEX1S1PMINI function 0 */
/* On this device function 0 is the parallel port, and
* function 3 is the serial port. So let's go look for
* the UART.
*/
- id = pci_read_config32(OXPCIE_DEVICE_3, PCI_VENDOR_ID);
+ device = PCI_DEV(bus, dev, 3);
+ id = pci_read_config32(device, PCI_VENDOR_ID);
if (id != 0xc11b1415)
- return;
- device = OXPCIE_DEVICE_3;
+ return -1;
break;
+ case 0xc11b1415: /* e.g. Startech PEX1S1PMINI function 3 */
case 0xc1581415: /* e.g. Startech MPEX2S952 */
- device = OXPCIE_DEVICE;
break;
default:
/* No UART here. */
- return;
+ return -1;
}
/* Setup base address on device */
- pci_write_config32(device, PCI_BASE_ADDRESS_0,
- CONFIG_OXFORD_OXPCIE_BASE_ADDRESS);
+ pci_write_config32(device, PCI_BASE_ADDRESS_0, mmio_base);
/* Enable memory on device */
- reg16 = pci_read_config16(device, PCI_COMMAND);
+ u16 reg16 = pci_read_config16(device, PCI_COMMAND);
reg16 |= PCI_COMMAND_MEMORY;
pci_write_config16(device, PCI_COMMAND, reg16);
car_set_var(oxpcie_present, 1);
+ return 0;
}
static int oxpcie_uart_active(void)
@@ -149,6 +98,6 @@ uint32_t uartmem_getbaseaddr(void)
void oxford_init(void)
{
- oxpcie_init_bridge();
+ pci_bridge_early_init(&oxpcie_probe);
uart_init();
}
diff --git a/src/drivers/pci/Kconfig b/src/drivers/pci/Kconfig
new file mode 100644
index 0000000..bb6d2bf
--- /dev/null
+++ b/src/drivers/pci/Kconfig
@@ -0,0 +1,31 @@
+config EARLY_PCI_BRIDGE
+ bool "Early PCI bridge"
+ depends on PCI
+ default n
+ help
+ While coreboot is executing code from ROM, the coreboot resource
+ allocator has not been running yet. Hence PCI devices living behind
+ a bridge are not yet visible to the system.
+
+ This option enables static configuration for a single pre-defined
+ PCI bridge function on bus 0.
+
+if EARLY_PCI_BRIDGE
+
+config EARLY_PCI_BRIDGE_DEVICE
+ hex "bridge device"
+ default 0x0
+
+config EARLY_PCI_BRIDGE_FUNCTION
+ hex "bridge function"
+ default 0x0
+
+config EARLY_PCI_MMIO_BASE
+ hex "MMIO window base"
+ default 0x0
+
+config EARLY_PCI_BRIDGE_SECONDARY
+ hex "Early PCI bridge secondary bus"
+ default 0x0
+
+endif # EARLY_PCI_BRIDGE
diff --git a/src/drivers/pci/pci_early.c b/src/drivers/pci/pci_early.c
new file mode 100644
index 0000000..6e1a6f7
--- /dev/null
+++ b/src/drivers/pci/pci_early.c
@@ -0,0 +1,58 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Google Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <device/pci.h>
+#include <device/pci_def.h>
+
+
+{
+ /* No PCI-to-PCI bridges are enabled yet, so the one we try to
+ * configure must have its primary on bus 0.
+ */
+ pci_devfn_t p2p_bridge = PCI_DEV(0, CONFIG_EARLY_PCI_BRIDGE_DEVICE,
+ CONFIG_EARLY_PCI_BRIDGE_FUNCTION);
+
+ u8 bus = CONFIG_EARLY_PCI_BRIDGE_SECONDARY;
+
+ pci_bridge_reset_secondary(p2p_bridge);
+ pci_bridge_set_secondary(p2p_bridge, bus);
+
+ u3 timeout = 20000; // Timeout in 10s of microseconds.
+ u32 id = 0;
+ for (;;) {
+ id = pci_read_config32(OXPCIE_DEVICE, PCI_VENDOR_ID);
+ if (!timeout-- || (id != 0 && id != 0xffffffff))
+ break;
+ udelay(10);
+ }
+
+ ret = probe(bus, dev, mmio_base, io_base);
+
+ /* Enable both MMIO and IO window with static allocation
+ * if we found any suitable device behind bridge.
+ */
+ pci_bridge_enable_mmio(p2p_bridge, base, limit);
+
+ /* Resource allocator will reconfigure bridges and secondary bus
+ * number may change. Early device must not use config transactions
+ * from here on.
+ */
+ pci_bridge_set_secondary(p2p_bridge, 0);
+}
diff --git a/src/include/device/pci.h b/src/include/device/pci.h
index 29d988f..881c2ac 100644
--- a/src/include/device/pci.h
+++ b/src/include/device/pci.h
@@ -98,6 +98,12 @@ static inline const struct pci_operations *ops_pci(device_t dev)
return pops;
}
+#else
+
+void pci_bridge_reset_secondary(device_t p2p_bridge);
+void pci_bridge_enable_mmio(device_t p2p_bridge, u32 base);
+void pci_bridge_set_secondary(device_t p2p_bridge, u8 secondary);
+
#endif /* ! __SIMPLE_DEVICE__ */
unsigned pci_find_next_capability(device_t dev, unsigned cap, unsigned last);
diff --git a/src/southbridge/intel/bd82x6x/Kconfig b/src/southbridge/intel/bd82x6x/Kconfig
index 9cfa5d5..69c1fc9 100644
--- a/src/southbridge/intel/bd82x6x/Kconfig
+++ b/src/southbridge/intel/bd82x6x/Kconfig
@@ -41,6 +41,26 @@ config EHCI_BAR
hex
default 0xfef00000
+if EARLY_PCI_BRIDGE
+
+config EARLY_PCI_BRIDGE_DEVICE
+ hex
+ default 0x1c
+
+config EARLY_PCI_BRIDGE_FUNCTION
+ hex
+ default 0x2
+
+config EARLY_PCI_MMIO_BASE
+ hex
+ default 0xe0400000
+
+config EARLY_PCI_BRIDGE_SECONDARY
+ hex
+ default 0x3
+
+endif
+
config DRAM_RESET_GATE_GPIO
int
default 60
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