[coreboot-gerrit] Patch set updated for coreboot: ac88691 uart8250: Split register definitions

Kyösti Mälkki (kyosti.malkki@gmail.com) gerrit at coreboot.org
Sat Feb 15 21:53:34 CET 2014


Kyösti Mälkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5233

-gerrit

commit ac8869178dfab6ca6140319733b8de78d164b1a8
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date:   Fri Feb 14 06:59:51 2014 +0200

    uart8250: Split register definitions
    
    Change-Id: Ideb7f55f329e1ae037debc156d3cb4a5b95bde22
    Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
---
 src/cpu/allwinner/a10/uart.c   |   7 +--
 src/drivers/uart/uart8250reg.h | 108 +++++++++++++++++++++++++++++++++++++++++
 src/include/uart8250.h         |  85 --------------------------------
 src/lib/uart8250.c             |   1 +
 src/lib/uart8250mem.c          |   1 +
 5 files changed, 111 insertions(+), 91 deletions(-)

diff --git a/src/cpu/allwinner/a10/uart.c b/src/cpu/allwinner/a10/uart.c
index dc98bff..83f677a 100644
--- a/src/cpu/allwinner/a10/uart.c
+++ b/src/cpu/allwinner/a10/uart.c
@@ -7,12 +7,7 @@
 
 #include "uart.h"
 #include <arch/io.h>
-
-/* Give me my 8250 UART definitions!!!! */
-/* TODO: Clean this up when uart8250mem works on ARM */
-#undef CONFIG_CONSOLE_SERIAL8250MEM
-#define CONFIG_CONSOLE_SERIAL8250MEM 1
-#include <uart8250.h>
+#include "drivers/uart8250/uart8250reg.h"
 
 /**
  * \brief Configure line control settings for UART
diff --git a/src/drivers/uart/uart8250reg.h b/src/drivers/uart/uart8250reg.h
new file mode 100644
index 0000000..cdfbb1b
--- /dev/null
+++ b/src/drivers/uart/uart8250reg.h
@@ -0,0 +1,108 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2003 Eric Biederman
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef UART8250REG_H
+#define UART8250REG_H
+
+/* Data */
+#define UART_RBR 0x00
+#define UART_TBR 0x00
+
+/* Control */
+#define UART_IER 0x01
+#define   UART_IER_MSI		0x08 /* Enable Modem status interrupt */
+#define   UART_IER_RLSI		0x04 /* Enable receiver line status interrupt */
+#define   UART_IER_THRI		0x02 /* Enable Transmitter holding register int. */
+#define   UART_IER_RDI		0x01 /* Enable receiver data interrupt */
+
+#define UART_IIR 0x02
+#define   UART_IIR_NO_INT	0x01 /* No interrupts pending */
+#define   UART_IIR_ID		0x06 /* Mask for the interrupt ID */
+
+#define   UART_IIR_MSI		0x00 /* Modem status interrupt */
+#define   UART_IIR_THRI		0x02 /* Transmitter holding register empty */
+#define   UART_IIR_RDI		0x04 /* Receiver data interrupt */
+#define   UART_IIR_RLSI		0x06 /* Receiver line status interrupt */
+
+#define UART_FCR 0x02
+#define   UART_FCR_FIFO_EN	0x01 /* Fifo enable */
+#define   UART_FCR_CLEAR_RCVR	0x02 /* Clear the RCVR FIFO */
+#define   UART_FCR_CLEAR_XMIT	0x04 /* Clear the XMIT FIFO */
+#define   UART_FCR_DMA_SELECT	0x08 /* For DMA applications */
+#define   UART_FCR_TRIGGER_MASK	0xC0 /* Mask for the FIFO trigger range */
+#define   UART_FCR_TRIGGER_1	0x00 /* Mask for trigger set at 1 */
+#define   UART_FCR_TRIGGER_4	0x40 /* Mask for trigger set at 4 */
+#define   UART_FCR_TRIGGER_8	0x80 /* Mask for trigger set at 8 */
+#define   UART_FCR_TRIGGER_14	0xC0 /* Mask for trigger set at 14 */
+
+#define   UART_FCR_RXSR		0x02 /* Receiver soft reset */
+#define   UART_FCR_TXSR		0x04 /* Transmitter soft reset */
+
+#define UART_LCR 0x03
+#define   UART_LCR_WLS_MSK	0x03 /* character length select mask */
+#define   UART_LCR_WLS_5	0x00 /* 5 bit character length */
+#define   UART_LCR_WLS_6	0x01 /* 6 bit character length */
+#define   UART_LCR_WLS_7	0x02 /* 7 bit character length */
+#define   UART_LCR_WLS_8	0x03 /* 8 bit character length */
+#define   UART_LCR_STB		0x04 /* Number of stop Bits, off = 1, on = 1.5 or 2) */
+#define   UART_LCR_PEN		0x08 /* Parity enable */
+#define   UART_LCR_EPS		0x10 /* Even Parity Select */
+#define   UART_LCR_STKP		0x20 /* Stick Parity */
+#define   UART_LCR_SBRK		0x40 /* Set Break */
+#define   UART_LCR_BKSE		0x80 /* Bank select enable */
+#define   UART_LCR_DLAB		0x80 /* Divisor latch access bit */
+
+#define UART_MCR 0x04
+#define   UART_MCR_DTR		0x01 /* DTR   */
+#define   UART_MCR_RTS		0x02 /* RTS   */
+#define   UART_MCR_OUT1		0x04 /* Out 1 */
+#define   UART_MCR_OUT2		0x08 /* Out 2 */
+#define   UART_MCR_LOOP		0x10 /* Enable loopback test mode */
+
+#define UART_MCR_DMA_EN		0x04
+#define UART_MCR_TX_DFR		0x08
+
+#define UART_DLL 0x00
+#define UART_DLM 0x01
+
+/* Status */
+#define UART_LSR 0x05
+#define   UART_LSR_DR		0x01 /* Data ready */
+#define   UART_LSR_OE		0x02 /* Overrun */
+#define   UART_LSR_PE		0x04 /* Parity error */
+#define   UART_LSR_FE		0x08 /* Framing error */
+#define   UART_LSR_BI		0x10 /* Break */
+#define   UART_LSR_THRE		0x20 /* Xmit holding register empty */
+#define   UART_LSR_TEMT		0x40 /* Xmitter empty */
+#define   UART_LSR_ERR		0x80 /* Error */
+
+#define UART_MSR 0x06
+#define   UART_MSR_DCD		0x80 /* Data Carrier Detect */
+#define   UART_MSR_RI		0x40 /* Ring Indicator */
+#define   UART_MSR_DSR		0x20 /* Data Set Ready */
+#define   UART_MSR_CTS		0x10 /* Clear to Send */
+#define   UART_MSR_DDCD		0x08 /* Delta DCD */
+#define   UART_MSR_TERI		0x04 /* Trailing edge ring indicator */
+#define   UART_MSR_DDSR		0x02 /* Delta DSR */
+#define   UART_MSR_DCTS		0x01 /* Delta CTS */
+
+#define UART_SCR 0x07
+#define UART_SPR 0x07
+
+#endif /* UART8250REG_H */
diff --git a/src/include/uart8250.h b/src/include/uart8250.h
index 598cdfa..a214ce1 100644
--- a/src/include/uart8250.h
+++ b/src/include/uart8250.h
@@ -22,91 +22,6 @@
 
 #if CONFIG_CONSOLE_SERIAL8250 || CONFIG_CONSOLE_SERIAL8250MEM
 
-/* Data */
-#define UART_RBR 0x00
-#define UART_TBR 0x00
-
-/* Control */
-#define UART_IER 0x01
-#define   UART_IER_MSI		0x08 /* Enable Modem status interrupt */
-#define   UART_IER_RLSI		0x04 /* Enable receiver line status interrupt */
-#define   UART_IER_THRI		0x02 /* Enable Transmitter holding register int. */
-#define   UART_IER_RDI		0x01 /* Enable receiver data interrupt */
-
-#define UART_IIR 0x02
-#define   UART_IIR_NO_INT	0x01 /* No interrupts pending */
-#define   UART_IIR_ID		0x06 /* Mask for the interrupt ID */
-
-#define   UART_IIR_MSI		0x00 /* Modem status interrupt */
-#define   UART_IIR_THRI		0x02 /* Transmitter holding register empty */
-#define   UART_IIR_RDI		0x04 /* Receiver data interrupt */
-#define   UART_IIR_RLSI		0x06 /* Receiver line status interrupt */
-
-#define UART_FCR 0x02
-#define   UART_FCR_FIFO_EN	0x01 /* Fifo enable */
-#define   UART_FCR_CLEAR_RCVR	0x02 /* Clear the RCVR FIFO */
-#define   UART_FCR_CLEAR_XMIT	0x04 /* Clear the XMIT FIFO */
-#define   UART_FCR_DMA_SELECT	0x08 /* For DMA applications */
-#define   UART_FCR_TRIGGER_MASK	0xC0 /* Mask for the FIFO trigger range */
-#define   UART_FCR_TRIGGER_1	0x00 /* Mask for trigger set at 1 */
-#define   UART_FCR_TRIGGER_4	0x40 /* Mask for trigger set at 4 */
-#define   UART_FCR_TRIGGER_8	0x80 /* Mask for trigger set at 8 */
-#define   UART_FCR_TRIGGER_14	0xC0 /* Mask for trigger set at 14 */
-
-#define   UART_FCR_RXSR		0x02 /* Receiver soft reset */
-#define   UART_FCR_TXSR		0x04 /* Transmitter soft reset */
-
-#define UART_LCR 0x03
-#define   UART_LCR_WLS_MSK	0x03 /* character length select mask */
-#define   UART_LCR_WLS_5	0x00 /* 5 bit character length */
-#define   UART_LCR_WLS_6	0x01 /* 6 bit character length */
-#define   UART_LCR_WLS_7	0x02 /* 7 bit character length */
-#define   UART_LCR_WLS_8	0x03 /* 8 bit character length */
-#define   UART_LCR_STB		0x04 /* Number of stop Bits, off = 1, on = 1.5 or 2) */
-#define   UART_LCR_PEN		0x08 /* Parity enable */
-#define   UART_LCR_EPS		0x10 /* Even Parity Select */
-#define   UART_LCR_STKP		0x20 /* Stick Parity */
-#define   UART_LCR_SBRK		0x40 /* Set Break */
-#define   UART_LCR_BKSE		0x80 /* Bank select enable */
-#define   UART_LCR_DLAB		0x80 /* Divisor latch access bit */
-
-#define UART_MCR 0x04
-#define   UART_MCR_DTR		0x01 /* DTR   */
-#define   UART_MCR_RTS		0x02 /* RTS   */
-#define   UART_MCR_OUT1		0x04 /* Out 1 */
-#define   UART_MCR_OUT2		0x08 /* Out 2 */
-#define   UART_MCR_LOOP		0x10 /* Enable loopback test mode */
-
-#define UART_MCR_DMA_EN		0x04
-#define UART_MCR_TX_DFR		0x08
-
-#define UART_DLL 0x00
-#define UART_DLM 0x01
-
-/* Status */
-#define UART_LSR 0x05
-#define   UART_LSR_DR		0x01 /* Data ready */
-#define   UART_LSR_OE		0x02 /* Overrun */
-#define   UART_LSR_PE		0x04 /* Parity error */
-#define   UART_LSR_FE		0x08 /* Framing error */
-#define   UART_LSR_BI		0x10 /* Break */
-#define   UART_LSR_THRE		0x20 /* Xmit holding register empty */
-#define   UART_LSR_TEMT		0x40 /* Xmitter empty */
-#define   UART_LSR_ERR		0x80 /* Error */
-
-#define UART_MSR 0x06
-#define   UART_MSR_DCD		0x80 /* Data Carrier Detect */
-#define   UART_MSR_RI		0x40 /* Ring Indicator */
-#define   UART_MSR_DSR		0x20 /* Data Set Ready */
-#define   UART_MSR_CTS		0x10 /* Clear to Send */
-#define   UART_MSR_DDCD		0x08 /* Delta DCD */
-#define   UART_MSR_TERI		0x04 /* Trailing edge ring indicator */
-#define   UART_MSR_DDSR		0x02 /* Delta DSR */
-#define   UART_MSR_DCTS		0x01 /* Delta CTS */
-
-#define UART_SCR 0x07
-#define UART_SPR 0x07
-
 #if ((115200 % CONFIG_TTYS0_BAUD) != 0)
 #error Bad ttyS0 baud rate
 #endif
diff --git a/src/lib/uart8250.c b/src/lib/uart8250.c
index bcb137a..4d2cb63 100644
--- a/src/lib/uart8250.c
+++ b/src/lib/uart8250.c
@@ -21,6 +21,7 @@
 #include <arch/io.h>
 #include <uart8250.h>
 #include <trace.h>
+#include "drivers/uart/uart8250reg.h"
 
 /* Should support 8250, 16450, 16550, 16550A type UARTs */
 
diff --git a/src/lib/uart8250mem.c b/src/lib/uart8250mem.c
index 26c83fa..cff67d7 100644
--- a/src/lib/uart8250mem.c
+++ b/src/lib/uart8250mem.c
@@ -22,6 +22,7 @@
 #include <uart8250.h>
 #include <device/device.h>
 #include <delay.h>
+#include "drivers/uart/uart8250reg.h"
 
 /* Should support 8250, 16450, 16550, 16550A type UARTs */
 



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