[coreboot-gerrit] Patch set updated for coreboot: b66e855 lynxpoint: Kill alternative cbfs_load_payload.

[Vladimir Serbinenko (phcoder@gmail.com)]

Vladimir Serbinenko (phcoder at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5131

-gerrit

commit b66e8554bbad22be3e7257a43915d69184fe4ab7
Author: Vladimir Serbinenko <phcoder at gmail.com>
Date:   Wed Feb 5 14:23:56 2014 +0100

    lynxpoint: Kill alternative cbfs_load_payload.
    
    With generic load using 32-bit accesses this is no longer necessarry
    
    Change-Id: I7e8a74ea1ceaa225e1024f9eb43e7280773e2b5a
    Signed-off-by: Vladimir Serbinenko <phcoder at gmail.com>
---
 src/southbridge/intel/lynxpoint/Kconfig       |  1 -
 src/southbridge/intel/lynxpoint/Makefile.inc  |  1 -
 src/southbridge/intel/lynxpoint/spi_loading.c | 90 ---------------------------
 3 files changed, 92 deletions(-)

diff --git a/src/southbridge/intel/lynxpoint/Kconfig b/src/southbridge/intel/lynxpoint/Kconfig
index 5ff00db..970a11d 100644
--- a/src/southbridge/intel/lynxpoint/Kconfig
+++ b/src/southbridge/intel/lynxpoint/Kconfig
@@ -32,7 +32,6 @@ config SOUTH_BRIDGE_OPTIONS # dummy
 	select PCIEXP_ASPM
 	select PCIEXP_COMMON_CLOCK
 	select SPI_FLASH
-	select ALT_CBFS_LOAD_PAYLOAD
 
 config INTEL_LYNXPOINT_LP
 	bool
diff --git a/src/southbridge/intel/lynxpoint/Makefile.inc b/src/southbridge/intel/lynxpoint/Makefile.inc
index 7be2d03..b691e6f 100644
--- a/src/southbridge/intel/lynxpoint/Makefile.inc
+++ b/src/southbridge/intel/lynxpoint/Makefile.inc
@@ -41,7 +41,6 @@ ramstage-y += me_status.c
 ramstage-y += reset.c
 ramstage-y += watchdog.c
 ramstage-y += acpi.c
-ramstage-$(CONFIG_ALT_CBFS_LOAD_PAYLOAD) += spi_loading.c
 
 ramstage-$(CONFIG_ELOG) += elog.c
 ramstage-y += spi.c
diff --git a/src/southbridge/intel/lynxpoint/spi_loading.c b/src/southbridge/intel/lynxpoint/spi_loading.c
deleted file mode 100644
index 57e3af8..0000000
--- a/src/southbridge/intel/lynxpoint/spi_loading.c
+++ /dev/null
@@ -1,90 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013 ChromeOS Authors
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-
-#include <stdlib.h>
-#include <string.h>
-#include <arch/byteorder.h>
-#include <cbmem.h>
-#include <cbfs.h>
-#include <console/console.h>
-#include <cpu/x86/smm.h>
-#if CONFIG_VBOOT_VERIFY_FIRMWARE
-#include <vendorcode/google/chromeos/chromeos.h>
-#else
-static inline void *vboot_get_payload(size_t *len) { return NULL; }
-#endif
-
-#define CACHELINE_SIZE 64
-#define INTRA_CACHELINE_MASK (CACHELINE_SIZE - 1)
-#define CACHELINE_MASK (~INTRA_CACHELINE_MASK)
-
-/* Mirror the payload file to the default SMM location if it is small enough.
- * The default SMM region can be used since no one is using the memory at this
- * location at this stage in the boot. */
-static inline void *spi_mirror(void *file_start, int file_len)
-{
-	int alignment_diff;
-	char *src;
-	char *dest = (void *)SMM_DEFAULT_BASE;
-
-	alignment_diff = (INTRA_CACHELINE_MASK & (long)file_start);
-
-	/* Adjust file length so that the start and end points are aligned to a
-	 * cacheline. Coupled with the ROM caching in the CPU the SPI hardware
-	 * will read and cache full length cachelines. It will also prefetch
-	 * data as well. Once things are mirrored in memory all accesses should
-	 * hit the CPUs cache. */
-	file_len += alignment_diff;
-	file_len = ALIGN(file_len, CACHELINE_SIZE);
-
-	printk(BIOS_DEBUG, "Payload aligned size: 0x%x\n", file_len);
-
-	/* Just pass back the pointer to ROM space if the file is larger
-	 * than the RAM mirror region. */
-	if (file_len > SMM_DEFAULT_SIZE)
-		return file_start;
-
-	src = (void *)(CACHELINE_MASK & (long)file_start);
-	/* Note that if mempcy is not using 32-bit moves the performance will
-	 * degrade because the SPI hardware prefetchers look for
-	 * cacheline-aligned 32-bit accesses to kick in. */
-	memcpy(dest, src, file_len);
-
-	/* Provide pointer into mirrored space. */
-	return &dest[alignment_diff];
-}
-
-void *cbfs_load_payload(struct cbfs_media *media, const char *name)
-{
-	size_t file_len;
-	void *file_start;
-
-	file_start = vboot_get_payload(&file_len);
-
-	if (file_start != NULL)
-		return spi_mirror(file_start, file_len);
-
-	file_start = cbfs_get_file_content(media, name, CBFS_TYPE_PAYLOAD, &file_len);
-
-	if (file_start == NULL)
-		return NULL;
-
-	return spi_mirror(file_start, file_len);
-}