[coreboot-gerrit] New patch to review for coreboot: 85edbea Remove CACHE_ROM.
Vladimir Serbinenko (phcoder@gmail.com)
gerrit at coreboot.org
Wed Feb 5 19:50:26 CET 2014
Vladimir Serbinenko (phcoder at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5146
-gerrit
commit 85edbea369ed55b3a071862d5d4182219376be22
Author: Vladimir Serbinenko <phcoder at gmail.com>
Date: Wed Feb 5 19:46:45 2014 +0100
Remove CACHE_ROM.
With the improvements down in this patch stack, speed up by CACHE_ROM
is reduced a lot.
On the other hand this makes coreboot run out of MTRRs on all systems
I tried it on, hence screwing up I/O access and cahce coherency in worst
cases.
Remove this as a buggy feature until we figure out how todo it properly
if necessarry.
Change-Id: I858d78a907bf042fcc21fdf7a2bf899e9f6b591d
Signed-off-by: Vladimir Serbinenko <phcoder at gmail.com>
---
src/cpu/x86/Kconfig | 7 ---
src/cpu/x86/mtrr/mtrr.c | 76 ---------------------------
src/include/cpu/x86/mtrr.h | 20 +------
src/mainboard/google/Kconfig | 5 --
src/mainboard/google/bolt/Kconfig | 1 -
src/mainboard/google/falco/Kconfig | 1 -
src/mainboard/google/peppy/Kconfig | 1 -
src/mainboard/google/slippy/Kconfig | 1 -
src/mainboard/intel/wtm2/Kconfig | 1 -
src/northbridge/intel/fsp_sandybridge/Kconfig | 4 --
src/soc/intel/baytrail/Kconfig | 1 -
11 files changed, 2 insertions(+), 116 deletions(-)
diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig
index 21282c3..4425ed3 100644
--- a/src/cpu/x86/Kconfig
+++ b/src/cpu/x86/Kconfig
@@ -76,13 +76,6 @@ config LOGICAL_CPUS
bool
default y
-config CACHE_ROM
- bool "Allow for caching system ROM."
- default n
- help
- When selected a variable range MTRR is allocated for coreboot and
- the bootloader enables caching of the system ROM for faster access.
-
config SMM_TSEG
bool
default n
diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c
index dbedf0f..54fdfd8 100644
--- a/src/cpu/x86/mtrr/mtrr.c
+++ b/src/cpu/x86/mtrr/mtrr.c
@@ -185,16 +185,6 @@ static struct memranges *get_physical_address_space(void)
memranges_add_resources(addr_space, mask, match,
MTRR_TYPE_WRCOMB);
-#if CONFIG_CACHE_ROM
- /* Add a write-protect region covering the ROM size
- * when CONFIG_CACHE_ROM is enabled. The ROM is assumed
- * to be located at 4GiB - rom size. */
- resource_t rom_base = RANGE_TO_PHYS_ADDR(
- RANGE_4GB - PHYS_TO_RANGE_ADDR(CACHE_ROM_SIZE));
- memranges_insert(addr_space, rom_base, CACHE_ROM_SIZE,
- MTRR_TYPE_WRPROT);
-#endif
-
/* The address space below 4GiB is special. It needs to be
* covered entirly by range entries so that MTRR calculations
* can be properly done for the full 32-bit address space.
@@ -366,61 +356,6 @@ void x86_setup_fixed_mtrrs(void)
enable_fixed_mtrr();
}
-/* Keep track of the MTRR that covers the ROM for caching purposes. */
-#if CONFIG_CACHE_ROM
-static long rom_cache_mtrr = -1;
-
-long x86_mtrr_rom_cache_var_index(void)
-{
- return rom_cache_mtrr;
-}
-
-void x86_mtrr_enable_rom_caching(void)
-{
- msr_t msr_val;
- unsigned long index;
-
- if (rom_cache_mtrr < 0)
- return;
-
- index = rom_cache_mtrr;
- disable_cache();
- msr_val = rdmsr(MTRRphysBase_MSR(index));
- msr_val.lo &= ~0xff;
- msr_val.lo |= MTRR_TYPE_WRPROT;
- wrmsr(MTRRphysBase_MSR(index), msr_val);
- enable_cache();
-}
-
-void x86_mtrr_disable_rom_caching(void)
-{
- msr_t msr_val;
- unsigned long index;
-
- if (rom_cache_mtrr < 0)
- return;
-
- index = rom_cache_mtrr;
- disable_cache();
- msr_val = rdmsr(MTRRphysBase_MSR(index));
- msr_val.lo &= ~0xff;
- wrmsr(MTRRphysBase_MSR(index), msr_val);
- enable_cache();
-}
-
-static void disable_cache_rom(void *unused)
-{
- x86_mtrr_disable_rom_caching();
-}
-
-BOOT_STATE_INIT_ENTRIES(disable_rom_cache_bscb) = {
- BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY,
- disable_cache_rom, NULL),
- BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT,
- disable_cache_rom, NULL),
-};
-#endif
-
struct var_mtrr_state {
struct memranges *addr_space;
int above4gb;
@@ -468,17 +403,6 @@ static void write_var_mtrr(struct var_mtrr_state *var_state,
mask = (1ULL << var_state->address_bits) - 1;
rsize = rsize & mask;
-#if CONFIG_CACHE_ROM
- /* CONFIG_CACHE_ROM allocates an MTRR specifically for allowing
- * one to turn on caching for faster ROM access. However, it is
- * left to the MTRR callers to enable it. */
- if (mtrr_type == MTRR_TYPE_WRPROT) {
- mtrr_type = MTRR_TYPE_UNCACHEABLE;
- if (rom_cache_mtrr < 0)
- rom_cache_mtrr = var_state->mtrr_index;
- }
-#endif
-
printk(BIOS_DEBUG, "MTRR: %d base 0x%016llx mask 0x%016llx type %d\n",
var_state->mtrr_index, rbase, rsize, mtrr_type);
diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h
index 9414687..d6cf039 100644
--- a/src/include/cpu/x86/mtrr.h
+++ b/src/include/cpu/x86/mtrr.h
@@ -52,10 +52,6 @@
* of the nature of the global MTRR enable flag. Therefore, all direct
* or indirect callers of enable_fixed_mtrr() should ensure that the
* variable MTRR MSRs do not contain bad ranges.
- * 3. If CONFIG_CACHE_ROM is selected an MTRR is allocated for enabling
- * the caching of the ROM. However, it is set to uncacheable (UC). It
- * is the responsibility of the caller to enable it by calling
- * x86_mtrr_enable_rom_caching().
*/
void x86_setup_mtrrs(void);
/*
@@ -71,24 +67,12 @@ void x86_setup_fixed_mtrrs(void);
/* Set up fixed MTRRs but do not enable them. */
void x86_setup_fixed_mtrrs_no_enable(void);
int x86_mtrr_check(void);
-/* ROM caching can be used after variable MTRRs are set up. Beware that
- * enabling CONFIG_CACHE_ROM will eat through quite a few MTRRs based on
- * one's IO hole size and WRCOMB resources. Be sure to check the console
- * log when enabling CONFIG_CACHE_ROM or adding WRCOMB resources. Beware that
+/* ROM caching can be used after variable MTRRs are set up.
+ * Be sure to check the console log when adding WRCOMB resources. Beware that
* on CPUs with core-scoped MTRR registers such as hyperthreaded CPUs the
* rom caching will be disabled if all threads run the MTRR code. Therefore,
* one needs to call x86_mtrr_enable_rom_caching() after all threads of the
* same core have run the MTRR code. */
-#if CONFIG_CACHE_ROM
-void x86_mtrr_enable_rom_caching(void);
-void x86_mtrr_disable_rom_caching(void);
-/* Return the variable range MTRR index of the ROM cache. */
-long x86_mtrr_rom_cache_var_index(void);
-#else
-static inline void x86_mtrr_enable_rom_caching(void) {}
-static inline void x86_mtrr_disable_rom_caching(void) {}
-static inline long x86_mtrr_rom_cache_var_index(void) { return -1; }
-#endif /* CONFIG_CACHE_ROM */
#endif
diff --git a/src/mainboard/google/Kconfig b/src/mainboard/google/Kconfig
index b86b0ad..85c8592 100644
--- a/src/mainboard/google/Kconfig
+++ b/src/mainboard/google/Kconfig
@@ -18,11 +18,6 @@
##
if VENDOR_GOOGLE
-# Auto select common options
-config VENDOR_SPECIFIC_OPTIONS
- def_bool y
- select CACHE_ROM
-
choice
prompt "Mainboard model"
diff --git a/src/mainboard/google/bolt/Kconfig b/src/mainboard/google/bolt/Kconfig
index 1d2b259..3004443 100644
--- a/src/mainboard/google/bolt/Kconfig
+++ b/src/mainboard/google/bolt/Kconfig
@@ -18,7 +18,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select HAVE_SMI_HANDLER
select MAINBOARD_HAS_CHROMEOS
select EXTERNAL_MRC_BLOB
- select CACHE_ROM
select MARK_GRAPHICS_MEM_WRCOMB
select MONOTONIC_TIMER_MSR
diff --git a/src/mainboard/google/falco/Kconfig b/src/mainboard/google/falco/Kconfig
index b372c47..893c4e5 100644
--- a/src/mainboard/google/falco/Kconfig
+++ b/src/mainboard/google/falco/Kconfig
@@ -18,7 +18,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select HAVE_SMI_HANDLER
select MAINBOARD_HAS_CHROMEOS
select EXTERNAL_MRC_BLOB
- select CACHE_ROM
select MARK_GRAPHICS_MEM_WRCOMB
select MONOTONIC_TIMER_MSR
select DRIVERS_I2C_RTD2132
diff --git a/src/mainboard/google/peppy/Kconfig b/src/mainboard/google/peppy/Kconfig
index 7a406e1..59fb8c0 100644
--- a/src/mainboard/google/peppy/Kconfig
+++ b/src/mainboard/google/peppy/Kconfig
@@ -18,7 +18,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select HAVE_SMI_HANDLER
select MAINBOARD_HAS_CHROMEOS
select EXTERNAL_MRC_BLOB
- select CACHE_ROM
select MARK_GRAPHICS_MEM_WRCOMB
select MONOTONIC_TIMER_MSR
diff --git a/src/mainboard/google/slippy/Kconfig b/src/mainboard/google/slippy/Kconfig
index 065830a..3ffacde 100644
--- a/src/mainboard/google/slippy/Kconfig
+++ b/src/mainboard/google/slippy/Kconfig
@@ -18,7 +18,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select HAVE_SMI_HANDLER
select MAINBOARD_HAS_CHROMEOS
select EXTERNAL_MRC_BLOB
- select CACHE_ROM
select MARK_GRAPHICS_MEM_WRCOMB
select MONOTONIC_TIMER_MSR
select MAINBOARD_HAS_NATIVE_VGA_INIT
diff --git a/src/mainboard/intel/wtm2/Kconfig b/src/mainboard/intel/wtm2/Kconfig
index 99ed53c..7ff66ed 100644
--- a/src/mainboard/intel/wtm2/Kconfig
+++ b/src/mainboard/intel/wtm2/Kconfig
@@ -13,7 +13,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select HAVE_ACPI_RESUME
select HAVE_SMI_HANDLER
select MAINBOARD_HAS_CHROMEOS
- select CACHE_ROM
select MARK_GRAPHICS_MEM_WRCOMB
select MAINBOARD_HAS_NATIVE_VGA_INIT
select MONOTONIC_TIMER_MSR
diff --git a/src/northbridge/intel/fsp_sandybridge/Kconfig b/src/northbridge/intel/fsp_sandybridge/Kconfig
index 0c3d5f5..ce366ef 100644
--- a/src/northbridge/intel/fsp_sandybridge/Kconfig
+++ b/src/northbridge/intel/fsp_sandybridge/Kconfig
@@ -87,14 +87,10 @@ config CBFS_SIZE
config ENABLE_FAST_BOOT
bool "Enable Fast Boot"
default y if CPU_INTEL_FSP_MODEL_306AX && SOUTHBRIDGE_INTEL_FSP_BD82X6X
- depends on !CACHE_ROM
help
Enabling this feature will cause MRC data to be cached in NV storage
which will speed up boot time on future reboots and/or power cycles.
- WARNING: This feature combined with the CACHE_ROM may result in undefined
- behavior.
-
config MRC_CACHE_SIZE
hex "MRC Data Cache Size"
default 0x10000
diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig
index 613593e..d3311ef 100644
--- a/src/soc/intel/baytrail/Kconfig
+++ b/src/soc/intel/baytrail/Kconfig
@@ -9,7 +9,6 @@ if SOC_INTEL_BAYTRAIL
config CPU_SPECIFIC_OPTIONS
def_bool y
select CACHE_MRC_SETTINGS
- select CACHE_ROM
select CAR_MIGRATION
select COLLECT_TIMESTAMPS
select CPU_MICROCODE_IN_CBFS
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