[coreboot-gerrit] New patch to review for coreboot: ffa7141 NOTFORMERGE: gm45: fix broken text-mode graphics.

[Francis Rowe (info@gluglug.org.uk)]

Francis Rowe (info at gluglug.org.uk) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8018

-gerrit

commit ffa714170abc11d7b31853fcd3308a436226c8d0
Author: Francis Rowe <info at gluglug.org.uk>
Date:   Wed Dec 31 18:04:25 2014 +0000

    NOTFORMERGE: gm45: fix broken text-mode graphics.
    
    When text-mode graphics (disable "Keep VESA Framebuffer") is
    selected, backlight turns on at payload stage (GRUB tested) but
    no graphics are shown (black screen). Graphics do work after payload
    stage, when booting a GNU/Linux distribution.
    
    (tested on X200. fix doesn't work yet)
    
    Change-Id: Idf6496bb2f578c7dfb15c07f3e46a00ba3da11e7
    Signed-off-by: Francis Rowe <info at gluglug.org.uk>
---
 src/northbridge/intel/gm45/gma.c | 53 ++++++++++++++++++++++------------------
 1 file changed, 29 insertions(+), 24 deletions(-)

diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c
index 74e16ad..482aa1d 100644
--- a/src/northbridge/intel/gm45/gma.c
+++ b/src/northbridge/intel/gm45/gma.c
@@ -174,9 +174,7 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info,
 
 	target_frequency = info->gfx.lvds_dual_channel ? edid.pixel_clock
 		: (2 * edid.pixel_clock);
-#if !IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
-	vga_textmode_init();
-#else
+
 	vga_sr_write(1, 1);
 	vga_sr_write(0x2, 0xf);
 	vga_sr_write(0x3, 0x0);
@@ -200,7 +198,6 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info,
 	write32(mmio + DSPSURF(0), 0);
 	for (i = 0; i < 0x100; i++)
 		write32(mmio + LGC_PALETTE(0) + 4 * i, i * 0x010101);
-#endif
 
 	/* Find suitable divisors.  */
 	for (candp1 = 1; candp1 <= 8; candp1++) {
@@ -272,6 +269,21 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info,
 	       120000 * (5 * pixel_m1 + pixel_m2) / pixel_n
 	       / (pixel_p1 * 7));
 
+	write32(mmio + PF_WIN_POS(0), 0);
+#if !IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
+	write32(mmio + PIPESRC(0), (639 << 16) | 399);
+	write32(mmio + PF_CTL(0),PF_ENABLE | PF_FILTER_MED_3x3);
+	write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16));
+	write32(mmio + PFIT_CONTROL, 0xa0000000);
+#else
+	write32(mmio + PIPESRC(0), ((hactive - 1) << 16) | (vactive - 1));
+	write32(mmio + PF_CTL(0),0);
+	write32(mmio + PF_WIN_SZ(0), 0);
+	write32(mmio + PFIT_CONTROL, 0x20000000);
+#endif
+
+	mdelay(1);
+
 	write32(mmio + LVDS,
 		(hpolarity << 20) | (vpolarity << 21)
 		| (info->gfx.lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL
@@ -328,21 +340,6 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info,
 
 	write32(mmio + PIPECONF(0), PIPECONF_DISABLE);
 
-	write32(mmio + PF_WIN_POS(0), 0);
-#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
-	write32(mmio + PIPESRC(0), ((hactive - 1) << 16) | (vactive - 1));
-	write32(mmio + PF_CTL(0),0);
-	write32(mmio + PF_WIN_SZ(0), 0);
-	write32(mmio + PFIT_CONTROL, 0x20000000);
-#else
-	write32(mmio + PIPESRC(0), (639 << 16) | 399);
-	write32(mmio + PF_CTL(0),PF_ENABLE | PF_FILTER_MED_3x3);
-	write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16));
-	write32(mmio + PFIT_CONTROL, 0xa0000000);
-#endif
-
-	mdelay(1);
-
 	write32(mmio + PIPE_DATA_M1(0), 0x7e000000 | data_m1);
 	write32(mmio + PIPE_DATA_N1(0), data_n1);
 	write32(mmio + PIPE_LINK_M1(0), link_m1);
@@ -359,13 +356,13 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info,
 	write32(mmio + PIPECONF(0), PIPECONF_BPP_6 | PIPECONF_DITHER_EN);
 	write32(mmio + PIPECONF(0), PIPECONF_ENABLE | PIPECONF_BPP_6 | PIPECONF_DITHER_EN);
 
-#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
+#if !IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
+	write32(mmio + VGACNTRL, 0x22c4008e);
+#else
 	write32(mmio + VGACNTRL, 0x22c4008e | VGA_DISP_DISABLE);
 	write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888);
-	mdelay(1);
-#else
-	write32(mmio + VGACNTRL, 0x22c4008e);
 #endif
+	mdelay(1);
 
 	write32(mmio + TRANS_HTOTAL(0),
 		((hactive + right_border + hblank - 1) << 16)
@@ -426,7 +423,15 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info,
 	write32(mmio + DEIIR, 0xffffffff);
 	write32(mmio + SDEIIR, 0xffffffff);
 
-#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
+#if !IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
+	vga_misc_write(0x67);
+
+	write32(mmio + DSPCNTR(0), DISPPLANE_SEL_PIPE_B);
+
+	write32(mmio + VGACNTRL, 0x22c4008e | VGA_PIPE_B_SELECT);
+
+	vga_textmode_init();
+#else
 	memset ((void *) lfb, 0, edid.x_resolution * edid.y_resolution * 4);
 	set_vbe_mode_info_valid(&edid, lfb);
 #endif