[coreboot-gerrit] Patch merged into coreboot/master: 773485b intel CAR: Fix DCACHE_RAM_BASE for old sockets

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit 773485b8920145443da8b09712553c10c954fed1
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date:   Mon Dec 22 16:33:24 2014 +0200

    intel CAR: Fix DCACHE_RAM_BASE for old sockets
    
    When using fixed MTRRs for CAR setup, CONFIG_DCACHE_RAM_BASE is ignored
    and was not correctly set on affected sockets and boards. It was still
    referenced in romstage linker script. This was discovered by clang builds
    failing for cases where DCACHE_RAM_BASE = 0, while gcc builds passed.
    
    The actual DCACHE_RAM_BASE programming is base = 0xd0000 - size, as taken
    from intel/cpu/cache_as_ram.inc.
    
    Change-Id: Ied5ab2e9683f12990f1aad48ee15eaf91133121c
    Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
    Reviewed-on: http://review.coreboot.org/7887
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan at alterapraxis.com>


See http://review.coreboot.org/7887 for details.

-gerrit