[coreboot-gerrit] New patch to review for coreboot: 1a8c103 intel CAR: Fix DCACHE_RAM_BASE for old sockets

Mon Dec 22 15:56:02 CET 2014

Kyösti Mälkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7887

-gerrit

commit 1a8c1034a79ad16c0df1f00846a95b4a3f9b1bd4
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date:   Mon Dec 22 16:33:24 2014 +0200

    intel CAR: Fix DCACHE_RAM_BASE for old sockets
    
    When using fixed MTRRs for CAR setup, CONFIG_DCACHE_RAM_BASE is ignored
    and was not correctly set on affected sockets and boards. It was still
    referenced in romstage linker script. This was discovered by clang builds
    failing for cases where DCACHE_RAM_BASE = 0, while gcc builds passed.
    
    The actual DCACHE_RAM_BASE programming is base = 0xd0000 - size, as taken
    from intel/cpu/cache_as_ram.inc.
    
    Change-Id: Ied5ab2e9683f12990f1aad48ee15eaf91133121c
    Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
---
 src/cpu/intel/slot_1/Kconfig                |  4 ++++
 src/cpu/intel/socket_FC_PGA370/Kconfig      | 11 +++++++++--
 src/cpu/intel/socket_PGA370/Kconfig         |  4 ++++
 src/cpu/intel/socket_mFCBGA479/Kconfig      | 12 ++++++++++++
 src/cpu/intel/socket_mPGA479M/Kconfig       | 12 ++++++++++++
 src/mainboard/digitallogic/adl855pc/Kconfig |  8 --------
 src/mainboard/intel/mtarvon/Kconfig         |  8 --------
 src/mainboard/lanner/em8510/Kconfig         |  8 --------
 src/mainboard/rca/rm4100/Kconfig            |  8 --------
 src/mainboard/thomson/ip1000/Kconfig        |  8 --------
 10 files changed, 41 insertions(+), 42 deletions(-)

diff --git a/src/cpu/intel/slot_1/Kconfig b/src/cpu/intel/slot_1/Kconfig
index 57076d7..25bcbaf 100644
--- a/src/cpu/intel/slot_1/Kconfig
+++ b/src/cpu/intel/slot_1/Kconfig
@@ -30,6 +30,10 @@ config SLOT_SPECIFIC_OPTIONS # dummy
 	select CPU_INTEL_MODEL_6BX
 	select CPU_INTEL_MODEL_6XX
 
+config DCACHE_RAM_BASE
+	hex
+	default 0xcf000
+
 config DCACHE_RAM_SIZE
 	hex
 	default 0x01000
diff --git a/src/cpu/intel/socket_FC_PGA370/Kconfig b/src/cpu/intel/socket_FC_PGA370/Kconfig
index f8ea0f9..91295b1 100644
--- a/src/cpu/intel/socket_FC_PGA370/Kconfig
+++ b/src/cpu/intel/socket_FC_PGA370/Kconfig
@@ -24,7 +24,14 @@ config CPU_INTEL_SOCKET_FC_PGA370
 	select MMX
 	select SSE
 
+if CPU_INTEL_SOCKET_FC_PGA370
+
+config DCACHE_RAM_BASE
+	hex
+	default 0xc8000
+
 config DCACHE_RAM_SIZE
 	hex
-	default 0x8000
-	depends on CPU_INTEL_SOCKET_FC_PGA370
+	default 0x08000
+
+endif
diff --git a/src/cpu/intel/socket_PGA370/Kconfig b/src/cpu/intel/socket_PGA370/Kconfig
index ea2de87..d3cf724 100644
--- a/src/cpu/intel/socket_PGA370/Kconfig
+++ b/src/cpu/intel/socket_PGA370/Kconfig
@@ -30,6 +30,10 @@ config SSE2
 	bool
 	default n
 
+config DCACHE_RAM_BASE
+	hex
+	default 0xcf000
+
 config DCACHE_RAM_SIZE
 	hex
 	default 0x01000
diff --git a/src/cpu/intel/socket_mFCBGA479/Kconfig b/src/cpu/intel/socket_mFCBGA479/Kconfig
index 5576623..7450854 100644
--- a/src/cpu/intel/socket_mFCBGA479/Kconfig
+++ b/src/cpu/intel/socket_mFCBGA479/Kconfig
@@ -3,3 +3,15 @@ config CPU_INTEL_SOCKET_MFCBGA479
 	select CPU_INTEL_MODEL_6BX
 	select MMX
 	select SSE
+
+if CPU_INTEL_SOCKET_MFCBGA479
+
+config DCACHE_RAM_BASE
+	hex
+	default 0xc8000
+
+config DCACHE_RAM_SIZE
+	hex
+	default 0x08000
+
+endif
diff --git a/src/cpu/intel/socket_mPGA479M/Kconfig b/src/cpu/intel/socket_mPGA479M/Kconfig
index 8598eaf..ba6f7ea 100644
--- a/src/cpu/intel/socket_mPGA479M/Kconfig
+++ b/src/cpu/intel/socket_mPGA479M/Kconfig
@@ -6,3 +6,15 @@ config CPU_INTEL_SOCKET_MPGA479M
 	select CPU_INTEL_MODEL_F2X
 	select MMX
 	select SSE
+
+if CPU_INTEL_SOCKET_MPGA479M
+
+config DCACHE_RAM_BASE
+	hex
+	default 0xc8000
+
+config DCACHE_RAM_SIZE
+	hex
+	default 0x08000
+
+endif
diff --git a/src/mainboard/digitallogic/adl855pc/Kconfig b/src/mainboard/digitallogic/adl855pc/Kconfig
index 8c57a89..d8cb4b2 100644
--- a/src/mainboard/digitallogic/adl855pc/Kconfig
+++ b/src/mainboard/digitallogic/adl855pc/Kconfig
@@ -18,14 +18,6 @@ config MAINBOARD_PART_NUMBER
 	string
 	default "smartModule855"
 
-config DCACHE_RAM_BASE
-	hex
-	default 0xffdf8000
-
-config DCACHE_RAM_SIZE
-	hex
-	default 0x8000
-
 config IRQ_SLOT_COUNT
 	int
 	default 5
diff --git a/src/mainboard/intel/mtarvon/Kconfig b/src/mainboard/intel/mtarvon/Kconfig
index 4097fa7..75bca40 100644
--- a/src/mainboard/intel/mtarvon/Kconfig
+++ b/src/mainboard/intel/mtarvon/Kconfig
@@ -23,14 +23,6 @@ config IRQ_SLOT_COUNT
 	int
 	default 1
 
-config DCACHE_RAM_BASE
-	hex
-	default 0xffdf8000
-
-config DCACHE_RAM_SIZE
-	hex
-	default 0x8000
-
 config MAX_CPUS
 	int
 	default 4
diff --git a/src/mainboard/lanner/em8510/Kconfig b/src/mainboard/lanner/em8510/Kconfig
index e042e81..2919df9 100644
--- a/src/mainboard/lanner/em8510/Kconfig
+++ b/src/mainboard/lanner/em8510/Kconfig
@@ -18,14 +18,6 @@ config MAINBOARD_PART_NUMBER
 	string
 	default "EM-8510"
 
-config DCACHE_RAM_BASE
-	hex
-	default 0xffdf8000
-
-config DCACHE_RAM_SIZE
-	hex
-	default 0x8000
-
 config IRQ_SLOT_COUNT
 	int
 	default 10
diff --git a/src/mainboard/rca/rm4100/Kconfig b/src/mainboard/rca/rm4100/Kconfig
index 8f04505..a6f216e 100644
--- a/src/mainboard/rca/rm4100/Kconfig
+++ b/src/mainboard/rca/rm4100/Kconfig
@@ -18,14 +18,6 @@ config MAINBOARD_PART_NUMBER
 	string
 	default "RM4100"
 
-config DCACHE_RAM_BASE
-	hex
-	default 0xffdf8000
-
-config DCACHE_RAM_SIZE
-	hex
-	default 0x8000
-
 config IRQ_SLOT_COUNT
 	int
 	default 7
diff --git a/src/mainboard/thomson/ip1000/Kconfig b/src/mainboard/thomson/ip1000/Kconfig
index 80d365c..f775e2b 100644
--- a/src/mainboard/thomson/ip1000/Kconfig
+++ b/src/mainboard/thomson/ip1000/Kconfig
@@ -19,14 +19,6 @@ config MAINBOARD_PART_NUMBER
 	string
 	default "IP1000"
 
-config DCACHE_RAM_BASE
-	hex
-	default 0xffdf8000
-
-config DCACHE_RAM_SIZE
-	hex
-	default 0x8000
-
 config IRQ_SLOT_COUNT
 	int
 	default 7

