[coreboot-gerrit] Patch set updated for coreboot: e6977cb AGESA: Only fam14 sets Ontario APU IDs
Kyösti Mälkki (kyosti.malkki@gmail.com)
gerrit at coreboot.org
Fri Dec 19 19:33:02 CET 2014
Kyösti Mälkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7810
-gerrit
commit e6977cb74165b125a8fd5a1860a0fdd94d46a422
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date: Sun Dec 14 09:26:04 2014 +0200
AGESA: Only fam14 sets Ontario APU IDs
Change-Id: I3d249a1234599e3820e4ad9b852bbb03a89dd49a
Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
---
src/northbridge/amd/agesa/agesawrapper.h | 3 ---
src/northbridge/amd/agesa/family12/agesawrapper.c | 8 --------
src/northbridge/amd/agesa/family14/agesawrapper.c | 4 ++++
src/northbridge/amd/pi/agesawrapper.h | 3 ---
4 files changed, 4 insertions(+), 14 deletions(-)
diff --git a/src/northbridge/amd/agesa/agesawrapper.h b/src/northbridge/amd/agesa/agesawrapper.h
index 7b61b4c..421212e 100644
--- a/src/northbridge/amd/agesa/agesawrapper.h
+++ b/src/northbridge/amd/agesa/agesawrapper.h
@@ -24,9 +24,6 @@
#include "Porting.h"
#include "AGESA.h"
-/* Define AMD Ontario APPU SSID/SVID */
-#define AMD_APU_SVID 0x1022
-#define AMD_APU_SSID 0x1234
#define PCIE_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS
enum {
diff --git a/src/northbridge/amd/agesa/family12/agesawrapper.c b/src/northbridge/amd/agesa/family12/agesawrapper.c
index 8d0fe90..0c441ee 100644
--- a/src/northbridge/amd/agesa/family12/agesawrapper.c
+++ b/src/northbridge/amd/agesa/family12/agesawrapper.c
@@ -186,14 +186,6 @@ AGESA_STATUS agesawrapper_amdinitmmio(VOID)
MsrReg = MsrReg | 0x0000400000000000ull;
LibAmdMsrWrite(0xC001001F, &MsrReg, &StdHeader);
- /* Set Ontario Link Data */
-//- PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0xE0);
-//- PciData = 0x01308002;
-//- LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-//- PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0xE4);
-//- PciData = (AMD_APU_SSID<<0x10)|AMD_APU_SVID;
-//- LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-
/* Enable Non-Post Memory in CPU */
PciData = ((CONFIG_MMCONF_BASE_ADDRESS >> 8) | 0x3FF80);
PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x018, 0x01, 0xA4);
diff --git a/src/northbridge/amd/agesa/family14/agesawrapper.c b/src/northbridge/amd/agesa/family14/agesawrapper.c
index 8d80ef1..70d8918 100644
--- a/src/northbridge/amd/agesa/family14/agesawrapper.c
+++ b/src/northbridge/amd/agesa/family14/agesawrapper.c
@@ -36,6 +36,10 @@
#define MMCONF_ENABLE 1
+/* Define AMD Ontario APPU SSID/SVID */
+#define AMD_APU_SVID 0x1022
+#define AMD_APU_SSID 0x1234
+
/* ACPI table pointers returned by AmdInitLate */
VOID *DmiTable = NULL;
VOID *AcpiPstate = NULL;
diff --git a/src/northbridge/amd/pi/agesawrapper.h b/src/northbridge/amd/pi/agesawrapper.h
index b345567..d6558c4 100644
--- a/src/northbridge/amd/pi/agesawrapper.h
+++ b/src/northbridge/amd/pi/agesawrapper.h
@@ -24,9 +24,6 @@
#include "Porting.h"
#include "AGESA.h"
-/* Define AMD APU and SoC SSID/SVID */
-#define AMD_APU_SVID 0x1022
-#define AMD_APU_SSID 0x1234
#define PCIE_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS
enum {
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