[coreboot-gerrit] Patch set updated for coreboot: 88c1b88 x86: Change MMIO functions to correspond to other architectures
Kevin Paul Herbert (kph@meraki.net)
gerrit at coreboot.org
Tue Dec 16 03:25:07 CET 2014
Kevin Paul Herbert (kph at meraki.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7784
-gerrit
commit 88c1b885121169777c00af370c5065f430821b1a
Author: Kevin Paul Herbert <kph at meraki.net>
Date: Mon Dec 15 18:18:47 2014 -0800
x86: Change MMIO functions to correspond to other architectures
Change the x86 MMIO functions to match the definitions in the
non-x86 architectures (and in Linux). The read functions take
a const volatile void *, and the write functions take a volatile
void *. Also, the write operations are writeX(val, addr) - previously
x86 was writeX(addr, val).
Done as a Coccinelle patch:
@@
expression val, addr;
@@
- write8(addr, val)
+ write8(val, (void *)(uintptr_t)(addr))
@@
expression val, addr;
@@
- write16(addr, val)
+ write16(val, (void *)(uintptr_t)(addr))
@@
expression val, addr;
@@
- write32(addr, val)
+ write32(val, (void *)(uintptr_t)(addr))
@@
expression addr;
@@
- read8(addr)
+ read8((void *)(uintptr_t)(addr))
@@
expression addr;
@@
- read16(addr)
+ read16((void *)(uintptr_t)(addr))
@@
expression addr;
@@
- read32(addr)
+ read32((void *)(uintptr_t)(addr))
Change-Id: Ic26dd8a72d82828b69be3c04944710681b7bd330
Signed-off-by: Kevin Paul Herbert <kph at meraki.net>
---
src/arch/x86/include/arch/io.h | 12 +-
src/arch/x86/include/arch/pci_mmio_cfg.h | 12 +-
src/arch/x86/lib/ebda.c | 6 +-
src/arch/x86/lib/ioapic.c | 8 +-
src/arch/x86/lib/pci_ops_mmconf.c | 14 +-
src/device/azalia_device.c | 27 +-
src/device/oprom/realmode/x86.c | 2 +-
src/drivers/ati/ragexl/atyfb.h | 12 +-
src/drivers/ati/ragexl/xlinit.c | 6 +-
src/drivers/intel/gma/edid.c | 22 +-
src/drivers/uart/oxpcie.c | 5 +-
src/drivers/uart/uart8250mem.c | 4 +-
src/drivers/usb/ehci_debug.c | 116 +-
src/drivers/usb/pci_ehci.c | 2 +-
src/lib/reg_script.c | 12 +-
src/mainboard/amd/torpedo/mptable.c | 4 +-
src/mainboard/asus/dsbf/romstage.c | 14 +-
src/mainboard/intel/eagleheights/debug.c | 2 +-
src/mainboard/intel/eagleheights/mptable.c | 16 +-
src/mainboard/intel/eagleheights/romstage.c | 22 +-
src/mainboard/intel/jarrell/debug.c | 2 +-
src/mainboard/intel/mohonpeak/romstage.c | 20 +-
src/mainboard/supermicro/x6dai_g/debug.c | 2 +-
src/mainboard/supermicro/x6dhe_g/debug.c | 2 +-
src/mainboard/supermicro/x6dhe_g2/debug.c | 2 +-
src/mainboard/supermicro/x6dhr_ig/debug.c | 2 +-
src/mainboard/supermicro/x6dhr_ig2/debug.c | 2 +-
src/mainboard/supermicro/x7db8/romstage.c | 14 +-
src/mainboard/thomson/ip1000/mainboard.c | 6 +-
src/northbridge/amd/gx1/northbridge.c | 4 +-
src/northbridge/amd/gx1/raminit.c | 4 +-
src/northbridge/intel/e7501/raminit.c | 59 +-
src/northbridge/intel/e7505/raminit.c | 72 +-
src/northbridge/intel/e7520/raminit.c | 157 +-
src/northbridge/intel/e7525/raminit.c | 157 +-
src/northbridge/intel/fsp_sandybridge/acpi.c | 2 +-
src/northbridge/intel/gm45/gma.c | 334 ++--
src/northbridge/intel/gm45/raminit.c | 12 +-
.../intel/gm45/raminit_read_write_training.c | 14 +-
.../gm45/raminit_receive_enable_calibration.c | 2 +-
src/northbridge/intel/haswell/acpi.c | 2 +-
src/northbridge/intel/haswell/gma.c | 4 +-
src/northbridge/intel/haswell/minihd.c | 8 +-
src/northbridge/intel/i3100/raminit.c | 142 +-
src/northbridge/intel/i3100/raminit_ep80579.c | 96 +-
src/northbridge/intel/i440bx/raminit.c | 2 +-
src/northbridge/intel/i440lx/raminit.c | 2 +-
src/northbridge/intel/i5000/raminit.c | 11 +-
src/northbridge/intel/i82810/raminit.c | 4 +-
src/northbridge/intel/i82830/raminit.c | 8 +-
src/northbridge/intel/i82830/smihandler.c | 5 +-
src/northbridge/intel/i855/raminit.c | 2 +-
src/northbridge/intel/i945/gma.c | 227 ++-
src/northbridge/intel/i945/raminit.c | 2 +-
src/northbridge/intel/i945/rcven.c | 4 +-
src/northbridge/intel/nehalem/acpi.c | 2 +-
src/northbridge/intel/nehalem/gma.c | 398 +++--
src/northbridge/intel/nehalem/raminit.c | 164 +-
src/northbridge/intel/sandybridge/acpi.c | 2 +-
src/northbridge/intel/sandybridge/gma.c | 4 +-
.../intel/sandybridge/gma_ivybridge_lvds.c | 460 +++---
.../intel/sandybridge/gma_sandybridge_lvds.c | 402 +++--
src/northbridge/intel/sandybridge/raminit_native.c | 1595 +++++++++++---------
src/northbridge/via/cn700/raminit.c | 20 +-
src/northbridge/via/cx700/raminit.c | 155 +-
src/soc/intel/baytrail/acpi.c | 2 +-
src/soc/intel/baytrail/baytrail/gpio.h | 15 +-
src/soc/intel/baytrail/gfx.c | 2 +-
src/soc/intel/baytrail/gpio.c | 14 +-
src/soc/intel/baytrail/iosf.c | 4 +-
src/soc/intel/baytrail/lpe.c | 9 +-
src/soc/intel/baytrail/pmutil.c | 9 +-
src/soc/intel/baytrail/romstage/romstage.c | 13 +-
src/soc/intel/baytrail/sata.c | 28 +-
src/soc/intel/baytrail/smm.c | 2 +-
src/soc/intel/baytrail/southcluster.c | 59 +-
src/soc/intel/baytrail/spi.c | 24 +-
src/soc/intel/broadwell/adsp.c | 7 +-
src/soc/intel/broadwell/hda.c | 4 +-
src/soc/intel/broadwell/igd.c | 4 +-
src/soc/intel/broadwell/me.c | 8 +-
src/soc/intel/broadwell/minihd.c | 8 +-
src/soc/intel/broadwell/sata.c | 14 +-
src/soc/intel/broadwell/serialio.c | 36 +-
src/soc/intel/broadwell/spi.c | 24 +-
src/soc/intel/broadwell/usbdebug.c | 5 +-
src/soc/intel/broadwell/xhci.c | 21 +-
src/soc/intel/common/hda_verb.c | 25 +-
src/soc/intel/fsp_baytrail/acpi.c | 2 +-
src/soc/intel/fsp_baytrail/baytrail/gpio.h | 15 +-
src/soc/intel/fsp_baytrail/bootblock/bootblock.c | 3 +-
src/soc/intel/fsp_baytrail/gpio.c | 10 +-
src/soc/intel/fsp_baytrail/iosf.c | 4 +-
src/soc/intel/fsp_baytrail/pmutil.c | 9 +-
src/soc/intel/fsp_baytrail/romstage/romstage.c | 24 +-
src/soc/intel/fsp_baytrail/smm.c | 2 +-
src/soc/intel/fsp_baytrail/southcluster.c | 38 +-
src/soc/intel/fsp_baytrail/spi.c | 24 +-
src/southbridge/amd/agesa/hudson/enable_usbdebug.c | 5 +-
src/southbridge/amd/agesa/hudson/hudson.c | 8 +-
src/southbridge/amd/agesa/hudson/imc.c | 20 +-
src/southbridge/amd/agesa/hudson/smi.h | 8 +-
src/southbridge/amd/agesa/hudson/spi.c | 4 +-
src/southbridge/amd/amd8111/nic.c | 7 +-
src/southbridge/amd/cimx/sb800/spi.c | 20 +-
src/southbridge/amd/cs5530/vga.c | 65 +-
src/southbridge/amd/cs5536/cs5536.c | 28 +-
src/southbridge/amd/pi/avalon/enable_usbdebug.c | 5 +-
src/southbridge/amd/pi/avalon/hudson.c | 8 +-
src/southbridge/amd/pi/avalon/smi.h | 8 +-
src/southbridge/amd/sb600/hda.c | 18 +-
src/southbridge/amd/sb600/sata.c | 24 +-
src/southbridge/amd/sb600/usb.c | 8 +-
src/southbridge/amd/sb700/enable_usbdebug.c | 5 +-
src/southbridge/amd/sb700/hda.c | 16 +-
src/southbridge/amd/sb700/sata.c | 28 +-
src/southbridge/amd/sb700/usb.c | 8 +-
src/southbridge/amd/sb800/enable_usbdebug.c | 5 +-
src/southbridge/amd/sb800/hda.c | 16 +-
src/southbridge/amd/sb800/sata.c | 36 +-
src/southbridge/amd/sb800/usb.c | 4 +-
src/southbridge/broadcom/bcm5785/sata.c | 22 +-
src/southbridge/intel/bd82x6x/azalia.c | 31 +-
src/southbridge/intel/bd82x6x/early_pch_native.c | 452 +++---
src/southbridge/intel/bd82x6x/early_thermal.c | 25 +-
src/southbridge/intel/bd82x6x/early_usb_native.c | 22 +-
src/southbridge/intel/bd82x6x/me.c | 8 +-
src/southbridge/intel/bd82x6x/me_8.x.c | 8 +-
src/southbridge/intel/bd82x6x/sata.c | 19 +-
src/southbridge/intel/bd82x6x/usb_ehci.c | 5 +-
src/southbridge/intel/common/spi.c | 24 +-
src/southbridge/intel/fsp_bd82x6x/azalia.c | 31 +-
src/southbridge/intel/fsp_bd82x6x/me.c | 8 +-
src/southbridge/intel/fsp_bd82x6x/me_8.x.c | 8 +-
src/southbridge/intel/fsp_bd82x6x/sata.c | 4 +-
src/southbridge/intel/fsp_rangeley/early_init.c | 9 +-
src/southbridge/intel/fsp_rangeley/gpio.c | 36 +-
src/southbridge/intel/fsp_rangeley/lpc.c | 27 +-
src/southbridge/intel/fsp_rangeley/romstage.c | 5 +-
src/southbridge/intel/fsp_rangeley/sata.c | 4 +-
src/southbridge/intel/fsp_rangeley/spi.c | 24 +-
src/southbridge/intel/i82801gx/azalia.c | 22 +-
src/southbridge/intel/i82801gx/usb_ehci.c | 4 +-
src/southbridge/intel/i82801ix/hdaudio.c | 24 +-
src/southbridge/intel/i82801ix/sata.c | 21 +-
src/southbridge/intel/i82801ix/thermal.c | 16 +-
src/southbridge/intel/ibexpeak/azalia.c | 31 +-
src/southbridge/intel/ibexpeak/early_thermal.c | 7 +-
src/southbridge/intel/ibexpeak/lpc.c | 3 +-
src/southbridge/intel/ibexpeak/me.c | 8 +-
src/southbridge/intel/ibexpeak/sata.c | 19 +-
src/southbridge/intel/ibexpeak/thermal.c | 14 +-
src/southbridge/intel/ibexpeak/usb_ehci.c | 5 +-
src/southbridge/intel/lynxpoint/azalia.c | 4 +-
src/southbridge/intel/lynxpoint/hda_verb.c | 25 +-
src/southbridge/intel/lynxpoint/me_9.x.c | 8 +-
src/southbridge/intel/lynxpoint/sata.c | 15 +-
src/southbridge/intel/lynxpoint/serialio.c | 32 +-
src/southbridge/intel/lynxpoint/usb_ehci.c | 15 +-
src/southbridge/intel/lynxpoint/usb_xhci.c | 31 +-
src/southbridge/intel/sch/audio.c | 34 +-
src/southbridge/nvidia/ck804/nic.c | 10 +-
src/southbridge/nvidia/mcp55/azalia.c | 22 +-
src/southbridge/nvidia/mcp55/nic.c | 29 +-
src/southbridge/sis/sis966/aza.c | 32 +-
src/southbridge/sis/sis966/nic.c | 18 +-
src/southbridge/sis/sis966/usb2.c | 2 +-
167 files changed, 3623 insertions(+), 3330 deletions(-)
diff --git a/src/arch/x86/include/arch/io.h b/src/arch/x86/include/arch/io.h
index d5cdf35..57a79a5 100644
--- a/src/arch/x86/include/arch/io.h
+++ b/src/arch/x86/include/arch/io.h
@@ -142,32 +142,32 @@ static inline void insl(uint16_t port, void *addr, unsigned long count)
);
}
-static inline __attribute__((always_inline)) uint8_t read8(unsigned long addr)
+static inline __attribute__((always_inline)) uint8_t read8(volatile const void *addr)
{
return *((volatile uint8_t *)(addr));
}
-static inline __attribute__((always_inline)) uint16_t read16(unsigned long addr)
+static inline __attribute__((always_inline)) uint16_t read16(volatile const void *addr)
{
return *((volatile uint16_t *)(addr));
}
-static inline __attribute__((always_inline)) uint32_t read32(unsigned long addr)
+static inline __attribute__((always_inline)) uint32_t read32(volatile const void *addr)
{
return *((volatile uint32_t *)(addr));
}
-static inline __attribute__((always_inline)) void write8(unsigned long addr, uint8_t value)
+static inline __attribute__((always_inline)) void write8(uint8_t value, volatile void *addr)
{
*((volatile uint8_t *)(addr)) = value;
}
-static inline __attribute__((always_inline)) void write16(unsigned long addr, uint16_t value)
+static inline __attribute__((always_inline)) void write16(uint16_t value, volatile void *addr)
{
*((volatile uint16_t *)(addr)) = value;
}
-static inline __attribute__((always_inline)) void write32(unsigned long addr, uint32_t value)
+static inline __attribute__((always_inline)) void write32(uint32_t value, volatile void *addr)
{
*((volatile uint32_t *)(addr)) = value;
}
diff --git a/src/arch/x86/include/arch/pci_mmio_cfg.h b/src/arch/x86/include/arch/pci_mmio_cfg.h
index b62a2166b..7b69c8b 100644
--- a/src/arch/x86/include/arch/pci_mmio_cfg.h
+++ b/src/arch/x86/include/arch/pci_mmio_cfg.h
@@ -30,7 +30,7 @@ u8 pcie_read_config8(pci_devfn_t dev, unsigned int where)
{
unsigned long addr;
addr = DEFAULT_PCIEXBAR | dev | where;
- return read8(addr);
+ return read8((void *)(uintptr_t)(addr));
}
static inline __attribute__ ((always_inline))
@@ -38,7 +38,7 @@ u16 pcie_read_config16(pci_devfn_t dev, unsigned int where)
{
unsigned long addr;
addr = DEFAULT_PCIEXBAR | dev | (where & ~1);
- return read16(addr);
+ return read16((void *)(uintptr_t)(addr));
}
static inline __attribute__ ((always_inline))
@@ -46,7 +46,7 @@ u32 pcie_read_config32(pci_devfn_t dev, unsigned int where)
{
unsigned long addr;
addr = DEFAULT_PCIEXBAR | dev | (where & ~3);
- return read32(addr);
+ return read32((void *)(uintptr_t)(addr));
}
static inline __attribute__ ((always_inline))
@@ -54,7 +54,7 @@ void pcie_write_config8(pci_devfn_t dev, unsigned int where, u8 value)
{
unsigned long addr;
addr = DEFAULT_PCIEXBAR | dev | where;
- write8(addr, value);
+ write8(value, (void *)(uintptr_t)(addr));
}
static inline __attribute__ ((always_inline))
@@ -62,7 +62,7 @@ void pcie_write_config16(pci_devfn_t dev, unsigned int where, u16 value)
{
unsigned long addr;
addr = DEFAULT_PCIEXBAR | dev | (where & ~1);
- write16(addr, value);
+ write16(value, (void *)(uintptr_t)(addr));
}
static inline __attribute__ ((always_inline))
@@ -70,7 +70,7 @@ void pcie_write_config32(pci_devfn_t dev, unsigned int where, u32 value)
{
unsigned long addr;
addr = DEFAULT_PCIEXBAR | dev | (where & ~3);
- write32(addr, value);
+ write32(value, (void *)(uintptr_t)(addr));
}
static inline __attribute__ ((always_inline))
diff --git a/src/arch/x86/lib/ebda.c b/src/arch/x86/lib/ebda.c
index 7efc662..aa09b18 100644
--- a/src/arch/x86/lib/ebda.c
+++ b/src/arch/x86/lib/ebda.c
@@ -37,12 +37,12 @@ void setup_ebda(u32 low_memory_size, u16 ebda_segment, u16 ebda_size)
/* clear BIOS DATA AREA */
memset((void *)X86_BDA_BASE, 0, X86_BDA_SIZE);
- write16(X86_EBDA_LOWMEM, (low_memory_size >> 10));
- write16(X86_EBDA_SEGMENT, ebda_segment);
+ write16((low_memory_size >> 10), (void *)(uintptr_t)(X86_EBDA_LOWMEM));
+ write16(ebda_segment, (void *)(uintptr_t)(X86_EBDA_SEGMENT));
/* Set up EBDA */
memset((void *)(ebda_segment << 4), 0, ebda_size);
- write16((ebda_segment << 4), (ebda_size >> 10));
+ write16((ebda_size >> 10), (void *)(uintptr_t)((ebda_segment << 4)));
}
void setup_default_ebda(void)
diff --git a/src/arch/x86/lib/ioapic.c b/src/arch/x86/lib/ioapic.c
index 7fb25ba..b4ac2ef 100644
--- a/src/arch/x86/lib/ioapic.c
+++ b/src/arch/x86/lib/ioapic.c
@@ -24,14 +24,14 @@
u32 io_apic_read(u32 ioapic_base, u32 reg)
{
- write32(ioapic_base, reg);
- return read32(ioapic_base + 0x10);
+ write32(reg, (void *)(uintptr_t)(ioapic_base));
+ return read32((void *)(uintptr_t)(ioapic_base + 0x10));
}
void io_apic_write(u32 ioapic_base, u32 reg, u32 value)
{
- write32(ioapic_base, reg);
- write32(ioapic_base + 0x10, value);
+ write32(reg, (void *)(uintptr_t)(ioapic_base));
+ write32(value, (void *)(uintptr_t)(ioapic_base + 0x10));
}
static int ioapic_interrupt_count(int ioapic_base)
diff --git a/src/arch/x86/lib/pci_ops_mmconf.c b/src/arch/x86/lib/pci_ops_mmconf.c
index 4eaf297..cbc7199 100644
--- a/src/arch/x86/lib/pci_ops_mmconf.c
+++ b/src/arch/x86/lib/pci_ops_mmconf.c
@@ -18,37 +18,39 @@
static uint8_t pci_mmconf_read_config8(struct bus *pbus, int bus, int devfn,
int where)
{
- return (read8(PCI_MMIO_ADDR(bus, devfn, where)));
+ return (read8((void *)(uintptr_t)(PCI_MMIO_ADDR(bus, devfn, where))));
}
static uint16_t pci_mmconf_read_config16(struct bus *pbus, int bus, int devfn,
int where)
{
- return (read16(PCI_MMIO_ADDR(bus, devfn, where) & ~1));
+ return (read16((void *)(uintptr_t)(PCI_MMIO_ADDR(bus, devfn, where) & ~1)));
}
static uint32_t pci_mmconf_read_config32(struct bus *pbus, int bus, int devfn,
int where)
{
- return (read32(PCI_MMIO_ADDR(bus, devfn, where) & ~3));
+ return (read32((void *)(uintptr_t)(PCI_MMIO_ADDR(bus, devfn, where) & ~3)));
}
static void pci_mmconf_write_config8(struct bus *pbus, int bus, int devfn,
int where, uint8_t value)
{
- write8(PCI_MMIO_ADDR(bus, devfn, where), value);
+ write8(value, (void *)(uintptr_t)(PCI_MMIO_ADDR(bus, devfn, where)));
}
static void pci_mmconf_write_config16(struct bus *pbus, int bus, int devfn,
int where, uint16_t value)
{
- write16(PCI_MMIO_ADDR(bus, devfn, where) & ~1, value);
+ write16(value,
+ (void *)(uintptr_t)(PCI_MMIO_ADDR(bus, devfn, where) & ~1));
}
static void pci_mmconf_write_config32(struct bus *pbus, int bus, int devfn,
int where, uint32_t value)
{
- write32(PCI_MMIO_ADDR(bus, devfn, where) & ~3, value);
+ write32(value,
+ (void *)(uintptr_t)(PCI_MMIO_ADDR(bus, devfn, where) & ~3));
}
const struct pci_bus_operations pci_ops_mmconf = {
diff --git a/src/device/azalia_device.c b/src/device/azalia_device.c
index b250f3d..c7e3ef6 100644
--- a/src/device/azalia_device.c
+++ b/src/device/azalia_device.c
@@ -37,10 +37,10 @@ static int set_bits(u32 port, u32 mask, u32 val)
/* Write (val & mask) to port */
val &= mask;
- reg32 = read32(port);
+ reg32 = read32((void *)(uintptr_t)(port));
reg32 &= ~mask;
reg32 |= val;
- write32(port, reg32);
+ write32(reg32, (void *)(uintptr_t)(port));
/* Wait for readback of register to
* match what was just written to it
@@ -49,7 +49,7 @@ static int set_bits(u32 port, u32 mask, u32 val)
do {
/* Wait 1ms based on BKDG wait time */
mdelay(1);
- reg32 = read32(port);
+ reg32 = read32((void *)(uintptr_t)(port));
reg32 &= mask;
} while ((reg32 != val) && --count);
@@ -69,9 +69,9 @@ static int codec_detect(u32 base)
goto no_codec;
/* clear STATESTS bits (BAR + 0xE)[2:0] */
- reg32 = read32(base + 0x0E);
+ reg32 = read32((void *)(uintptr_t)(base + 0x0E));
reg32 |= 7;
- write32(base + 0x0E, reg32);
+ write32(reg32, (void *)(uintptr_t)(base + 0x0E));
/* Wait for readback of register to
* match what was just written to it
@@ -80,7 +80,7 @@ static int codec_detect(u32 base)
do {
/* Wait 1ms based on BKDG wait time */
mdelay(1);
- reg32 = read32(base + 0x0E);
+ reg32 = read32((void *)(uintptr_t)(base + 0x0E));
} while ((reg32 != 0) && --count);
/* Timeout occured */
if (!count)
@@ -95,7 +95,7 @@ static int codec_detect(u32 base)
goto no_codec;
/* Read in Codec location (BAR + 0xe)[2..0] */
- reg32 = read32(base + 0xe);
+ reg32 = read32((void *)(uintptr_t)(base + 0xe));
reg32 &= 0x0f;
if (!reg32)
goto no_codec;
@@ -144,7 +144,7 @@ static int wait_for_ready(u32 base)
int timeout = 50;
while (timeout--) {
- u32 reg32 = read32(base + HDA_ICII_REG);
+ u32 reg32 = read32((void *)(uintptr_t)(base + HDA_ICII_REG));
if (!(reg32 & HDA_ICII_BUSY))
return 0;
udelay(1);
@@ -166,13 +166,14 @@ static int wait_for_valid(u32 base)
int timeout = 25;
- write32(base + HDA_ICII_REG, HDA_ICII_VALID | HDA_ICII_BUSY);
+ write32(HDA_ICII_VALID | HDA_ICII_BUSY,
+ (void *)(uintptr_t)(base + HDA_ICII_REG));
while (timeout--) {
udelay(1);
}
timeout = 50;
while (timeout--) {
- u32 reg32 = read32(base + HDA_ICII_REG);
+ u32 reg32 = read32((void *)(uintptr_t)(base + HDA_ICII_REG));
if ((reg32 & (HDA_ICII_VALID | HDA_ICII_BUSY)) ==
HDA_ICII_VALID)
return 0;
@@ -196,12 +197,12 @@ static void codec_init(struct device *dev, u32 base, int addr)
return;
reg32 = (addr << 28) | 0x000f0000;
- write32(base + 0x60, reg32);
+ write32(reg32, (void *)(uintptr_t)(base + 0x60));
if (wait_for_valid(base) == -1)
return;
- reg32 = read32(base + 0x64);
+ reg32 = read32((void *)(uintptr_t)(base + 0x64));
/* 2 */
printk(BIOS_DEBUG, "azalia_audio: codec viddid: %08x\n", reg32);
@@ -218,7 +219,7 @@ static void codec_init(struct device *dev, u32 base, int addr)
if (wait_for_ready(base) == -1)
return;
- write32(base + 0x60, verb[i]);
+ write32(verb[i], (void *)(uintptr_t)(base + 0x60));
if (wait_for_valid(base) == -1)
return;
diff --git a/src/device/oprom/realmode/x86.c b/src/device/oprom/realmode/x86.c
index fc3c40c..e0e19bc 100644
--- a/src/device/oprom/realmode/x86.c
+++ b/src/device/oprom/realmode/x86.c
@@ -80,7 +80,7 @@ static void setup_rombios(void)
memcpy((void *)0xfffd9, &ident, 7);
/* system model: IBM-AT */
- write8(0xffffe, 0xfc);
+ write8(0xfc, (void *)(uintptr_t)(0xffffe));
}
static int (*intXX_handler[256])(void) = { NULL };
diff --git a/src/drivers/ati/ragexl/atyfb.h b/src/drivers/ati/ragexl/atyfb.h
index 94f31fe..8c6848b 100644
--- a/src/drivers/ati/ragexl/atyfb.h
+++ b/src/drivers/ati/ragexl/atyfb.h
@@ -211,7 +211,7 @@ static inline u32 aty_ld_le32(int regindex,
#ifdef ATARI
return in_le32((volatile u32 *)(info->ati_regbase+regindex));
#else
- return read32 (info->ati_regbase + regindex);
+ return read32((void *)(uintptr_t)(info->ati_regbase + regindex));
#endif
}
@@ -225,7 +225,7 @@ static inline void aty_st_le32(int regindex, u32 val,
#ifdef ATARI
out_le32 (info->ati_regbase+regindex, val);
#else
- write32 (info->ati_regbase + regindex, val);
+ write32(val, (void *)(uintptr_t)(info->ati_regbase + regindex));
#endif
}
@@ -239,7 +239,7 @@ static inline u16 aty_ld_le16(int regindex,
#if defined(__mc68000__)
return le16_to_cpu(*((volatile u16 *)(info->ati_regbase+regindex)));
#else
- return read16 (info->ati_regbase + regindex);
+ return read16((void *)(uintptr_t)(info->ati_regbase + regindex));
#endif
}
@@ -253,7 +253,7 @@ static inline void aty_st_le16(int regindex, u16 val,
#if defined(__mc68000__)
*((volatile u16 *)(info->ati_regbase+regindex)) = cpu_to_le16(val);
#else
- write16 (info->ati_regbase + regindex, val);
+ write16(val, (void *)(uintptr_t)(info->ati_regbase + regindex));
#endif
}
@@ -267,7 +267,7 @@ static inline u8 aty_ld_8(int regindex,
#ifdef ATARI
return in_8 (info->ati_regbase + regindex);
#else
- return read8 (info->ati_regbase + regindex);
+ return read8((void *)(uintptr_t)(info->ati_regbase + regindex));
#endif
}
@@ -281,7 +281,7 @@ static inline void aty_st_8(int regindex, u8 val,
#ifdef ATARI
out_8 (info->ati_regbase + regindex, val);
#else
- write8 (info->ati_regbase + regindex, val);
+ write8(val, (void *)(uintptr_t)(info->ati_regbase + regindex));
#endif
}
diff --git a/src/drivers/ati/ragexl/xlinit.c b/src/drivers/ati/ragexl/xlinit.c
index 41cea72..c2fc2df 100644
--- a/src/drivers/ati/ragexl/xlinit.c
+++ b/src/drivers/ati/ragexl/xlinit.c
@@ -1439,9 +1439,9 @@ static int atyfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
scale = (M64_HAS(INTEGRATED) && info->default_par.crtc.bpp == 16) ? 3 : 0;
#endif
write8(&info->aty_cmap_regs->windex, regno << scale)
- write8(&info->aty_cmap_regs->lut, red);
- write8(&info->aty_cmap_regs->lut, green);
- write8(&info->aty_cmap_regs->lut, blue);
+ write8(red, (void *)(uintptr_t)(&info->aty_cmap_regs->lut));
+ write8(green, (void *)(uintptr_t)(&info->aty_cmap_regs->lut));
+ write8(blue, (void *)(uintptr_t)(&info->aty_cmap_regs->lut));
return 0;
}
diff --git a/src/drivers/intel/gma/edid.c b/src/drivers/intel/gma/edid.c
index 91ad742..39c67ac 100644
--- a/src/drivers/intel/gma/edid.c
+++ b/src/drivers/intel/gma/edid.c
@@ -31,7 +31,7 @@ static void wait_rdy(u32 mmio)
unsigned try = 100;
while (try--) {
- if (read32(mmio + 8) & (1 << 11))
+ if (read32((void *)(uintptr_t)(mmio + 8)) & (1 << 11))
return;
udelay(10);
}
@@ -46,30 +46,30 @@ void intel_gmbus_read_edid(u32 mmio, u8 bus, u8 slave, u8 *edid, u32 edid_size)
wait_rdy(mmio);
/* 100 KHz, hold 0ns, */
- write32(mmio + 4 * 0, bus);
+ write32(bus, (void *)(uintptr_t)(mmio + 4 * 0));
wait_rdy(mmio);
/* Ensure index bits are disabled. */
- write32(mmio + 4 * 5, 0);
- write32(mmio + 4 * 1, 0x46000000 | (slave << 1));
+ write32(0, (void *)(uintptr_t)(mmio + 4 * 5));
+ write32(0x46000000 | (slave << 1), (void *)(uintptr_t)(mmio + 4 * 1));
wait_rdy(mmio);
/* Ensure index bits are disabled. */
- write32(mmio + 4 * 5, 0);
- write32(mmio + 4 * 1, 0x4a000001 | (slave << 1)
- | (edid_size << 16));
+ write32(0, (void *)(uintptr_t)(mmio + 4 * 5));
+ write32(0x4a000001 | (slave << 1) | (edid_size << 16),
+ (void *)(uintptr_t)(mmio + 4 * 1));
for (i = 0; i < edid_size / 4; i++) {
u32 reg32;
wait_rdy(mmio);
- reg32 = read32(mmio + 4 * 3);
+ reg32 = read32((void *)(uintptr_t)(mmio + 4 * 3));
edid[4 * i] = reg32 & 0xff;
edid[4 * i + 1] = (reg32 >> 8) & 0xff;
edid[4 * i + 2] = (reg32 >> 16) & 0xff;
edid[4 * i + 3] = (reg32 >> 24) & 0xff;
}
wait_rdy(mmio);
- write32(mmio + 4 * 1, 0x4a800000 | (slave << 1));
+ write32(0x4a800000 | (slave << 1), (void *)(uintptr_t)(mmio + 4 * 1));
wait_rdy(mmio);
- write32(mmio + 4 * 0, 0x48000000);
- write32(mmio + 4 * 2, 0x00008000);
+ write32(0x48000000, (void *)(uintptr_t)(mmio + 4 * 0));
+ write32(0x00008000, (void *)(uintptr_t)(mmio + 4 * 2));
printk (BIOS_SPEW, "EDID:\n");
for (i = 0; i < 128; i++) {
diff --git a/src/drivers/uart/oxpcie.c b/src/drivers/uart/oxpcie.c
index 76119d2..b54887b 100644
--- a/src/drivers/uart/oxpcie.c
+++ b/src/drivers/uart/oxpcie.c
@@ -36,9 +36,10 @@ static void oxford_oxpcie_enable(device_t dev)
}
printk(BIOS_DEBUG, "OXPCIe952: Class=%x Revision ID=%x\n",
- (read32(res->base) >> 8), (read32(res->base) & 0xff));
+ (read32((void *)(uintptr_t)(res->base)) >> 8),
+ (read32((void *)(uintptr_t)(res->base)) & 0xff));
printk(BIOS_DEBUG, "OXPCIe952: %d UARTs detected.\n",
- (read32(res->base + 4) & 3));
+ (read32((void *)(uintptr_t)(res->base + 4)) & 3));
printk(BIOS_DEBUG, "OXPCIe952: UART BAR: 0x%x\n", (u32)res->base);
}
diff --git a/src/drivers/uart/uart8250mem.c b/src/drivers/uart/uart8250mem.c
index 5fbbeec..2b39cfc 100644
--- a/src/drivers/uart/uart8250mem.c
+++ b/src/drivers/uart/uart8250mem.c
@@ -36,12 +36,12 @@
static uint8_t uart8250_read(void *base, uint8_t reg)
{
- return read8((uintptr_t) (base + reg));
+ return read8((void *)(uintptr_t)((uintptr_t)(base + reg)));
}
static void uart8250_write(void *base, uint8_t reg, uint8_t data)
{
- write8((uintptr_t) (base + reg), data);
+ write8(data, (void *)(uintptr_t)((uintptr_t)(base + reg)));
}
static int uart8250_mem_can_tx_byte(void *base)
diff --git a/src/drivers/usb/ehci_debug.c b/src/drivers/usb/ehci_debug.c
index 83c23a3..08cb941 100644
--- a/src/drivers/usb/ehci_debug.c
+++ b/src/drivers/usb/ehci_debug.c
@@ -78,7 +78,7 @@ static int dbgp_wait_until_complete(struct ehci_dbg_port *ehci_debug)
int loop = 0;
do {
- ctrl = read32((unsigned long)&ehci_debug->control);
+ ctrl = read32((void *)(uintptr_t)((unsigned long)&ehci_debug->control));
/* Stop when the transaction is finished */
if (ctrl & DBGP_DONE)
break;
@@ -92,7 +92,8 @@ static int dbgp_wait_until_complete(struct ehci_dbg_port *ehci_debug)
/* Now that we have observed the completed transaction,
* clear the done bit.
*/
- write32((unsigned long)&ehci_debug->control, ctrl | DBGP_DONE);
+ write32(ctrl | DBGP_DONE,
+ (void *)(uintptr_t)((unsigned long)&ehci_debug->control));
return (ctrl & DBGP_ERROR) ? -DBGP_ERRCODE(ctrl) : DBGP_LEN(ctrl);
}
@@ -122,10 +123,11 @@ host_retry:
if (loop == 1 || host_retries > 1)
dprintk(BIOS_SPEW, "dbgp: start (@ %3d,%d) ctrl=%08x\n",
loop, host_retries, ctrl | DBGP_GO);
- write32((unsigned long)&ehci_debug->control, ctrl | DBGP_GO);
+ write32(ctrl | DBGP_GO,
+ (void *)(uintptr_t)((unsigned long)&ehci_debug->control));
ret = dbgp_wait_until_complete(ehci_debug);
- rd_ctrl = read32((unsigned long)&ehci_debug->control);
- rd_pids = read32((unsigned long)&ehci_debug->pids);
+ rd_ctrl = read32((void *)(uintptr_t)((unsigned long)&ehci_debug->control));
+ rd_pids = read32((void *)(uintptr_t)((unsigned long)&ehci_debug->pids));
if (rd_ctrl != ctrl_prev || rd_pids != pids_prev || (ret<0)) {
ctrl_prev = rd_ctrl;
@@ -184,8 +186,8 @@ static void dbgp_set_data(struct ehci_dbg_port *ehci_debug, const void *buf, int
lo |= bytes[i] << (8*i);
for (; i < 8 && i < size; i++)
hi |= bytes[i] << (8*(i - 4));
- write32((unsigned long)&ehci_debug->data03, lo);
- write32((unsigned long)&ehci_debug->data47, hi);
+ write32(lo, (void *)(uintptr_t)((unsigned long)&ehci_debug->data03));
+ write32(hi, (void *)(uintptr_t)((unsigned long)&ehci_debug->data47));
}
static void dbgp_get_data(struct ehci_dbg_port *ehci_debug, void *buf, int size)
@@ -194,8 +196,8 @@ static void dbgp_get_data(struct ehci_dbg_port *ehci_debug, void *buf, int size)
u32 lo, hi;
int i;
- lo = read32((unsigned long)&ehci_debug->data03);
- hi = read32((unsigned long)&ehci_debug->data47);
+ lo = read32((void *)(uintptr_t)((unsigned long)&ehci_debug->data03));
+ hi = read32((void *)(uintptr_t)((unsigned long)&ehci_debug->data47));
for (i = 0; i < 4 && i < size; i++)
bytes[i] = (lo >> (8*i)) & 0xff;
for (; i < 8 && i < size; i++)
@@ -205,9 +207,9 @@ static void dbgp_get_data(struct ehci_dbg_port *ehci_debug, void *buf, int size)
#if CONFIG_DEBUG_USBDEBUG
static void dbgp_print_data(struct ehci_dbg_port *ehci_debug)
{
- u32 ctrl = read32((unsigned long)&ehci_debug->control);
- u32 lo = read32((unsigned long)&ehci_debug->data03);
- u32 hi = read32((unsigned long)&ehci_debug->data47);
+ u32 ctrl = read32((void *)(uintptr_t)((unsigned long)&ehci_debug->control));
+ u32 lo = read32((void *)(uintptr_t)((unsigned long)&ehci_debug->data03));
+ u32 hi = read32((void *)(uintptr_t)((unsigned long)&ehci_debug->data47));
int len = DBGP_LEN(ctrl);
if (len) {
int i;
@@ -233,13 +235,14 @@ static int dbgp_bulk_write(struct ehci_dbg_port *ehci_debug, struct dbgp_pipe *p
addr = DBGP_EPADDR(pipe->devnum, pipe->endpoint);
pids = DBGP_PID_SET(pipe->pid, USB_PID_OUT);
- ctrl = read32((unsigned long)&ehci_debug->control);
+ ctrl = read32((void *)(uintptr_t)((unsigned long)&ehci_debug->control));
ctrl = DBGP_LEN_UPDATE(ctrl, size);
ctrl |= DBGP_OUT;
dbgp_set_data(ehci_debug, bytes, size);
- write32((unsigned long)&ehci_debug->address, addr);
- write32((unsigned long)&ehci_debug->pids, pids);
+ write32(addr,
+ (void *)(uintptr_t)((unsigned long)&ehci_debug->address));
+ write32(pids, (void *)(uintptr_t)((unsigned long)&ehci_debug->pids));
ret = dbgp_wait_until_done(ehci_debug, pipe, ctrl, pipe->timeout);
@@ -264,12 +267,13 @@ static int dbgp_bulk_read(struct ehci_dbg_port *ehci_debug, struct dbgp_pipe *pi
addr = DBGP_EPADDR(pipe->devnum, pipe->endpoint);
pids = DBGP_PID_SET(pipe->pid, USB_PID_IN);
- ctrl = read32((unsigned long)&ehci_debug->control);
+ ctrl = read32((void *)(uintptr_t)((unsigned long)&ehci_debug->control));
ctrl = DBGP_LEN_UPDATE(ctrl, size);
ctrl &= ~DBGP_OUT;
- write32((unsigned long)&ehci_debug->address, addr);
- write32((unsigned long)&ehci_debug->pids, pids);
+ write32(addr,
+ (void *)(uintptr_t)((unsigned long)&ehci_debug->address));
+ write32(pids, (void *)(uintptr_t)((unsigned long)&ehci_debug->pids));
ret = dbgp_wait_until_done(ehci_debug, pipe, ctrl, pipe->timeout);
if (ret < 0)
return ret;
@@ -324,14 +328,15 @@ int dbgp_control_msg(struct ehci_dbg_port *ehci_debug, unsigned devnum, int requ
addr = DBGP_EPADDR(pipe->devnum, pipe->endpoint);
pids = DBGP_PID_SET(pipe->pid, USB_PID_SETUP);
- ctrl = read32((unsigned long)&ehci_debug->control);
+ ctrl = read32((void *)(uintptr_t)((unsigned long)&ehci_debug->control));
ctrl = DBGP_LEN_UPDATE(ctrl, sizeof(req));
ctrl |= DBGP_OUT;
/* Setup stage */
dbgp_set_data(ehci_debug, &req, sizeof(req));
- write32((unsigned long)&ehci_debug->address, addr);
- write32((unsigned long)&ehci_debug->pids, pids);
+ write32(addr,
+ (void *)(uintptr_t)((unsigned long)&ehci_debug->address));
+ write32(pids, (void *)(uintptr_t)((unsigned long)&ehci_debug->pids));
ret = dbgp_wait_until_done(ehci_debug, pipe, ctrl, 1);
if (ret < 0)
return ret;
@@ -344,7 +349,7 @@ int dbgp_control_msg(struct ehci_dbg_port *ehci_debug, unsigned devnum, int requ
/* Status stage in opposite direction */
pipe->pid = USB_PID_DATA1;
- ctrl = read32((unsigned long)&ehci_debug->control);
+ ctrl = read32((void *)(uintptr_t)((unsigned long)&ehci_debug->control));
ctrl = DBGP_LEN_UPDATE(ctrl, 0);
if (read) {
pids = DBGP_PID_SET(pipe->pid, USB_PID_OUT);
@@ -354,7 +359,7 @@ int dbgp_control_msg(struct ehci_dbg_port *ehci_debug, unsigned devnum, int requ
ctrl &= ~DBGP_OUT;
}
- write32((unsigned long)&ehci_debug->pids, pids);
+ write32(pids, (void *)(uintptr_t)((unsigned long)&ehci_debug->pids));
ret2 = dbgp_wait_until_done(ehci_debug, pipe, ctrl, pipe->timeout);
if (ret2 < 0)
return ret2;
@@ -368,21 +373,22 @@ static int ehci_reset_port(struct ehci_regs *ehci_regs, int port)
int loop;
/* Reset the usb debug port */
- portsc = read32((unsigned long)&ehci_regs->port_status[port - 1]);
+ portsc = read32((void *)(uintptr_t)((unsigned long)&ehci_regs->port_status[port - 1]));
portsc &= ~PORT_PE;
portsc |= PORT_RESET;
- write32((unsigned long)&ehci_regs->port_status[port - 1], portsc);
+ write32(portsc,
+ (void *)(uintptr_t)((unsigned long)&ehci_regs->port_status[port - 1]));
dbgp_mdelay(HUB_ROOT_RESET_TIME);
- portsc = read32((unsigned long)&ehci_regs->port_status[port - 1]);
- write32((unsigned long)&ehci_regs->port_status[port - 1],
- portsc & ~(PORT_RWC_BITS | PORT_RESET));
+ portsc = read32((void *)(uintptr_t)((unsigned long)&ehci_regs->port_status[port - 1]));
+ write32(portsc & ~(PORT_RWC_BITS | PORT_RESET),
+ (void *)(uintptr_t)((unsigned long)&ehci_regs->port_status[port - 1]));
loop = 100;
do {
dbgp_mdelay(1);
- portsc = read32((unsigned long)&ehci_regs->port_status[port - 1]);
+ portsc = read32((void *)(uintptr_t)((unsigned long)&ehci_regs->port_status[port - 1]));
} while ((portsc & PORT_RESET) && (--loop > 0));
/* Device went away? */
@@ -407,7 +413,7 @@ static int ehci_wait_for_port(struct ehci_regs *ehci_regs, int port)
for (reps = 0; reps < 3; reps++) {
dbgp_mdelay(100);
- status = read32((unsigned long)&ehci_regs->status);
+ status = read32((void *)(uintptr_t)((unsigned long)&ehci_regs->status));
if (status & STS_PCD) {
ret = ehci_reset_port(ehci_regs, port);
if (ret == 0)
@@ -440,7 +446,7 @@ static int usbdebug_init_(unsigned ehci_bar, unsigned offset, struct ehci_debug_
ehci_caps = (struct ehci_caps *)ehci_bar;
ehci_regs = (struct ehci_regs *)(ehci_bar +
- HC_LENGTH(read32((unsigned long)&ehci_caps->hc_capbase)));
+ HC_LENGTH(read32((void *)(uintptr_t)((unsigned long)&ehci_caps->hc_capbase))));
struct ehci_dbg_port *ehci_debug = info->ehci_debug;
@@ -453,7 +459,7 @@ try_next_time:
port_map_tried = 0;
try_next_port:
- hcs_params = read32((unsigned long)&ehci_caps->hcs_params);
+ hcs_params = read32((void *)(uintptr_t)((unsigned long)&ehci_caps->hcs_params));
debug_port = HCS_DEBUG_PORT(hcs_params);
n_ports = HCS_N_PORTS(hcs_params);
@@ -461,7 +467,7 @@ try_next_port:
dprintk(BIOS_INFO, "n_ports: %d\n", n_ports);
for (i = 1; i <= n_ports; i++) {
- portsc = read32((unsigned long)&ehci_regs->port_status[i-1]);
+ portsc = read32((void *)(uintptr_t)((unsigned long)&ehci_regs->port_status[i - 1]));
dprintk(BIOS_INFO, "PORTSC #%d: %08x\n", i, portsc);
}
@@ -474,15 +480,16 @@ try_next_port:
}
/* Wait until the controller is halted */
- status = read32((unsigned long)&ehci_regs->status);
+ status = read32((void *)(uintptr_t)((unsigned long)&ehci_regs->status));
if (!(status & STS_HALT)) {
- cmd = read32((unsigned long)&ehci_regs->command);
+ cmd = read32((void *)(uintptr_t)((unsigned long)&ehci_regs->command));
cmd &= ~CMD_RUN;
- write32((unsigned long)&ehci_regs->command, cmd);
+ write32(cmd,
+ (void *)(uintptr_t)((unsigned long)&ehci_regs->command));
loop = 100;
do {
dbgp_mdelay(10);
- status = read32((unsigned long)&ehci_regs->status);
+ status = read32((void *)(uintptr_t)((unsigned long)&ehci_regs->status));
} while (!(status & STS_HALT) && (--loop > 0));
if (status & STS_HALT)
dprintk(BIOS_INFO, "EHCI controller halted successfully.\n");
@@ -492,12 +499,12 @@ try_next_port:
loop = 100;
/* Reset the EHCI controller */
- cmd = read32((unsigned long)&ehci_regs->command);
+ cmd = read32((void *)(uintptr_t)((unsigned long)&ehci_regs->command));
cmd |= CMD_RESET;
- write32((unsigned long)&ehci_regs->command, cmd);
+ write32(cmd, (void *)(uintptr_t)((unsigned long)&ehci_regs->command));
do {
dbgp_mdelay(10);
- cmd = read32((unsigned long)&ehci_regs->command);
+ cmd = read32((void *)(uintptr_t)((unsigned long)&ehci_regs->command));
} while ((cmd & CMD_RESET) && (--loop > 0));
if(!loop) {
@@ -509,25 +516,27 @@ try_next_port:
}
/* Claim ownership, but do not enable yet */
- ctrl = read32((unsigned long)&ehci_debug->control);
+ ctrl = read32((void *)(uintptr_t)((unsigned long)&ehci_debug->control));
ctrl |= DBGP_OWNER;
ctrl &= ~(DBGP_ENABLED | DBGP_INUSE);
- write32((unsigned long)&ehci_debug->control, ctrl);
+ write32(ctrl,
+ (void *)(uintptr_t)((unsigned long)&ehci_debug->control));
/* Start EHCI controller */
- cmd = read32((unsigned long)&ehci_regs->command);
+ cmd = read32((void *)(uintptr_t)((unsigned long)&ehci_regs->command));
cmd &= ~(CMD_LRESET | CMD_IAAD | CMD_PSE | CMD_ASE | CMD_RESET);
cmd |= CMD_RUN;
- write32((unsigned long)&ehci_regs->command, cmd);
+ write32(cmd, (void *)(uintptr_t)((unsigned long)&ehci_regs->command));
/* Ensure everything is routed to the EHCI */
- write32((unsigned long)&ehci_regs->configured_flag, FLAG_CF);
+ write32(FLAG_CF,
+ (void *)(uintptr_t)((unsigned long)&ehci_regs->configured_flag));
/* Wait until the controller is no longer halted */
loop = 10;
do {
dbgp_mdelay(10);
- status = read32((unsigned long)&ehci_regs->status);
+ status = read32((void *)(uintptr_t)((unsigned long)&ehci_regs->status));
} while ((status & STS_HALT) && (--loop > 0));
if(!loop) {
@@ -546,13 +555,15 @@ try_next_port:
/* Enable the debug port */
- ctrl = read32((unsigned long)&ehci_debug->control);
+ ctrl = read32((void *)(uintptr_t)((unsigned long)&ehci_debug->control));
ctrl |= DBGP_CLAIM;
- write32((unsigned long)&ehci_debug->control, ctrl);
- ctrl = read32((unsigned long)&ehci_debug->control);
+ write32(ctrl,
+ (void *)(uintptr_t)((unsigned long)&ehci_debug->control));
+ ctrl = read32((void *)(uintptr_t)((unsigned long)&ehci_debug->control));
if ((ctrl & DBGP_CLAIM) != DBGP_CLAIM) {
dprintk(BIOS_INFO, "No device in EHCI debug port.\n");
- write32((unsigned long)&ehci_debug->control, ctrl & ~DBGP_CLAIM);
+ write32(ctrl & ~DBGP_CLAIM,
+ (void *)(uintptr_t)((unsigned long)&ehci_debug->control));
ret = -4;
goto err;
}
@@ -577,9 +588,10 @@ try_next_port:
return 0;
err:
/* Things didn't work so remove my claim */
- ctrl = read32((unsigned long)&ehci_debug->control);
+ ctrl = read32((void *)(uintptr_t)((unsigned long)&ehci_debug->control));
ctrl &= ~(DBGP_CLAIM | DBGP_OUT);
- write32((unsigned long)(unsigned long)&ehci_debug->control, ctrl);
+ write32(ctrl,
+ (void *)(uintptr_t)((unsigned long)(unsigned long)&ehci_debug->control));
//return ret;
next_debug_port:
diff --git a/src/drivers/usb/pci_ehci.c b/src/drivers/usb/pci_ehci.c
index 8fe78b1..ffffaf7 100644
--- a/src/drivers/usb/pci_ehci.c
+++ b/src/drivers/usb/pci_ehci.c
@@ -111,5 +111,5 @@ unsigned long pci_ehci_base_regs(pci_devfn_t sdev)
device_t dev = dev_find_slot(PCI_DEV2SEGBUS(sdev), PCI_DEV2DEVFN(sdev));
unsigned long base = pci_read_config32(dev, EHCI_BAR_INDEX) & ~0x0f;
#endif
- return base + HC_LENGTH(read32(base));
+ return base + HC_LENGTH(read32((void *)(uintptr_t)(base)));
}
diff --git a/src/lib/reg_script.c b/src/lib/reg_script.c
index 647723b..7b927a2 100644
--- a/src/lib/reg_script.c
+++ b/src/lib/reg_script.c
@@ -155,11 +155,11 @@ static uint32_t reg_script_read_mmio(struct reg_script_context *ctx)
switch (step->size) {
case REG_SCRIPT_SIZE_8:
- return read8(step->reg);
+ return read8((void *)(uintptr_t)(step->reg));
case REG_SCRIPT_SIZE_16:
- return read16(step->reg);
+ return read16((void *)(uintptr_t)(step->reg));
case REG_SCRIPT_SIZE_32:
- return read32(step->reg);
+ return read32((void *)(uintptr_t)(step->reg));
}
return 0;
}
@@ -170,13 +170,13 @@ static void reg_script_write_mmio(struct reg_script_context *ctx)
switch (step->size) {
case REG_SCRIPT_SIZE_8:
- write8(step->reg, step->value);
+ write8(step->value, (void *)(uintptr_t)(step->reg));
break;
case REG_SCRIPT_SIZE_16:
- write16(step->reg, step->value);
+ write16(step->value, (void *)(uintptr_t)(step->reg));
break;
case REG_SCRIPT_SIZE_32:
- write32(step->reg, step->value);
+ write32(step->value, (void *)(uintptr_t)(step->reg));
break;
}
}
diff --git a/src/mainboard/amd/torpedo/mptable.c b/src/mainboard/amd/torpedo/mptable.c
index 477d97a..e3c43e4 100644
--- a/src/mainboard/amd/torpedo/mptable.c
+++ b/src/mainboard/amd/torpedo/mptable.c
@@ -113,8 +113,8 @@ static void *smp_write_config_table(void *v)
ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword);
dword &= 0xFFFFFFF0;
/* Set IO APIC ID onto IO_APIC_ID */
- write32 (dword, 0x00);
- write32 (dword + 0x10, IO_APIC_ID << 24);
+ write32(0x00, (void *)(uintptr_t)(dword));
+ write32(IO_APIC_ID << 24, (void *)(uintptr_t)(dword + 0x10));
apicid_sb900 = IO_APIC_ID;
smp_write_ioapic(mc, apicid_sb900, 0x21, dword);
diff --git a/src/mainboard/asus/dsbf/romstage.c b/src/mainboard/asus/dsbf/romstage.c
index fbd0848..ddbb81f 100644
--- a/src/mainboard/asus/dsbf/romstage.c
+++ b/src/mainboard/asus/dsbf/romstage.c
@@ -52,22 +52,22 @@ static void early_config(void)
pci_write_config32(PCI_DEV(0, 0x1F, 0), RCBA, DEFAULT_RCBA | 1);
/* Disable watchdog */
- gcs = read32(DEFAULT_RCBA + RCBA_GCS);
+ gcs = read32((void *)(uintptr_t)(DEFAULT_RCBA + RCBA_GCS));
gcs |= (1 << 5); /* No reset */
- write32(DEFAULT_RCBA + RCBA_GCS, gcs);
+ write32(gcs, (void *)(uintptr_t)(DEFAULT_RCBA + RCBA_GCS));
/* Configure PCIe port B as 4x */
- rpc = read32(DEFAULT_RCBA + RCBA_RPC);
+ rpc = read32((void *)(uintptr_t)(DEFAULT_RCBA + RCBA_RPC));
rpc |= (3 << 0);
- write32(DEFAULT_RCBA + RCBA_RPC, rpc);
+ write32(rpc, (void *)(uintptr_t)(DEFAULT_RCBA + RCBA_RPC));
/* Disable Modem, Audio, PCIe ports 2/3/4 */
- fd = read32(DEFAULT_RCBA + RCBA_FD);
+ fd = read32((void *)(uintptr_t)(DEFAULT_RCBA + RCBA_FD));
fd |= (1 << 19) | (1 << 18) | (1 << 17) | (1 << 6) | (1 << 5);
- write32(DEFAULT_RCBA + RCBA_FD, fd);
+ write32(fd, (void *)(uintptr_t)(DEFAULT_RCBA + RCBA_FD));
/* Enable HPET */
- write32(DEFAULT_RCBA + RCBA_HPTC, (1 << 7));
+ write32((1 << 7), (void *)(uintptr_t)(DEFAULT_RCBA + RCBA_HPTC));
/* Setup sata mode */
pci_write_config8(PCI_DEV(0, 0x1F, 2), SATA_MAP, 0x40);
diff --git a/src/mainboard/intel/eagleheights/debug.c b/src/mainboard/intel/eagleheights/debug.c
index d2c3d58..d4a20a0 100644
--- a/src/mainboard/intel/eagleheights/debug.c
+++ b/src/mainboard/intel/eagleheights/debug.c
@@ -153,7 +153,7 @@ static inline void dump_bar14(unsigned dev)
print_debug_hex16(i);
print_debug_char(' ');
}
- print_debug_hex32(read32(bar + i));
+ print_debug_hex32(read32((void *)(uintptr_t)(bar + i)));
print_debug_char(' ');
}
print_debug("\n");
diff --git a/src/mainboard/intel/eagleheights/mptable.c b/src/mainboard/intel/eagleheights/mptable.c
index 809feec..4335445 100644
--- a/src/mainboard/intel/eagleheights/mptable.c
+++ b/src/mainboard/intel/eagleheights/mptable.c
@@ -145,10 +145,10 @@ static void *smp_write_config_table(void *v)
/* PCIe Port B
*/
for(i = 0; i < 4; i++) {
- pin = (read32(rcba + RCBA_D28IP) >> (i * 4)) & 0x0F;
+ pin = (read32((void *)(uintptr_t)(rcba + RCBA_D28IP)) >> (i * 4)) & 0x0F;
if(pin > 0) {
pin -= 1;
- route = PIRQ_A + ((read16(rcba + RCBA_D28IR) >> (pin * 4)) & 0x07);
+ route = PIRQ_A + ((read16((void *)(uintptr_t)(rcba + RCBA_D28IR)) >> (pin * 4)) & 0x07);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_chipset, PCI_IRQ(28, pin), IO_APIC0, route);
}
}
@@ -156,20 +156,20 @@ static void *smp_write_config_table(void *v)
/* USB 1.1 : device 29, function 0, 1
*/
for(i = 0; i < 2; i++) {
- pin = (read32(rcba + RCBA_D29IP) >> (i * 4)) & 0x0F;
+ pin = (read32((void *)(uintptr_t)(rcba + RCBA_D29IP)) >> (i * 4)) & 0x0F;
if(pin > 0) {
pin -= 1;
- route = PIRQ_A + ((read16(rcba + RCBA_D29IR) >> (pin * 4)) & 0x07);
+ route = PIRQ_A + ((read16((void *)(uintptr_t)(rcba + RCBA_D29IR)) >> (pin * 4)) & 0x07);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_chipset, PCI_IRQ(29, pin), IO_APIC0, route);
}
}
/* USB 2.0 : device 29, function 7
*/
- pin = (read32(rcba + RCBA_D29IP) >> (7 * 4)) & 0x0F;
+ pin = (read32((void *)(uintptr_t)(rcba + RCBA_D29IP)) >> (7 * 4)) & 0x0F;
if(pin > 0) {
pin -= 1;
- route = PIRQ_A + ((read16(rcba + RCBA_D29IR) >> (pin * 4)) & 0x07);
+ route = PIRQ_A + ((read16((void *)(uintptr_t)(rcba + RCBA_D29IR)) >> (pin * 4)) & 0x07);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_chipset, PCI_IRQ(29, pin), IO_APIC0, route);
}
@@ -178,10 +178,10 @@ static void *smp_write_config_table(void *v)
Performance counters : device 31 function 4
*/
for(i = 2; i < 5; i++) {
- pin = (read32(rcba + RCBA_D31IP) >> (i * 4)) & 0x0F;
+ pin = (read32((void *)(uintptr_t)(rcba + RCBA_D31IP)) >> (i * 4)) & 0x0F;
if(pin > 0) {
pin -= 1;
- route = PIRQ_A + ((read16(rcba + RCBA_D31IR) >> (pin * 4)) & 0x07);
+ route = PIRQ_A + ((read16((void *)(uintptr_t)(rcba + RCBA_D31IR)) >> (pin * 4)) & 0x07);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_chipset, PCI_IRQ(31, pin), IO_APIC0, route);
}
}
diff --git a/src/mainboard/intel/eagleheights/romstage.c b/src/mainboard/intel/eagleheights/romstage.c
index c03c7d7..5654c5b 100644
--- a/src/mainboard/intel/eagleheights/romstage.c
+++ b/src/mainboard/intel/eagleheights/romstage.c
@@ -84,22 +84,22 @@ static void early_config(void)
pci_write_config32(PCI_DEV(0, 0x1F, 0), RCBA, DEFAULT_RCBA | 1);
/* Disable watchdog */
- gcs = read32(DEFAULT_RCBA + RCBA_GCS);
+ gcs = read32((void *)(uintptr_t)(DEFAULT_RCBA + RCBA_GCS));
gcs |= (1 << 5); /* No reset */
- write32(DEFAULT_RCBA + RCBA_GCS, gcs);
+ write32(gcs, (void *)(uintptr_t)(DEFAULT_RCBA + RCBA_GCS));
/* Configure PCIe port B as 4x */
- rpc = read32(DEFAULT_RCBA + RCBA_RPC);
+ rpc = read32((void *)(uintptr_t)(DEFAULT_RCBA + RCBA_RPC));
rpc |= (3 << 0);
- write32(DEFAULT_RCBA + RCBA_RPC, rpc);
+ write32(rpc, (void *)(uintptr_t)(DEFAULT_RCBA + RCBA_RPC));
/* Disable Modem, Audio, PCIe ports 2/3/4 */
- fd = read32(DEFAULT_RCBA + RCBA_FD);
+ fd = read32((void *)(uintptr_t)(DEFAULT_RCBA + RCBA_FD));
fd |= (1 << 19) | (1 << 18) | (1 << 17) | (1 << 6) | (1 << 5);
- write32(DEFAULT_RCBA + RCBA_FD, fd);
+ write32(fd, (void *)(uintptr_t)(DEFAULT_RCBA + RCBA_FD));
/* Enable HPET */
- write32(DEFAULT_RCBA + RCBA_HPTC, (1 << 7));
+ write32((1 << 7), (void *)(uintptr_t)(DEFAULT_RCBA + RCBA_HPTC));
/* Improve interrupt routing
* D31:F2 SATA INTB# -> PIRQD
@@ -111,10 +111,10 @@ static void early_config(void)
* D28:F0 PCIe Port 1 INTA# -> PIRQE
*/
- write16(DEFAULT_RCBA + RCBA_D31IR, 0x0230);
- write16(DEFAULT_RCBA + RCBA_D30IR, 0x3210);
- write16(DEFAULT_RCBA + RCBA_D29IR, 0x3237);
- write16(DEFAULT_RCBA + RCBA_D28IR, 0x3214);
+ write16(0x0230, (void *)(uintptr_t)(DEFAULT_RCBA + RCBA_D31IR));
+ write16(0x3210, (void *)(uintptr_t)(DEFAULT_RCBA + RCBA_D30IR));
+ write16(0x3237, (void *)(uintptr_t)(DEFAULT_RCBA + RCBA_D29IR));
+ write16(0x3214, (void *)(uintptr_t)(DEFAULT_RCBA + RCBA_D28IR));
/* Setup sata mode */
pci_write_config8(PCI_DEV(0, 0x1F, 2), SATA_MAP, (SATA_MODE_AHCI << 6) | (0 << 0));
diff --git a/src/mainboard/intel/jarrell/debug.c b/src/mainboard/intel/jarrell/debug.c
index b92a75d..b58bf2a 100644
--- a/src/mainboard/intel/jarrell/debug.c
+++ b/src/mainboard/intel/jarrell/debug.c
@@ -131,7 +131,7 @@ static void dump_bar14(unsigned dev)
print_debug_hex16(i);
print_debug_char(' ');
}
- print_debug_hex32(read32(bar + i));
+ print_debug_hex32(read32((void *)(uintptr_t)(bar + i)));
print_debug_char(' ');
}
print_debug("\n");
diff --git a/src/mainboard/intel/mohonpeak/romstage.c b/src/mainboard/intel/mohonpeak/romstage.c
index b1fb995..2b490e8 100644
--- a/src/mainboard/intel/mohonpeak/romstage.c
+++ b/src/mainboard/intel/mohonpeak/romstage.c
@@ -40,16 +40,16 @@ static void interrupt_routing_config(void)
* PIRQ_A maps to IRQ 16 ... PIRQ_H maps tp IRQ 23.
* This should match devicetree and the ACPI IRQ routing/
*/
- write32(ilb_base + ILB_ACTL, 0x0000); /* ACTL bit 2:0 SCIS IRQ9 */
- write16(ilb_base + ILB_IR01, 0x3210); /* IR01h IR(ABCD) - PIRQ(ABCD) */
- write16(ilb_base + ILB_IR02, 0x3210); /* IR02h IR(ABCD) - PIRQ(ABCD) */
- write16(ilb_base + ILB_IR03, 0x7654); /* IR03h IR(ABCD) - PIRQ(EFGH) */
- write16(ilb_base + ILB_IR04, 0x7654); /* IR04h IR(ABCD) - PIRQ(EFGH) */
- write16(ilb_base + ILB_IR20, 0x7654); /* IR14h IR(ABCD) - PIRQ(EFGH) */
- write16(ilb_base + ILB_IR22, 0x0007); /* IR16h IR(A) - PIRQ(H) */
- write16(ilb_base + ILB_IR23, 0x0003); /* IR17h IR(A) - PIRQ(D) */
- write16(ilb_base + ILB_IR24, 0x0003); /* IR18h IR(A) - PIRQ(D) */
- write16(ilb_base + ILB_IR31, 0x0020); /* IR1Fh IR(B) - PIRQ(C) */
+ write32(0x0000, (void *)(uintptr_t)(ilb_base + ILB_ACTL)); /* ACTL bit 2:0 SCIS IRQ9 */
+ write16(0x3210, (void *)(uintptr_t)(ilb_base + ILB_IR01)); /* IR01h IR(ABCD) - PIRQ(ABCD) */
+ write16(0x3210, (void *)(uintptr_t)(ilb_base + ILB_IR02)); /* IR02h IR(ABCD) - PIRQ(ABCD) */
+ write16(0x7654, (void *)(uintptr_t)(ilb_base + ILB_IR03)); /* IR03h IR(ABCD) - PIRQ(EFGH) */
+ write16(0x7654, (void *)(uintptr_t)(ilb_base + ILB_IR04)); /* IR04h IR(ABCD) - PIRQ(EFGH) */
+ write16(0x7654, (void *)(uintptr_t)(ilb_base + ILB_IR20)); /* IR14h IR(ABCD) - PIRQ(EFGH) */
+ write16(0x0007, (void *)(uintptr_t)(ilb_base + ILB_IR22)); /* IR16h IR(A) - PIRQ(H) */
+ write16(0x0003, (void *)(uintptr_t)(ilb_base + ILB_IR23)); /* IR17h IR(A) - PIRQ(D) */
+ write16(0x0003, (void *)(uintptr_t)(ilb_base + ILB_IR24)); /* IR18h IR(A) - PIRQ(D) */
+ write16(0x0020, (void *)(uintptr_t)(ilb_base + ILB_IR31)); /* IR1Fh IR(B) - PIRQ(C) */
}
/**
diff --git a/src/mainboard/supermicro/x6dai_g/debug.c b/src/mainboard/supermicro/x6dai_g/debug.c
index b92a75d..b58bf2a 100644
--- a/src/mainboard/supermicro/x6dai_g/debug.c
+++ b/src/mainboard/supermicro/x6dai_g/debug.c
@@ -131,7 +131,7 @@ static void dump_bar14(unsigned dev)
print_debug_hex16(i);
print_debug_char(' ');
}
- print_debug_hex32(read32(bar + i));
+ print_debug_hex32(read32((void *)(uintptr_t)(bar + i)));
print_debug_char(' ');
}
print_debug("\n");
diff --git a/src/mainboard/supermicro/x6dhe_g/debug.c b/src/mainboard/supermicro/x6dhe_g/debug.c
index b92a75d..b58bf2a 100644
--- a/src/mainboard/supermicro/x6dhe_g/debug.c
+++ b/src/mainboard/supermicro/x6dhe_g/debug.c
@@ -131,7 +131,7 @@ static void dump_bar14(unsigned dev)
print_debug_hex16(i);
print_debug_char(' ');
}
- print_debug_hex32(read32(bar + i));
+ print_debug_hex32(read32((void *)(uintptr_t)(bar + i)));
print_debug_char(' ');
}
print_debug("\n");
diff --git a/src/mainboard/supermicro/x6dhe_g2/debug.c b/src/mainboard/supermicro/x6dhe_g2/debug.c
index b92a75d..b58bf2a 100644
--- a/src/mainboard/supermicro/x6dhe_g2/debug.c
+++ b/src/mainboard/supermicro/x6dhe_g2/debug.c
@@ -131,7 +131,7 @@ static void dump_bar14(unsigned dev)
print_debug_hex16(i);
print_debug_char(' ');
}
- print_debug_hex32(read32(bar + i));
+ print_debug_hex32(read32((void *)(uintptr_t)(bar + i)));
print_debug_char(' ');
}
print_debug("\n");
diff --git a/src/mainboard/supermicro/x6dhr_ig/debug.c b/src/mainboard/supermicro/x6dhr_ig/debug.c
index b92a75d..b58bf2a 100644
--- a/src/mainboard/supermicro/x6dhr_ig/debug.c
+++ b/src/mainboard/supermicro/x6dhr_ig/debug.c
@@ -131,7 +131,7 @@ static void dump_bar14(unsigned dev)
print_debug_hex16(i);
print_debug_char(' ');
}
- print_debug_hex32(read32(bar + i));
+ print_debug_hex32(read32((void *)(uintptr_t)(bar + i)));
print_debug_char(' ');
}
print_debug("\n");
diff --git a/src/mainboard/supermicro/x6dhr_ig2/debug.c b/src/mainboard/supermicro/x6dhr_ig2/debug.c
index b92a75d..b58bf2a 100644
--- a/src/mainboard/supermicro/x6dhr_ig2/debug.c
+++ b/src/mainboard/supermicro/x6dhr_ig2/debug.c
@@ -131,7 +131,7 @@ static void dump_bar14(unsigned dev)
print_debug_hex16(i);
print_debug_char(' ');
}
- print_debug_hex32(read32(bar + i));
+ print_debug_hex32(read32((void *)(uintptr_t)(bar + i)));
print_debug_char(' ');
}
print_debug("\n");
diff --git a/src/mainboard/supermicro/x7db8/romstage.c b/src/mainboard/supermicro/x7db8/romstage.c
index 83e34b5..7013cac 100644
--- a/src/mainboard/supermicro/x7db8/romstage.c
+++ b/src/mainboard/supermicro/x7db8/romstage.c
@@ -54,22 +54,22 @@ static void early_config(void)
pci_write_config32(PCI_DEV(0, 0x1F, 0), RCBA, DEFAULT_RCBA | 1);
/* Disable watchdog */
- gcs = read32(DEFAULT_RCBA + RCBA_GCS);
+ gcs = read32((void *)(uintptr_t)(DEFAULT_RCBA + RCBA_GCS));
gcs |= (1 << 5); /* No reset */
- write32(DEFAULT_RCBA + RCBA_GCS, gcs);
+ write32(gcs, (void *)(uintptr_t)(DEFAULT_RCBA + RCBA_GCS));
/* Configure PCIe port B as 4x */
- rpc = read32(DEFAULT_RCBA + RCBA_RPC);
+ rpc = read32((void *)(uintptr_t)(DEFAULT_RCBA + RCBA_RPC));
rpc |= (3 << 0);
- write32(DEFAULT_RCBA + RCBA_RPC, rpc);
+ write32(rpc, (void *)(uintptr_t)(DEFAULT_RCBA + RCBA_RPC));
/* Disable Modem, Audio, PCIe ports 2/3/4 */
- fd = read32(DEFAULT_RCBA + RCBA_FD);
+ fd = read32((void *)(uintptr_t)(DEFAULT_RCBA + RCBA_FD));
fd |= (1 << 19) | (1 << 18) | (1 << 17) | (1 << 6) | (1 << 5);
- write32(DEFAULT_RCBA + RCBA_FD, fd);
+ write32(fd, (void *)(uintptr_t)(DEFAULT_RCBA + RCBA_FD));
/* Enable HPET */
- write32(DEFAULT_RCBA + RCBA_HPTC, (1 << 7));
+ write32((1 << 7), (void *)(uintptr_t)(DEFAULT_RCBA + RCBA_HPTC));
/* Setup sata mode */
pci_write_config8(PCI_DEV(0, 0x1F, 2), SATA_MAP, 0x40);
diff --git a/src/mainboard/thomson/ip1000/mainboard.c b/src/mainboard/thomson/ip1000/mainboard.c
index 7267696..18570fd 100644
--- a/src/mainboard/thomson/ip1000/mainboard.c
+++ b/src/mainboard/thomson/ip1000/mainboard.c
@@ -65,14 +65,14 @@ static void parport_gpios(void)
static void flash_gpios(void)
{
- u8 manufacturer_id = read8(0xffbc0000);
- u8 device_id = read8(0xffbc0001);
+ u8 manufacturer_id = read8((void *)(uintptr_t)(0xffbc0000));
+ u8 device_id = read8((void *)(uintptr_t)(0xffbc0001));
if ((manufacturer_id == 0x20) &&
((device_id == 0x2c) || (device_id == 0x2d))) {
printk(BIOS_DEBUG, "Detected ST M50FW0%c0 flash:\n",
(device_id==0x2c)?'4':'8');
- u8 fgpi = read8(0xffbc0100);
+ u8 fgpi = read8((void *)(uintptr_t)(0xffbc0100));
printk(BIOS_DEBUG, " FGPI0 [%c] FGPI1 [%c] FGPI2 [%c] FGPI3 [%c] FGPI4 [%c]\n",
(fgpi & (1 << 0)) ? 'X' : ' ',
(fgpi & (1 << 1)) ? 'X' : ' ',
diff --git a/src/northbridge/amd/gx1/northbridge.c b/src/northbridge/amd/gx1/northbridge.c
index bcb6e56..c7575d8 100644
--- a/src/northbridge/amd/gx1/northbridge.c
+++ b/src/northbridge/amd/gx1/northbridge.c
@@ -33,8 +33,8 @@ static void optimize_xbus(device_t dev)
static void enable_shadow(device_t dev)
{
- write32(GX_BASE+BC_XMAP_2, 0x77777777);
- write32(GX_BASE+BC_XMAP_3, 0x77777777);
+ write32(0x77777777, (void *)(uintptr_t)(GX_BASE + BC_XMAP_2));
+ write32(0x77777777, (void *)(uintptr_t)(GX_BASE + BC_XMAP_3));
}
static void northbridge_init(device_t dev)
diff --git a/src/northbridge/amd/gx1/raminit.c b/src/northbridge/amd/gx1/raminit.c
index aa07f49..4e654cb 100644
--- a/src/northbridge/amd/gx1/raminit.c
+++ b/src/northbridge/amd/gx1/raminit.c
@@ -34,12 +34,12 @@ it with the version available from LANL.
void setGX1Mem(unsigned int addr, unsigned int data)
{
- write32(addr, data);
+ write32(data, (void *)(uintptr_t)(addr));
}
unsigned int getGX1Mem(unsigned int addr)
{
- return (unsigned int)read32(addr);
+ return (unsigned int)read32((void *)(uintptr_t)(addr));
}
void do_refresh(void)
diff --git a/src/northbridge/intel/e7501/raminit.c b/src/northbridge/intel/e7501/raminit.c
index 2247a25..e2c2ff0 100644
--- a/src/northbridge/intel/e7501/raminit.c
+++ b/src/northbridge/intel/e7501/raminit.c
@@ -900,7 +900,7 @@ static void do_ram_command(uint8_t command, uint16_t jedec_mode_bits)
RAM_DEBUG_HEX32(dimm_start_address + e7501_mode_bits);
RAM_DEBUG_MESSAGE("\n");
- read32(dimm_start_address + e7501_mode_bits);
+ read32((void *)(uintptr_t)(dimm_start_address + e7501_mode_bits));
// Set the start of the next DIMM
dimm_start_64M_multiple =
@@ -1708,7 +1708,7 @@ static void write_8dwords(const uint32_t *src_addr, uint32_t dst_addr)
{
int i;
for (i = 0; i < 8; i++) {
- write32(dst_addr, *src_addr);
+ write32(*src_addr, (void *)(uintptr_t)(dst_addr));
src_addr++;
dst_addr += sizeof(uint32_t);
}
@@ -1740,82 +1740,87 @@ static void ram_set_rcomp_regs(void)
pci_write_config32(PCI_DEV(0, 0, 0), MAYBE_SMRBASE, RCOMP_MMIO);
// Block RCOMP updates while we configure the registers
- dword = read32(RCOMP_MMIO + MAYBE_SMRCTL);
+ dword = read32((void *)(uintptr_t)(RCOMP_MMIO + MAYBE_SMRCTL));
dword |= (1 << 9);
- write32(RCOMP_MMIO + MAYBE_SMRCTL, dword);
+ write32(dword, (void *)(uintptr_t)(RCOMP_MMIO + MAYBE_SMRCTL));
/* Begin to write the RCOMP registers */
// Set CMD and DQ/DQS strength to 2x (?)
- maybe_strength_control = read8(RCOMP_MMIO + MAYBE_DQCMDSTR) & 0x88;
+ maybe_strength_control = read8((void *)(uintptr_t)(RCOMP_MMIO + MAYBE_DQCMDSTR)) & 0x88;
maybe_strength_control |= 0x44;
- write8(RCOMP_MMIO + MAYBE_DQCMDSTR, maybe_strength_control);
+ write8(maybe_strength_control,
+ (void *)(uintptr_t)(RCOMP_MMIO + MAYBE_DQCMDSTR));
write_8dwords(maybe_2x_slew_table, RCOMP_MMIO + 0x80);
- write16(RCOMP_MMIO + 0x42, 0);
+ write16(0, (void *)(uintptr_t)(RCOMP_MMIO + 0x42));
write_8dwords(maybe_1x_slew_table, RCOMP_MMIO + 0x60);
// NOTE: some factory BIOS set 0x9088 here. Seems to work either way.
- write16(RCOMP_MMIO + 0x40, 0);
+ write16(0, (void *)(uintptr_t)(RCOMP_MMIO + 0x40));
// Set RCVEnOut# strength to 2x (?)
- maybe_strength_control = read8(RCOMP_MMIO + MAYBE_RCVENSTR) & 0xF8;
+ maybe_strength_control = read8((void *)(uintptr_t)(RCOMP_MMIO + MAYBE_RCVENSTR)) & 0xF8;
maybe_strength_control |= 4;
- write8(RCOMP_MMIO + MAYBE_RCVENSTR, maybe_strength_control);
+ write8(maybe_strength_control,
+ (void *)(uintptr_t)(RCOMP_MMIO + MAYBE_RCVENSTR));
write_8dwords(maybe_2x_slew_table, RCOMP_MMIO + 0x1c0);
- write16(RCOMP_MMIO + 0x50, 0);
+ write16(0, (void *)(uintptr_t)(RCOMP_MMIO + 0x50));
// Set CS# strength for x4 SDRAM to 2x (?)
- maybe_strength_control = read8(RCOMP_MMIO + MAYBE_CSBSTR) & 0xF8;
+ maybe_strength_control = read8((void *)(uintptr_t)(RCOMP_MMIO + MAYBE_CSBSTR)) & 0xF8;
maybe_strength_control |= 4;
- write8(RCOMP_MMIO + MAYBE_CSBSTR, maybe_strength_control);
+ write8(maybe_strength_control,
+ (void *)(uintptr_t)(RCOMP_MMIO + MAYBE_CSBSTR));
write_8dwords(maybe_2x_slew_table, RCOMP_MMIO + 0x140);
- write16(RCOMP_MMIO + 0x48, 0);
+ write16(0, (void *)(uintptr_t)(RCOMP_MMIO + 0x48));
// Set CKE strength for x4 SDRAM to 2x (?)
- maybe_strength_control = read8(RCOMP_MMIO + MAYBE_CKESTR) & 0xF8;
+ maybe_strength_control = read8((void *)(uintptr_t)(RCOMP_MMIO + MAYBE_CKESTR)) & 0xF8;
maybe_strength_control |= 4;
- write8(RCOMP_MMIO + MAYBE_CKESTR, maybe_strength_control);
+ write8(maybe_strength_control,
+ (void *)(uintptr_t)(RCOMP_MMIO + MAYBE_CKESTR));
write_8dwords(maybe_2x_slew_table, RCOMP_MMIO + 0xa0);
- write16(RCOMP_MMIO + 0x44, 0);
+ write16(0, (void *)(uintptr_t)(RCOMP_MMIO + 0x44));
// Set CK strength for x4 SDRAM to 1x (?)
- maybe_strength_control = read8(RCOMP_MMIO + MAYBE_CKSTR) & 0xF8;
+ maybe_strength_control = read8((void *)(uintptr_t)(RCOMP_MMIO + MAYBE_CKSTR)) & 0xF8;
maybe_strength_control |= 1;
- write8(RCOMP_MMIO + MAYBE_CKSTR, maybe_strength_control);
+ write8(maybe_strength_control,
+ (void *)(uintptr_t)(RCOMP_MMIO + MAYBE_CKSTR));
write_8dwords(maybe_pull_updown_offset_table, RCOMP_MMIO + 0x180);
- write16(RCOMP_MMIO + 0x4c, 0);
+ write16(0, (void *)(uintptr_t)(RCOMP_MMIO + 0x4c));
- write8(RCOMP_MMIO + 0x2c, 0xff);
+ write8(0xff, (void *)(uintptr_t)(RCOMP_MMIO + 0x2c));
// Set the digital filter length to 8 (?)
- dword = read32(RCOMP_MMIO + MAYBE_SMRCTL);
+ dword = read32((void *)(uintptr_t)(RCOMP_MMIO + MAYBE_SMRCTL));
// NOTE: Some factory BIOS don't do this.
// Doesn't seem to matter either way.
dword &= ~2;
dword |= 1;
- write32(RCOMP_MMIO + MAYBE_SMRCTL, dword);
+ write32(dword, (void *)(uintptr_t)(RCOMP_MMIO + MAYBE_SMRCTL));
/* Wait 40 usec */
SLOW_DOWN_IO;
/* unblock updates */
- dword = read32(RCOMP_MMIO + MAYBE_SMRCTL);
+ dword = read32((void *)(uintptr_t)(RCOMP_MMIO + MAYBE_SMRCTL));
dword &= ~(1 << 9);
- write32(RCOMP_MMIO + MAYBE_SMRCTL, dword);
+ write32(dword, (void *)(uintptr_t)(RCOMP_MMIO + MAYBE_SMRCTL));
// Force a RCOMP measurement cycle?
dword |= (1 << 8);
- write32(RCOMP_MMIO + MAYBE_SMRCTL, dword);
+ write32(dword, (void *)(uintptr_t)(RCOMP_MMIO + MAYBE_SMRCTL));
dword &= ~(1 << 8);
- write32(RCOMP_MMIO + MAYBE_SMRCTL, dword);
+ write32(dword, (void *)(uintptr_t)(RCOMP_MMIO + MAYBE_SMRCTL));
/* Wait 40 usec */
SLOW_DOWN_IO;
diff --git a/src/northbridge/intel/e7505/raminit.c b/src/northbridge/intel/e7505/raminit.c
index 909e740..a5092e0 100644
--- a/src/northbridge/intel/e7505/raminit.c
+++ b/src/northbridge/intel/e7505/raminit.c
@@ -280,7 +280,7 @@ static void d060_control(d060_cc cmd)
*/
static void rcomp_smr_control(rcomp_smr_cc cmd)
{
- uint32_t dword = read32(RCOMP_MMIO + SMRCTL);
+ uint32_t dword = read32((void *)(uintptr_t)(RCOMP_MMIO + SMRCTL));
switch (cmd) {
case RCOMP_HOLD:
dword |= (1 << 9);
@@ -296,7 +296,7 @@ static void rcomp_smr_control(rcomp_smr_cc cmd)
dword |= (1 << 10) | (1 << 8);
break;
}
- write32(RCOMP_MMIO + SMRCTL, dword);
+ write32(dword, (void *)(uintptr_t)(RCOMP_MMIO + SMRCTL));
}
/*-----------------------------------------------------------------------------
@@ -713,7 +713,7 @@ static void do_ram_command(uint8_t command, uint16_t jedec_mode_bits)
if (dimm_end_64M_multiple > dimm_start_64M_multiple) {
dimm_start_address &= 0x3ffffff;
dimm_start_address |= dimm_start_64M_multiple << 26;
- read32(dimm_start_address);
+ read32((void *)(uintptr_t)(dimm_start_address));
// Set the start of the next DIMM
dimm_start_64M_multiple = dimm_end_64M_multiple;
}
@@ -1525,7 +1525,7 @@ static void write_8dwords(const uint32_t *src_addr, uint32_t dst_addr)
{
int i;
for (i = 0; i < 8; i++) {
- write32(dst_addr, *src_addr);
+ write32(*src_addr, (void *)(uintptr_t)(dst_addr));
src_addr++;
dst_addr += sizeof(uint32_t);
}
@@ -1549,78 +1549,78 @@ static void rcomp_copy_registers(void)
RAM_DEBUG_MESSAGE("Setting RCOMP registers.\n");
/* Begin to write the RCOMP registers */
- write8(RCOMP_MMIO + 0x2c, 0x0);
+ write8(0x0, (void *)(uintptr_t)(RCOMP_MMIO + 0x2c));
// Set CMD and DQ/DQS strength to 2x (?)
- strength_control = read8(RCOMP_MMIO + DQCMDSTR) & 0x88;
+ strength_control = read8((void *)(uintptr_t)(RCOMP_MMIO + DQCMDSTR)) & 0x88;
strength_control |= 0x40;
- write8(RCOMP_MMIO + DQCMDSTR, strength_control);
+ write8(strength_control, (void *)(uintptr_t)(RCOMP_MMIO + DQCMDSTR));
write_8dwords(slew_2x, RCOMP_MMIO + 0x80);
- write16(RCOMP_MMIO + 0x42, 0);
+ write16(0, (void *)(uintptr_t)(RCOMP_MMIO + 0x42));
// Set CMD and DQ/DQS strength to 2x (?)
- strength_control = read8(RCOMP_MMIO + DQCMDSTR) & 0xF8;
+ strength_control = read8((void *)(uintptr_t)(RCOMP_MMIO + DQCMDSTR)) & 0xF8;
strength_control |= 0x04;
- write8(RCOMP_MMIO + DQCMDSTR, strength_control);
+ write8(strength_control, (void *)(uintptr_t)(RCOMP_MMIO + DQCMDSTR));
write_8dwords(slew_2x, RCOMP_MMIO + 0x60);
- write16(RCOMP_MMIO + 0x40, 0);
+ write16(0, (void *)(uintptr_t)(RCOMP_MMIO + 0x40));
// Set RCVEnOut# strength to 2x (?)
- strength_control = read8(RCOMP_MMIO + RCVENSTR) & 0xF8;
+ strength_control = read8((void *)(uintptr_t)(RCOMP_MMIO + RCVENSTR)) & 0xF8;
strength_control |= 0x04;
- write8(RCOMP_MMIO + RCVENSTR, strength_control);
+ write8(strength_control, (void *)(uintptr_t)(RCOMP_MMIO + RCVENSTR));
write_8dwords(slew_2x, RCOMP_MMIO + 0x1c0);
- write16(RCOMP_MMIO + 0x50, 0);
+ write16(0, (void *)(uintptr_t)(RCOMP_MMIO + 0x50));
// Set CS# strength for x4 SDRAM to 2x (?)
- strength_control = read8(RCOMP_MMIO + CSBSTR) & 0x88;
+ strength_control = read8((void *)(uintptr_t)(RCOMP_MMIO + CSBSTR)) & 0x88;
strength_control |= 0x04;
- write8(RCOMP_MMIO + CSBSTR, strength_control);
+ write8(strength_control, (void *)(uintptr_t)(RCOMP_MMIO + CSBSTR));
write_8dwords(slew_2x, RCOMP_MMIO + 0x140);
- write16(RCOMP_MMIO + 0x48, 0);
+ write16(0, (void *)(uintptr_t)(RCOMP_MMIO + 0x48));
// Set CS# strength for x4 SDRAM to 2x (?)
- strength_control = read8(RCOMP_MMIO + CSBSTR) & 0x8F;
+ strength_control = read8((void *)(uintptr_t)(RCOMP_MMIO + CSBSTR)) & 0x8F;
strength_control |= 0x40;
- write8(RCOMP_MMIO + CSBSTR, strength_control);
+ write8(strength_control, (void *)(uintptr_t)(RCOMP_MMIO + CSBSTR));
write_8dwords(slew_2x, RCOMP_MMIO + 0x160);
- write16(RCOMP_MMIO + 0x4a, 0);
+ write16(0, (void *)(uintptr_t)(RCOMP_MMIO + 0x4a));
// Set CKE strength for x4 SDRAM to 2x (?)
- strength_control = read8(RCOMP_MMIO + CKESTR) & 0x88;
+ strength_control = read8((void *)(uintptr_t)(RCOMP_MMIO + CKESTR)) & 0x88;
strength_control |= 0x04;
- write8(RCOMP_MMIO + CKESTR, strength_control);
+ write8(strength_control, (void *)(uintptr_t)(RCOMP_MMIO + CKESTR));
write_8dwords(slew_2x, RCOMP_MMIO + 0xa0);
- write16(RCOMP_MMIO + 0x44, 0);
+ write16(0, (void *)(uintptr_t)(RCOMP_MMIO + 0x44));
// Set CKE strength for x4 SDRAM to 2x (?)
- strength_control = read8(RCOMP_MMIO + CKESTR) & 0x8F;
+ strength_control = read8((void *)(uintptr_t)(RCOMP_MMIO + CKESTR)) & 0x8F;
strength_control |= 0x40;
- write8(RCOMP_MMIO + CKESTR, strength_control);
+ write8(strength_control, (void *)(uintptr_t)(RCOMP_MMIO + CKESTR));
write_8dwords(slew_2x, RCOMP_MMIO + 0xc0);
- write16(RCOMP_MMIO + 0x46, 0);
+ write16(0, (void *)(uintptr_t)(RCOMP_MMIO + 0x46));
// Set CK strength for x4 SDRAM to 1x (?)
- strength_control = read8(RCOMP_MMIO + CKSTR) & 0x88;
+ strength_control = read8((void *)(uintptr_t)(RCOMP_MMIO + CKSTR)) & 0x88;
strength_control |= 0x01;
- write8(RCOMP_MMIO + CKSTR, strength_control);
+ write8(strength_control, (void *)(uintptr_t)(RCOMP_MMIO + CKSTR));
write_8dwords(pull_updown_offset_table, RCOMP_MMIO + 0x180);
- write16(RCOMP_MMIO + 0x4c, 0);
+ write16(0, (void *)(uintptr_t)(RCOMP_MMIO + 0x4c));
// Set CK strength for x4 SDRAM to 1x (?)
- strength_control = read8(RCOMP_MMIO + CKSTR) & 0x8F;
+ strength_control = read8((void *)(uintptr_t)(RCOMP_MMIO + CKSTR)) & 0x8F;
strength_control |= 0x10;
- write8(RCOMP_MMIO + CKSTR, strength_control);
+ write8(strength_control, (void *)(uintptr_t)(RCOMP_MMIO + CKSTR));
write_8dwords(pull_updown_offset_table, RCOMP_MMIO + 0x1a0);
- write16(RCOMP_MMIO + 0x4e, 0);
+ write16(0, (void *)(uintptr_t)(RCOMP_MMIO + 0x4e));
- dword = read32(RCOMP_MMIO + 0x400);
+ dword = read32((void *)(uintptr_t)(RCOMP_MMIO + 0x400));
dword &= 0x7f7fffff;
- write32(RCOMP_MMIO + 0x400, dword);
+ write32(dword, (void *)(uintptr_t)(RCOMP_MMIO + 0x400));
- dword = read32(RCOMP_MMIO + 0x408);
+ dword = read32((void *)(uintptr_t)(RCOMP_MMIO + 0x408));
dword &= 0x7f7fffff;
- write32(RCOMP_MMIO + 0x408, dword);
+ write32(dword, (void *)(uintptr_t)(RCOMP_MMIO + 0x408));
}
static void ram_set_rcomp_regs(void)
diff --git a/src/northbridge/intel/e7520/raminit.c b/src/northbridge/intel/e7520/raminit.c
index 1e335f5..5409e5b 100644
--- a/src/northbridge/intel/e7520/raminit.c
+++ b/src/northbridge/intel/e7520/raminit.c
@@ -782,11 +782,12 @@ static void set_on_dimm_termination_enable(const struct mem_controller *ctrl)
for(dimm=0;dimm<8;dimm+=1) {
- write32(BAR+DCALADDR, 0x0b840001);
- write32(BAR+DCALCSR, 0x83000003 | (dimm << 20));
+ write32(0x0b840001, (void *)(uintptr_t)(BAR + DCALADDR));
+ write32(0x83000003 | (dimm << 20),
+ (void *)(uintptr_t)(BAR + DCALCSR));
for(i=0;i<1001;i++) {
- data32 = read32(BAR+DCALCSR);
+ data32 = read32((void *)(uintptr_t)(BAR + DCALCSR));
if(!(data32 & (1<<31)))
break;
}
@@ -816,27 +817,29 @@ static void set_receive_enable(const struct mem_controller *ctrl)
for(dimm=0;dimm<8;dimm+=1) {
if(!(dimm&1)) {
- write32(BAR+DCALDATA+(17*4), 0x04020000);
- write32(BAR+DCALCSR, 0x83800004 | (dimm << 20));
+ write32(0x04020000,
+ (void *)(uintptr_t)(BAR + DCALDATA + (17 * 4)));
+ write32(0x83800004 | (dimm << 20),
+ (void *)(uintptr_t)(BAR + DCALCSR));
for(i=0;i<1001;i++) {
- data32 = read32(BAR+DCALCSR);
+ data32 = read32((void *)(uintptr_t)(BAR + DCALCSR));
if(!(data32 & (1<<31)))
break;
}
if(i>=1000)
continue;
- dcal_data32_0 = read32(BAR+DCALDATA + 0);
- dcal_data32_1 = read32(BAR+DCALDATA + 4);
- dcal_data32_2 = read32(BAR+DCALDATA + 8);
- dcal_data32_3 = read32(BAR+DCALDATA + 12);
+ dcal_data32_0 = read32((void *)(uintptr_t)(BAR + DCALDATA + 0));
+ dcal_data32_1 = read32((void *)(uintptr_t)(BAR + DCALDATA + 4));
+ dcal_data32_2 = read32((void *)(uintptr_t)(BAR + DCALDATA + 8));
+ dcal_data32_3 = read32((void *)(uintptr_t)(BAR + DCALDATA + 12));
}
else {
- dcal_data32_0 = read32(BAR+DCALDATA + 16);
- dcal_data32_1 = read32(BAR+DCALDATA + 20);
- dcal_data32_2 = read32(BAR+DCALDATA + 24);
- dcal_data32_3 = read32(BAR+DCALDATA + 28);
+ dcal_data32_0 = read32((void *)(uintptr_t)(BAR + DCALDATA + 16));
+ dcal_data32_1 = read32((void *)(uintptr_t)(BAR + DCALDATA + 20));
+ dcal_data32_2 = read32((void *)(uintptr_t)(BAR + DCALDATA + 24));
+ dcal_data32_3 = read32((void *)(uintptr_t)(BAR + DCALDATA + 28));
}
/* check if bank is installed */
@@ -1013,16 +1016,16 @@ static void set_receive_enable(const struct mem_controller *ctrl)
print_debug("\n");
/* clear out the calibration area */
- write32(BAR+DCALDATA+(16*4), 0x00000000);
- write32(BAR+DCALDATA+(17*4), 0x00000000);
- write32(BAR+DCALDATA+(18*4), 0x00000000);
- write32(BAR+DCALDATA+(19*4), 0x00000000);
+ write32(0x00000000, (void *)(uintptr_t)(BAR + DCALDATA + (16 * 4)));
+ write32(0x00000000, (void *)(uintptr_t)(BAR + DCALDATA + (17 * 4)));
+ write32(0x00000000, (void *)(uintptr_t)(BAR + DCALDATA + (18 * 4)));
+ write32(0x00000000, (void *)(uintptr_t)(BAR + DCALDATA + (19 * 4)));
/* No command */
- write32(BAR+DCALCSR, 0x0000000f);
+ write32(0x0000000f, (void *)(uintptr_t)(BAR + DCALCSR));
- write32(BAR+0x150, recena);
- write32(BAR+0x154, recenb);
+ write32(recena, (void *)(uintptr_t)(BAR + 0x150));
+ write32(recenb, (void *)(uintptr_t)(BAR + 0x154));
}
static void sdram_enable(int controllers, const struct mem_controller *ctrl)
@@ -1124,11 +1127,13 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
/* Apply NOP */
do_delay();
- write32(BAR + 0x100, (0x03000000 | (i<<20)));
+ write32((0x03000000 | (i << 20)),
+ (void *)(uintptr_t)(BAR + 0x100));
- write32(BAR+0x100, (0x83000000 | (i<<20)));
+ write32((0x83000000 | (i << 20)),
+ (void *)(uintptr_t)(BAR + 0x100));
- do data32 = read32(BAR+DCALCSR);
+ do data32 = read32((void *)(uintptr_t)(BAR + DCALCSR));
while(data32 & 0x80000000);
}
@@ -1137,8 +1142,9 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
do_delay();
for(cs=0;cs<8;cs++) {
- write32(BAR + DCALCSR, (0x83000000 | (cs<<20)));
- do data32 = read32(BAR+DCALCSR);
+ write32((0x83000000 | (cs << 20)),
+ (void *)(uintptr_t)(BAR + DCALCSR));
+ do data32 = read32((void *)(uintptr_t)(BAR + DCALCSR));
while(data32 & 0x80000000);
}
@@ -1146,11 +1152,14 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
do_delay();
for(cs=0;cs<8;cs++) {
if ((drc & 3) == 2) /* DDR2 */
- write32(BAR+DCALADDR, 0x04000000);
+ write32(0x04000000,
+ (void *)(uintptr_t)(BAR + DCALADDR));
else /* DDR1 */
- write32(BAR+DCALADDR, 0x00000000);
- write32(BAR+DCALCSR, (0x83000002 | (cs<<20)));
- do data32 = read32(BAR+DCALCSR);
+ write32(0x00000000,
+ (void *)(uintptr_t)(BAR + DCALADDR));
+ write32((0x83000002 | (cs << 20)),
+ (void *)(uintptr_t)(BAR + DCALCSR));
+ do data32 = read32((void *)(uintptr_t)(BAR + DCALCSR));
while(data32 & 0x80000000);
}
@@ -1159,11 +1168,14 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
for(cs=0;cs<8;cs++) {
if ((drc & 3) == 2) /* DDR2 */
/* fixme hard code AL additive latency */
- write32(BAR+DCALADDR, 0x0b940001);
+ write32(0x0b940001,
+ (void *)(uintptr_t)(BAR + DCALADDR));
else /* DDR1 */
- write32(BAR+DCALADDR, 0x00000001);
- write32(BAR+DCALCSR, (0x83000003 | (cs<<20)));
- do data32 = read32(BAR+DCALCSR);
+ write32(0x00000001,
+ (void *)(uintptr_t)(BAR + DCALADDR));
+ write32((0x83000003 | (cs << 20)),
+ (void *)(uintptr_t)(BAR + DCALCSR));
+ do data32 = read32((void *)(uintptr_t)(BAR + DCALCSR));
while(data32 & 0x80000000);
}
/* MRS reset dll's */
@@ -1181,9 +1193,10 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
mode_reg = 0x016a0000;
}
for(cs=0;cs<8;cs++) {
- write32(BAR+DCALADDR, mode_reg);
- write32(BAR+DCALCSR, (0x83000003 | (cs<<20)));
- do data32 = read32(BAR+DCALCSR);
+ write32(mode_reg, (void *)(uintptr_t)(BAR + DCALADDR));
+ write32((0x83000003 | (cs << 20)),
+ (void *)(uintptr_t)(BAR + DCALCSR));
+ do data32 = read32((void *)(uintptr_t)(BAR + DCALCSR));
while(data32 & 0x80000000);
}
@@ -1193,59 +1206,72 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
do_delay();
for(cs=0;cs<8;cs++) {
if ((drc & 3) == 2) /* DDR2 */
- write32(BAR+DCALADDR, 0x04000000);
+ write32(0x04000000,
+ (void *)(uintptr_t)(BAR + DCALADDR));
else /* DDR1 */
- write32(BAR+DCALADDR, 0x00000000);
- write32(BAR+DCALCSR, (0x83000002 | (cs<<20)));
- do data32 = read32(BAR+DCALCSR);
+ write32(0x00000000,
+ (void *)(uintptr_t)(BAR + DCALADDR));
+ write32((0x83000002 | (cs << 20)),
+ (void *)(uintptr_t)(BAR + DCALCSR));
+ do data32 = read32((void *)(uintptr_t)(BAR + DCALCSR));
while(data32 & 0x80000000);
}
/* Do 2 refreshes */
do_delay();
for(cs=0;cs<8;cs++) {
- write32(BAR+DCALCSR, (0x83000001 | (cs<<20)));
- do data32 = read32(BAR+DCALCSR);
+ write32((0x83000001 | (cs << 20)),
+ (void *)(uintptr_t)(BAR + DCALCSR));
+ do data32 = read32((void *)(uintptr_t)(BAR + DCALCSR));
while(data32 & 0x80000000);
}
do_delay();
for(cs=0;cs<8;cs++) {
- write32(BAR+DCALCSR, (0x83000001 | (cs<<20)));
- do data32 = read32(BAR+DCALCSR);
+ write32((0x83000001 | (cs << 20)),
+ (void *)(uintptr_t)(BAR + DCALCSR));
+ do data32 = read32((void *)(uintptr_t)(BAR + DCALCSR));
while(data32 & 0x80000000);
}
do_delay();
/* for good luck do 6 more */
for(cs=0;cs<8;cs++) {
- write32(BAR+DCALCSR, (0x83000001 | (cs<<20)));
+ write32((0x83000001 | (cs << 20)),
+ (void *)(uintptr_t)(BAR + DCALCSR));
}
do_delay();
for(cs=0;cs<8;cs++) {
- write32(BAR+DCALCSR, (0x83000001 | (cs<<20)));
+ write32((0x83000001 | (cs << 20)),
+ (void *)(uintptr_t)(BAR + DCALCSR));
}
do_delay();
for(cs=0;cs<8;cs++) {
- write32(BAR+DCALCSR, (0x83000001 | (cs<<20)));
+ write32((0x83000001 | (cs << 20)),
+ (void *)(uintptr_t)(BAR + DCALCSR));
}
do_delay();
for(cs=0;cs<8;cs++) {
- write32(BAR+DCALCSR, (0x83000001 | (cs<<20)));
+ write32((0x83000001 | (cs << 20)),
+ (void *)(uintptr_t)(BAR + DCALCSR));
}
do_delay();
for(cs=0;cs<8;cs++) {
- write32(BAR+DCALCSR, (0x83000001 | (cs<<20)));
+ write32((0x83000001 | (cs << 20)),
+ (void *)(uintptr_t)(BAR + DCALCSR));
}
do_delay();
for(cs=0;cs<8;cs++) {
- write32(BAR+DCALCSR, (0x83000001 | (cs<<20)));
+ write32((0x83000001 | (cs << 20)),
+ (void *)(uintptr_t)(BAR + DCALCSR));
}
do_delay();
/* MRS reset dll's normal */
do_delay();
for(cs=0;cs<8;cs++) {
- write32(BAR+DCALADDR, (mode_reg & ~(1<<24)));
- write32(BAR+DCALCSR, (0x83000003 | (cs<<20)));
- do data32 = read32(BAR+DCALCSR);
+ write32((mode_reg & ~(1 << 24)),
+ (void *)(uintptr_t)(BAR + DCALADDR));
+ write32((0x83000003 | (cs << 20)),
+ (void *)(uintptr_t)(BAR + DCALCSR));
+ do data32 = read32((void *)(uintptr_t)(BAR + DCALCSR));
while(data32 & 0x80000000);
}
@@ -1253,20 +1279,22 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
if ((drc & 3) == 2) { /* DDR2 */
do_delay();
for(cs=0;cs<8;cs++) {
- write32(BAR+DCALADDR, (0x0b940001));
- write32(BAR+DCALCSR, (0x83000003 | (cs<<20)));
- do data32 = read32(BAR+DCALCSR);
+ write32((0x0b940001),
+ (void *)(uintptr_t)(BAR + DCALADDR));
+ write32((0x83000003 | (cs << 20)),
+ (void *)(uintptr_t)(BAR + DCALCSR));
+ do data32 = read32((void *)(uintptr_t)(BAR + DCALCSR));
while(data32 & 0x80000000);
}
}
do_delay();
/* No command */
- write32(BAR+DCALCSR, 0x0000000f);
+ write32(0x0000000f, (void *)(uintptr_t)(BAR + DCALCSR));
/* DDR1 This is test code to copy some codes in the factory setup */
- write32(BAR, 0x00100000);
+ write32(0x00100000, (void *)(uintptr_t)(BAR));
if ((drc & 3) == 2) { /* DDR2 */
/* enable on dimm termination */
@@ -1282,7 +1310,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
/* DQS */
pci_write_config32(PCI_DEV(0, 0x00, 0), 0x94, 0x3904a100 );
for(i = 0, cnt = (BAR+0x200); i < 24; i++, cnt+=4) {
- write32(cnt, dqs_data[i]);
+ write32(dqs_data[i], (void *)(uintptr_t)(cnt));
}
pci_write_config32(PCI_DEV(0, 0x00, 0), 0x94, 0x3904a100 );
@@ -1290,17 +1318,18 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
/* 0x7c DRC */
data32 = drc & ~(3 << 20); /* clear ECC mode */
pci_write_config32(PCI_DEV(0, 0x00, 0), DRC, data32);
- write32(BAR+DCALCSR, 0x0008000f);
+ write32(0x0008000f, (void *)(uintptr_t)(BAR + DCALCSR));
/* clear memory and init ECC */
print_debug("Clearing memory\n");
for(i=0;i<64;i+=4) {
- write32(BAR+DCALDATA+i, 0x00000000);
+ write32(0x00000000, (void *)(uintptr_t)(BAR + DCALDATA + i));
}
for(cs=0;cs<8;cs++) {
- write32(BAR+DCALCSR, (0x830831d8 | (cs<<20)));
- do data32 = read32(BAR+DCALCSR);
+ write32((0x830831d8 | (cs << 20)),
+ (void *)(uintptr_t)(BAR + DCALCSR));
+ do data32 = read32((void *)(uintptr_t)(BAR + DCALCSR));
while(data32 & 0x80000000);
}
diff --git a/src/northbridge/intel/e7525/raminit.c b/src/northbridge/intel/e7525/raminit.c
index 0e6e204..c93b174 100644
--- a/src/northbridge/intel/e7525/raminit.c
+++ b/src/northbridge/intel/e7525/raminit.c
@@ -759,11 +759,12 @@ static void set_on_dimm_termination_enable(const struct mem_controller *ctrl)
for(dimm=0;dimm<8;dimm+=1) {
- write32(BAR+DCALADDR, 0x0b840001);
- write32(BAR+DCALCSR, 0x83000003 | (dimm << 20));
+ write32(0x0b840001, (void *)(uintptr_t)(BAR + DCALADDR));
+ write32(0x83000003 | (dimm << 20),
+ (void *)(uintptr_t)(BAR + DCALCSR));
for(i=0;i<1001;i++) {
- data32 = read32(BAR+DCALCSR);
+ data32 = read32((void *)(uintptr_t)(BAR + DCALCSR));
if(!(data32 & (1<<31)))
break;
}
@@ -792,27 +793,29 @@ static void set_receive_enable(const struct mem_controller *ctrl)
for(dimm=0;dimm<8;dimm+=1) {
if(!(dimm&1)) {
- write32(BAR+DCALDATA+(17*4), 0x04020000);
- write32(BAR+DCALCSR, 0x83800004 | (dimm << 20));
+ write32(0x04020000,
+ (void *)(uintptr_t)(BAR + DCALDATA + (17 * 4)));
+ write32(0x83800004 | (dimm << 20),
+ (void *)(uintptr_t)(BAR + DCALCSR));
for(i=0;i<1001;i++) {
- data32 = read32(BAR+DCALCSR);
+ data32 = read32((void *)(uintptr_t)(BAR + DCALCSR));
if(!(data32 & (1<<31)))
break;
}
if(i>=1000)
continue;
- dcal_data32_0 = read32(BAR+DCALDATA + 0);
- dcal_data32_1 = read32(BAR+DCALDATA + 4);
- dcal_data32_2 = read32(BAR+DCALDATA + 8);
- dcal_data32_3 = read32(BAR+DCALDATA + 12);
+ dcal_data32_0 = read32((void *)(uintptr_t)(BAR + DCALDATA + 0));
+ dcal_data32_1 = read32((void *)(uintptr_t)(BAR + DCALDATA + 4));
+ dcal_data32_2 = read32((void *)(uintptr_t)(BAR + DCALDATA + 8));
+ dcal_data32_3 = read32((void *)(uintptr_t)(BAR + DCALDATA + 12));
}
else {
- dcal_data32_0 = read32(BAR+DCALDATA + 16);
- dcal_data32_1 = read32(BAR+DCALDATA + 20);
- dcal_data32_2 = read32(BAR+DCALDATA + 24);
- dcal_data32_3 = read32(BAR+DCALDATA + 28);
+ dcal_data32_0 = read32((void *)(uintptr_t)(BAR + DCALDATA + 16));
+ dcal_data32_1 = read32((void *)(uintptr_t)(BAR + DCALDATA + 20));
+ dcal_data32_2 = read32((void *)(uintptr_t)(BAR + DCALDATA + 24));
+ dcal_data32_3 = read32((void *)(uintptr_t)(BAR + DCALDATA + 28));
}
/* check if bank is installed */
@@ -989,16 +992,16 @@ static void set_receive_enable(const struct mem_controller *ctrl)
print_debug("\n");
/* clear out the calibration area */
- write32(BAR+DCALDATA+(16*4), 0x00000000);
- write32(BAR+DCALDATA+(17*4), 0x00000000);
- write32(BAR+DCALDATA+(18*4), 0x00000000);
- write32(BAR+DCALDATA+(19*4), 0x00000000);
+ write32(0x00000000, (void *)(uintptr_t)(BAR + DCALDATA + (16 * 4)));
+ write32(0x00000000, (void *)(uintptr_t)(BAR + DCALDATA + (17 * 4)));
+ write32(0x00000000, (void *)(uintptr_t)(BAR + DCALDATA + (18 * 4)));
+ write32(0x00000000, (void *)(uintptr_t)(BAR + DCALDATA + (19 * 4)));
/* No command */
- write32(BAR+DCALCSR, 0x0000000f);
+ write32(0x0000000f, (void *)(uintptr_t)(BAR + DCALCSR));
- write32(BAR+0x150, recena);
- write32(BAR+0x154, recenb);
+ write32(recena, (void *)(uintptr_t)(BAR + 0x150));
+ write32(recenb, (void *)(uintptr_t)(BAR + 0x154));
}
@@ -1100,11 +1103,13 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
/* Apply NOP */
do_delay();
- write32(BAR + 0x100, (0x03000000 | (i<<20)));
+ write32((0x03000000 | (i << 20)),
+ (void *)(uintptr_t)(BAR + 0x100));
- write32(BAR+0x100, (0x83000000 | (i<<20)));
+ write32((0x83000000 | (i << 20)),
+ (void *)(uintptr_t)(BAR + 0x100));
- do data32 = read32(BAR+DCALCSR);
+ do data32 = read32((void *)(uintptr_t)(BAR + DCALCSR));
while(data32 & 0x80000000);
}
@@ -1113,8 +1118,9 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
do_delay();
for(cs=0;cs<8;cs++) {
- write32(BAR + DCALCSR, (0x83000000 | (cs<<20)));
- do data32 = read32(BAR+DCALCSR);
+ write32((0x83000000 | (cs << 20)),
+ (void *)(uintptr_t)(BAR + DCALCSR));
+ do data32 = read32((void *)(uintptr_t)(BAR + DCALCSR));
while(data32 & 0x80000000);
}
@@ -1122,11 +1128,14 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
do_delay();
for(cs=0;cs<8;cs++) {
if ((drc & 3) == 2) /* DDR2 */
- write32(BAR+DCALADDR, 0x04000000);
+ write32(0x04000000,
+ (void *)(uintptr_t)(BAR + DCALADDR));
else /* DDR1 */
- write32(BAR+DCALADDR, 0x00000000);
- write32(BAR+DCALCSR, (0x83000002 | (cs<<20)));
- do data32 = read32(BAR+DCALCSR);
+ write32(0x00000000,
+ (void *)(uintptr_t)(BAR + DCALADDR));
+ write32((0x83000002 | (cs << 20)),
+ (void *)(uintptr_t)(BAR + DCALCSR));
+ do data32 = read32((void *)(uintptr_t)(BAR + DCALCSR));
while(data32 & 0x80000000);
}
@@ -1135,11 +1144,14 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
for(cs=0;cs<8;cs++) {
if ((drc & 3) == 2) /* DDR2 */
/* fixme hard code AL additive latency */
- write32(BAR+DCALADDR, 0x0b940001);
+ write32(0x0b940001,
+ (void *)(uintptr_t)(BAR + DCALADDR));
else /* DDR1 */
- write32(BAR+DCALADDR, 0x00000001);
- write32(BAR+DCALCSR, (0x83000003 | (cs<<20)));
- do data32 = read32(BAR+DCALCSR);
+ write32(0x00000001,
+ (void *)(uintptr_t)(BAR + DCALADDR));
+ write32((0x83000003 | (cs << 20)),
+ (void *)(uintptr_t)(BAR + DCALCSR));
+ do data32 = read32((void *)(uintptr_t)(BAR + DCALCSR));
while(data32 & 0x80000000);
}
/* MRS reset dll's */
@@ -1157,9 +1169,10 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
mode_reg = 0x016a0000;
}
for(cs=0;cs<8;cs++) {
- write32(BAR+DCALADDR, mode_reg);
- write32(BAR+DCALCSR, (0x83000003 | (cs<<20)));
- do data32 = read32(BAR+DCALCSR);
+ write32(mode_reg, (void *)(uintptr_t)(BAR + DCALADDR));
+ write32((0x83000003 | (cs << 20)),
+ (void *)(uintptr_t)(BAR + DCALCSR));
+ do data32 = read32((void *)(uintptr_t)(BAR + DCALCSR));
while(data32 & 0x80000000);
}
@@ -1169,59 +1182,72 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
do_delay();
for(cs=0;cs<8;cs++) {
if ((drc & 3) == 2) /* DDR2 */
- write32(BAR+DCALADDR, 0x04000000);
+ write32(0x04000000,
+ (void *)(uintptr_t)(BAR + DCALADDR));
else /* DDR1 */
- write32(BAR+DCALADDR, 0x00000000);
- write32(BAR+DCALCSR, (0x83000002 | (cs<<20)));
- do data32 = read32(BAR+DCALCSR);
+ write32(0x00000000,
+ (void *)(uintptr_t)(BAR + DCALADDR));
+ write32((0x83000002 | (cs << 20)),
+ (void *)(uintptr_t)(BAR + DCALCSR));
+ do data32 = read32((void *)(uintptr_t)(BAR + DCALCSR));
while(data32 & 0x80000000);
}
/* Do 2 refreshes */
do_delay();
for(cs=0;cs<8;cs++) {
- write32(BAR+DCALCSR, (0x83000001 | (cs<<20)));
- do data32 = read32(BAR+DCALCSR);
+ write32((0x83000001 | (cs << 20)),
+ (void *)(uintptr_t)(BAR + DCALCSR));
+ do data32 = read32((void *)(uintptr_t)(BAR + DCALCSR));
while(data32 & 0x80000000);
}
do_delay();
for(cs=0;cs<8;cs++) {
- write32(BAR+DCALCSR, (0x83000001 | (cs<<20)));
- do data32 = read32(BAR+DCALCSR);
+ write32((0x83000001 | (cs << 20)),
+ (void *)(uintptr_t)(BAR + DCALCSR));
+ do data32 = read32((void *)(uintptr_t)(BAR + DCALCSR));
while(data32 & 0x80000000);
}
do_delay();
/* for good luck do 6 more */
for(cs=0;cs<8;cs++) {
- write32(BAR+DCALCSR, (0x83000001 | (cs<<20)));
+ write32((0x83000001 | (cs << 20)),
+ (void *)(uintptr_t)(BAR + DCALCSR));
}
do_delay();
for(cs=0;cs<8;cs++) {
- write32(BAR+DCALCSR, (0x83000001 | (cs<<20)));
+ write32((0x83000001 | (cs << 20)),
+ (void *)(uintptr_t)(BAR + DCALCSR));
}
do_delay();
for(cs=0;cs<8;cs++) {
- write32(BAR+DCALCSR, (0x83000001 | (cs<<20)));
+ write32((0x83000001 | (cs << 20)),
+ (void *)(uintptr_t)(BAR + DCALCSR));
}
do_delay();
for(cs=0;cs<8;cs++) {
- write32(BAR+DCALCSR, (0x83000001 | (cs<<20)));
+ write32((0x83000001 | (cs << 20)),
+ (void *)(uintptr_t)(BAR + DCALCSR));
}
do_delay();
for(cs=0;cs<8;cs++) {
- write32(BAR+DCALCSR, (0x83000001 | (cs<<20)));
+ write32((0x83000001 | (cs << 20)),
+ (void *)(uintptr_t)(BAR + DCALCSR));
}
do_delay();
for(cs=0;cs<8;cs++) {
- write32(BAR+DCALCSR, (0x83000001 | (cs<<20)));
+ write32((0x83000001 | (cs << 20)),
+ (void *)(uintptr_t)(BAR + DCALCSR));
}
do_delay();
/* MRS reset dll's normal */
do_delay();
for(cs=0;cs<8;cs++) {
- write32(BAR+DCALADDR, (mode_reg & ~(1<<24)));
- write32(BAR+DCALCSR, (0x83000003 | (cs<<20)));
- do data32 = read32(BAR+DCALCSR);
+ write32((mode_reg & ~(1 << 24)),
+ (void *)(uintptr_t)(BAR + DCALADDR));
+ write32((0x83000003 | (cs << 20)),
+ (void *)(uintptr_t)(BAR + DCALCSR));
+ do data32 = read32((void *)(uintptr_t)(BAR + DCALCSR));
while(data32 & 0x80000000);
}
@@ -1229,20 +1255,22 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
if ((drc & 3) == 2) { /* DDR2 */
do_delay();
for(cs=0;cs<8;cs++) {
- write32(BAR+DCALADDR, (0x0b940001));
- write32(BAR+DCALCSR, (0x83000003 | (cs<<20)));
- do data32 = read32(BAR+DCALCSR);
+ write32((0x0b940001),
+ (void *)(uintptr_t)(BAR + DCALADDR));
+ write32((0x83000003 | (cs << 20)),
+ (void *)(uintptr_t)(BAR + DCALCSR));
+ do data32 = read32((void *)(uintptr_t)(BAR + DCALCSR));
while(data32 & 0x80000000);
}
}
do_delay();
/* No command */
- write32(BAR+DCALCSR, 0x0000000f);
+ write32(0x0000000f, (void *)(uintptr_t)(BAR + DCALCSR));
/* DDR1 This is test code to copy some codes in the factory setup */
- write32(BAR, 0x00100000);
+ write32(0x00100000, (void *)(uintptr_t)(BAR));
if ((drc & 3) == 2) { /* DDR2 */
/* enable on dimm termination */
@@ -1255,7 +1283,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
/* DQS */
pci_write_config32(ctrl->f0, 0x94, 0x3904a100 );
for(i = 0, cnt = (BAR+0x200); i < 24; i++, cnt+=4) {
- write32(cnt, dqs_data[i]);
+ write32(dqs_data[i], (void *)(uintptr_t)(cnt));
}
pci_write_config32(ctrl->f0, 0x94, 0x3904a100 );
@@ -1263,17 +1291,18 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
/* 0x7c DRC */
data32 = drc & ~(3 << 20); /* clear ECC mode */
pci_write_config32(ctrl->f0, DRC, data32);
- write32(BAR+DCALCSR, 0x0008000f);
+ write32(0x0008000f, (void *)(uintptr_t)(BAR + DCALCSR));
/* clear memory and init ECC */
print_debug("Clearing memory\n");
for(i=0;i<64;i+=4) {
- write32(BAR+DCALDATA+i, 0x00000000);
+ write32(0x00000000, (void *)(uintptr_t)(BAR + DCALDATA + i));
}
for(cs=0;cs<8;cs++) {
- write32(BAR+DCALCSR, (0x830831d8 | (cs<<20)));
- do data32 = read32(BAR+DCALCSR);
+ write32((0x830831d8 | (cs << 20)),
+ (void *)(uintptr_t)(BAR + DCALCSR));
+ do data32 = read32((void *)(uintptr_t)(BAR + DCALCSR));
while(data32 & 0x80000000);
}
diff --git a/src/northbridge/intel/fsp_sandybridge/acpi.c b/src/northbridge/intel/fsp_sandybridge/acpi.c
index a372e7b..6515b59 100644
--- a/src/northbridge/intel/fsp_sandybridge/acpi.c
+++ b/src/northbridge/intel/fsp_sandybridge/acpi.c
@@ -120,7 +120,7 @@ static int init_opregion_vbt(igd_opregion_t *opregion)
optionrom_vbt_t *vbt = (optionrom_vbt_t *)(vbios +
oprom->vbt_offset);
- if (read32((unsigned long)vbt->hdr_signature) != VBT_SIGNATURE) {
+ if (read32((void *)(uintptr_t)((unsigned long)vbt->hdr_signature)) != VBT_SIGNATURE) {
printk(BIOS_DEBUG, "VBT not found!\n");
return 1;
}
diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c
index 74e16ad..1523441 100644
--- a/src/northbridge/intel/gm45/gma.c
+++ b/src/northbridge/intel/gm45/gma.c
@@ -43,63 +43,63 @@ static struct resource *gtt_res = NULL;
void gtt_write(u32 reg, u32 data)
{
- write32(gtt_res->base + reg, data);
+ write32(data, (void *)(uintptr_t)(gtt_res->base + reg));
}
#if IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)
static void power_port(u32 mmio)
{
- read32(mmio + 0x00061100); // = 0x00000000
- write32(mmio + 0x00061100, 0x00000000);
- write32(mmio + 0x00061100, 0x00010000);
- read32(mmio + 0x00061100); // = 0x00010000
- read32(mmio + 0x00061100); // = 0x00010000
- read32(mmio + 0x00061100); // = 0x00000000
- write32(mmio + 0x00061100, 0x00000000);
- read32(mmio + 0x00061100); // = 0x00000000
- read32(mmio + 0x00064200); // = 0x0000001c
- write32(mmio + 0x00064210, 0x8004003e);
- write32(mmio + 0x00064214, 0x80060002);
- write32(mmio + 0x00064218, 0x01000000);
- read32(mmio + 0x00064210); // = 0x5144003e
- write32(mmio + 0x00064210, 0x5344003e);
- read32(mmio + 0x00064210); // = 0x0144003e
- write32(mmio + 0x00064210, 0x8074003e);
- read32(mmio + 0x00064210); // = 0x5144003e
- read32(mmio + 0x00064210); // = 0x5144003e
- write32(mmio + 0x00064210, 0x5344003e);
- read32(mmio + 0x00064210); // = 0x0144003e
- write32(mmio + 0x00064210, 0x8074003e);
- read32(mmio + 0x00064210); // = 0x5144003e
- read32(mmio + 0x00064210); // = 0x5144003e
- write32(mmio + 0x00064210, 0x5344003e);
- read32(mmio + 0x00064210); // = 0x0144003e
- write32(mmio + 0x00064210, 0x8074003e);
- read32(mmio + 0x00064210); // = 0x5144003e
- read32(mmio + 0x00064210); // = 0x5144003e
- write32(mmio + 0x00064210, 0x5344003e);
- write32(mmio + 0x00064f00, 0x0100030c);
- write32(mmio + 0x00064f04, 0x00b8230c);
- write32(mmio + 0x00064f08, 0x06f8930c);
- write32(mmio + 0x00064f0c, 0x09f8e38e);
- write32(mmio + 0x00064f10, 0x00b8030c);
- write32(mmio + 0x00064f14, 0x0b78830c);
- write32(mmio + 0x00064f18, 0x0ff8d3cf);
- write32(mmio + 0x00064f1c, 0x01e8030c);
- write32(mmio + 0x00064f20, 0x0ff863cf);
- write32(mmio + 0x00064f24, 0x0ff803cf);
- write32(mmio + 0x000c4030, 0x00001000);
- read32(mmio + 0x00044000); // = 0x00000000
- write32(mmio + 0x00044030, 0x00001000);
- read32(mmio + 0x00061150); // = 0x0000001c
- write32(mmio + 0x00061150, 0x0000089c);
- write32(mmio + 0x000fcc00, 0x01986f00);
- write32(mmio + 0x000fcc0c, 0x01986f00);
- write32(mmio + 0x000fcc18, 0x01986f00);
- write32(mmio + 0x000fcc24, 0x01986f00);
- read32(mmio + 0x00044000); // = 0x00000000
- read32(mmio + LVDS); // = 0x40000002
+ read32((void *)(uintptr_t)(mmio + 0x00061100)); // = 0x00000000
+ write32(0x00000000, (void *)(uintptr_t)(mmio + 0x00061100));
+ write32(0x00010000, (void *)(uintptr_t)(mmio + 0x00061100));
+ read32((void *)(uintptr_t)(mmio + 0x00061100)); // = 0x00010000
+ read32((void *)(uintptr_t)(mmio + 0x00061100)); // = 0x00010000
+ read32((void *)(uintptr_t)(mmio + 0x00061100)); // = 0x00000000
+ write32(0x00000000, (void *)(uintptr_t)(mmio + 0x00061100));
+ read32((void *)(uintptr_t)(mmio + 0x00061100)); // = 0x00000000
+ read32((void *)(uintptr_t)(mmio + 0x00064200)); // = 0x0000001c
+ write32(0x8004003e, (void *)(uintptr_t)(mmio + 0x00064210));
+ write32(0x80060002, (void *)(uintptr_t)(mmio + 0x00064214));
+ write32(0x01000000, (void *)(uintptr_t)(mmio + 0x00064218));
+ read32((void *)(uintptr_t)(mmio + 0x00064210)); // = 0x5144003e
+ write32(0x5344003e, (void *)(uintptr_t)(mmio + 0x00064210));
+ read32((void *)(uintptr_t)(mmio + 0x00064210)); // = 0x0144003e
+ write32(0x8074003e, (void *)(uintptr_t)(mmio + 0x00064210));
+ read32((void *)(uintptr_t)(mmio + 0x00064210)); // = 0x5144003e
+ read32((void *)(uintptr_t)(mmio + 0x00064210)); // = 0x5144003e
+ write32(0x5344003e, (void *)(uintptr_t)(mmio + 0x00064210));
+ read32((void *)(uintptr_t)(mmio + 0x00064210)); // = 0x0144003e
+ write32(0x8074003e, (void *)(uintptr_t)(mmio + 0x00064210));
+ read32((void *)(uintptr_t)(mmio + 0x00064210)); // = 0x5144003e
+ read32((void *)(uintptr_t)(mmio + 0x00064210)); // = 0x5144003e
+ write32(0x5344003e, (void *)(uintptr_t)(mmio + 0x00064210));
+ read32((void *)(uintptr_t)(mmio + 0x00064210)); // = 0x0144003e
+ write32(0x8074003e, (void *)(uintptr_t)(mmio + 0x00064210));
+ read32((void *)(uintptr_t)(mmio + 0x00064210)); // = 0x5144003e
+ read32((void *)(uintptr_t)(mmio + 0x00064210)); // = 0x5144003e
+ write32(0x5344003e, (void *)(uintptr_t)(mmio + 0x00064210));
+ write32(0x0100030c, (void *)(uintptr_t)(mmio + 0x00064f00));
+ write32(0x00b8230c, (void *)(uintptr_t)(mmio + 0x00064f04));
+ write32(0x06f8930c, (void *)(uintptr_t)(mmio + 0x00064f08));
+ write32(0x09f8e38e, (void *)(uintptr_t)(mmio + 0x00064f0c));
+ write32(0x00b8030c, (void *)(uintptr_t)(mmio + 0x00064f10));
+ write32(0x0b78830c, (void *)(uintptr_t)(mmio + 0x00064f14));
+ write32(0x0ff8d3cf, (void *)(uintptr_t)(mmio + 0x00064f18));
+ write32(0x01e8030c, (void *)(uintptr_t)(mmio + 0x00064f1c));
+ write32(0x0ff863cf, (void *)(uintptr_t)(mmio + 0x00064f20));
+ write32(0x0ff803cf, (void *)(uintptr_t)(mmio + 0x00064f24));
+ write32(0x00001000, (void *)(uintptr_t)(mmio + 0x000c4030));
+ read32((void *)(uintptr_t)(mmio + 0x00044000)); // = 0x00000000
+ write32(0x00001000, (void *)(uintptr_t)(mmio + 0x00044030));
+ read32((void *)(uintptr_t)(mmio + 0x00061150)); // = 0x0000001c
+ write32(0x0000089c, (void *)(uintptr_t)(mmio + 0x00061150));
+ write32(0x01986f00, (void *)(uintptr_t)(mmio + 0x000fcc00));
+ write32(0x01986f00, (void *)(uintptr_t)(mmio + 0x000fcc0c));
+ write32(0x01986f00, (void *)(uintptr_t)(mmio + 0x000fcc18));
+ write32(0x01986f00, (void *)(uintptr_t)(mmio + 0x000fcc24));
+ read32((void *)(uintptr_t)(mmio + 0x00044000)); // = 0x00000000
+ read32((void *)(uintptr_t)(mmio + LVDS)); // = 0x40000002
}
static void intel_gma_init(const struct northbridge_intel_gm45_config *info,
@@ -134,9 +134,9 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info,
outl(physbase + (i << 12) + 1, piobase + 4);
}
- write32(mmio + 0x61100, 0x40008c18);
- write32(mmio + 0x7041c, 0x0);
- write32(mmio + 0x6020, 0x3);
+ write32(0x40008c18, (void *)(uintptr_t)(mmio + 0x61100));
+ write32(0x0, (void *)(uintptr_t)(mmio + 0x7041c));
+ write32(0x3, (void *)(uintptr_t)(mmio + 0x6020));
vga_misc_write(0x67);
@@ -194,12 +194,13 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info,
edid.bytes_per_line = (edid.bytes_per_line + 63) & ~63;
- write32(mmio + DSPCNTR(0), DISPPLANE_BGRX888);
- write32(mmio + DSPADDR(0), 0);
- write32(mmio + DSPSTRIDE(0), edid.bytes_per_line);
- write32(mmio + DSPSURF(0), 0);
+ write32(DISPPLANE_BGRX888, (void *)(uintptr_t)(mmio + DSPCNTR(0)));
+ write32(0, (void *)(uintptr_t)(mmio + DSPADDR(0)));
+ write32(edid.bytes_per_line, (void *)(uintptr_t)(mmio + DSPSTRIDE(0)));
+ write32(0, (void *)(uintptr_t)(mmio + DSPSURF(0)));
for (i = 0; i < 0x100; i++)
- write32(mmio + LGC_PALETTE(0) + 4 * i, i * 0x010101);
+ write32(i * 0x010101,
+ (void *)(uintptr_t)(mmio + LGC_PALETTE(0) + 4 * i));
#endif
/* Find suitable divisors. */
@@ -272,159 +273,140 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info,
120000 * (5 * pixel_m1 + pixel_m2) / pixel_n
/ (pixel_p1 * 7));
- write32(mmio + LVDS,
- (hpolarity << 20) | (vpolarity << 21)
- | (info->gfx.lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL
- | LVDS_CLOCK_BOTH_POWERUP_ALL : 0)
- | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL);
+ write32((hpolarity << 20) | (vpolarity << 21) | (info->gfx.lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL,
+ (void *)(uintptr_t)(mmio + LVDS));
mdelay(1);
- write32(mmio + PP_CONTROL, PANEL_UNLOCK_REGS
- | (read32(mmio + PP_CONTROL) & ~PANEL_UNLOCK_MASK));
- write32(mmio + FP0(0),
- ((pixel_n - 2) << 16)
- | ((pixel_m1 - 2) << 8) | pixel_m2);
- write32(mmio + DPLL(0),
- DPLL_VCO_ENABLE | DPLLB_MODE_LVDS
- | (info->gfx.lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7
- : DPLLB_LVDS_P2_CLOCK_DIV_14)
- | (0x10000 << (pixel_p1 - 1))
- | ((info->gfx.use_spread_spectrum_clock ? 3 : 0) << 13)
- | (0x1 << (pixel_p1 - 1)));
+ write32(PANEL_UNLOCK_REGS | (read32((void *)(uintptr_t)(mmio + PP_CONTROL)) & ~PANEL_UNLOCK_MASK),
+ (void *)(uintptr_t)(mmio + PP_CONTROL));
+ write32(((pixel_n - 2) << 16) | ((pixel_m1 - 2) << 8) | pixel_m2,
+ (void *)(uintptr_t)(mmio + FP0(0)));
+ write32(DPLL_VCO_ENABLE | DPLLB_MODE_LVDS | (info->gfx.lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 : DPLLB_LVDS_P2_CLOCK_DIV_14) | (0x10000 << (pixel_p1 - 1)) | ((info->gfx.use_spread_spectrum_clock ? 3 : 0) << 13) | (0x1 << (pixel_p1 - 1)),
+ (void *)(uintptr_t)(mmio + DPLL(0)));
mdelay(1);
- write32(mmio + DPLL(0),
- DPLL_VCO_ENABLE | DPLLB_MODE_LVDS
- | (info->gfx.lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7
- : DPLLB_LVDS_P2_CLOCK_DIV_14)
- | (0x10000 << (pixel_p1 - 1))
- | ((info->gfx.use_spread_spectrum_clock ? 3 : 0) << 13)
- | (0x1 << (pixel_p1 - 1)));
+ write32(DPLL_VCO_ENABLE | DPLLB_MODE_LVDS | (info->gfx.lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 : DPLLB_LVDS_P2_CLOCK_DIV_14) | (0x10000 << (pixel_p1 - 1)) | ((info->gfx.use_spread_spectrum_clock ? 3 : 0) << 13) | (0x1 << (pixel_p1 - 1)),
+ (void *)(uintptr_t)(mmio + DPLL(0)));
/* Re-lock the registers. */
- write32(mmio + PP_CONTROL,
- (read32(mmio + PP_CONTROL) & ~PANEL_UNLOCK_MASK));
-
- write32(mmio + LVDS,
- (hpolarity << 20) | (vpolarity << 21)
- | (info->gfx.lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL
- | LVDS_CLOCK_BOTH_POWERUP_ALL : 0)
- | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL);
-
- write32(mmio + HTOTAL(0),
- ((hactive + right_border + hblank - 1) << 16)
- | (hactive - 1));
- write32(mmio + HBLANK(0),
- ((hactive + right_border + hblank - 1) << 16)
- | (hactive + right_border - 1));
- write32(mmio + HSYNC(0),
- ((hactive + right_border + hfront_porch + hsync - 1) << 16)
- | (hactive + right_border + hfront_porch - 1));
-
- write32(mmio + VTOTAL(0), ((vactive + bottom_border + vblank - 1) << 16)
- | (vactive - 1));
- write32(mmio + VBLANK(0), ((vactive + bottom_border + vblank - 1) << 16)
- | (vactive + bottom_border - 1));
- write32(mmio + VSYNC(0),
- (vactive + bottom_border + vfront_porch + vsync - 1)
- | (vactive + bottom_border + vfront_porch - 1));
-
- write32(mmio + PIPECONF(0), PIPECONF_DISABLE);
-
- write32(mmio + PF_WIN_POS(0), 0);
+ write32((read32((void *)(uintptr_t)(mmio + PP_CONTROL)) & ~PANEL_UNLOCK_MASK),
+ (void *)(uintptr_t)(mmio + PP_CONTROL));
+
+ write32((hpolarity << 20) | (vpolarity << 21) | (info->gfx.lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL,
+ (void *)(uintptr_t)(mmio + LVDS));
+
+ write32(((hactive + right_border + hblank - 1) << 16) | (hactive - 1),
+ (void *)(uintptr_t)(mmio + HTOTAL(0)));
+ write32(((hactive + right_border + hblank - 1) << 16) | (hactive + right_border - 1),
+ (void *)(uintptr_t)(mmio + HBLANK(0)));
+ write32(((hactive + right_border + hfront_porch + hsync - 1) << 16) | (hactive + right_border + hfront_porch - 1),
+ (void *)(uintptr_t)(mmio + HSYNC(0)));
+
+ write32(((vactive + bottom_border + vblank - 1) << 16) | (vactive - 1),
+ (void *)(uintptr_t)(mmio + VTOTAL(0)));
+ write32(((vactive + bottom_border + vblank - 1) << 16) | (vactive + bottom_border - 1),
+ (void *)(uintptr_t)(mmio + VBLANK(0)));
+ write32((vactive + bottom_border + vfront_porch + vsync - 1) | (vactive + bottom_border + vfront_porch - 1),
+ (void *)(uintptr_t)(mmio + VSYNC(0)));
+
+ write32(PIPECONF_DISABLE, (void *)(uintptr_t)(mmio + PIPECONF(0)));
+
+ write32(0, (void *)(uintptr_t)(mmio + PF_WIN_POS(0)));
#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
- write32(mmio + PIPESRC(0), ((hactive - 1) << 16) | (vactive - 1));
- write32(mmio + PF_CTL(0),0);
- write32(mmio + PF_WIN_SZ(0), 0);
- write32(mmio + PFIT_CONTROL, 0x20000000);
+ write32(((hactive - 1) << 16) | (vactive - 1),
+ (void *)(uintptr_t)(mmio + PIPESRC(0)));
+ write32(0, (void *)(uintptr_t)(mmio + PF_CTL(0)));
+ write32(0, (void *)(uintptr_t)(mmio + PF_WIN_SZ(0)));
+ write32(0x20000000, (void *)(uintptr_t)(mmio + PFIT_CONTROL));
#else
- write32(mmio + PIPESRC(0), (639 << 16) | 399);
- write32(mmio + PF_CTL(0),PF_ENABLE | PF_FILTER_MED_3x3);
- write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16));
- write32(mmio + PFIT_CONTROL, 0xa0000000);
+ write32((639 << 16) | 399, (void *)(uintptr_t)(mmio + PIPESRC(0)));
+ write32(PF_ENABLE | PF_FILTER_MED_3x3,
+ (void *)(uintptr_t)(mmio + PF_CTL(0)));
+ write32(vactive | (hactive << 16),
+ (void *)(uintptr_t)(mmio + PF_WIN_SZ(0)));
+ write32(0xa0000000, (void *)(uintptr_t)(mmio + PFIT_CONTROL));
#endif
mdelay(1);
- write32(mmio + PIPE_DATA_M1(0), 0x7e000000 | data_m1);
- write32(mmio + PIPE_DATA_N1(0), data_n1);
- write32(mmio + PIPE_LINK_M1(0), link_m1);
- write32(mmio + PIPE_LINK_N1(0), link_n1);
+ write32(0x7e000000 | data_m1,
+ (void *)(uintptr_t)(mmio + PIPE_DATA_M1(0)));
+ write32(data_n1, (void *)(uintptr_t)(mmio + PIPE_DATA_N1(0)));
+ write32(link_m1, (void *)(uintptr_t)(mmio + PIPE_LINK_M1(0)));
+ write32(link_n1, (void *)(uintptr_t)(mmio + PIPE_LINK_N1(0)));
- write32(mmio + 0x000f000c, 0x00002040);
+ write32(0x00002040, (void *)(uintptr_t)(mmio + 0x000f000c));
mdelay(1);
- write32(mmio + 0x000f000c, 0x00002050);
- write32(mmio + 0x00060100, 0x00044000);
+ write32(0x00002050, (void *)(uintptr_t)(mmio + 0x000f000c));
+ write32(0x00044000, (void *)(uintptr_t)(mmio + 0x00060100));
mdelay(1);
- write32(mmio + PIPECONF(0), PIPECONF_BPP_6);
- write32(mmio + 0x000f0008, 0x00000040);
- write32(mmio + 0x000f000c, 0x00022050);
- write32(mmio + PIPECONF(0), PIPECONF_BPP_6 | PIPECONF_DITHER_EN);
- write32(mmio + PIPECONF(0), PIPECONF_ENABLE | PIPECONF_BPP_6 | PIPECONF_DITHER_EN);
+ write32(PIPECONF_BPP_6, (void *)(uintptr_t)(mmio + PIPECONF(0)));
+ write32(0x00000040, (void *)(uintptr_t)(mmio + 0x000f0008));
+ write32(0x00022050, (void *)(uintptr_t)(mmio + 0x000f000c));
+ write32(PIPECONF_BPP_6 | PIPECONF_DITHER_EN,
+ (void *)(uintptr_t)(mmio + PIPECONF(0)));
+ write32(PIPECONF_ENABLE | PIPECONF_BPP_6 | PIPECONF_DITHER_EN,
+ (void *)(uintptr_t)(mmio + PIPECONF(0)));
#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
- write32(mmio + VGACNTRL, 0x22c4008e | VGA_DISP_DISABLE);
- write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888);
+ write32(0x22c4008e | VGA_DISP_DISABLE,
+ (void *)(uintptr_t)(mmio + VGACNTRL));
+ write32(DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888,
+ (void *)(uintptr_t)(mmio + DSPCNTR(0)));
mdelay(1);
#else
- write32(mmio + VGACNTRL, 0x22c4008e);
+ write32(0x22c4008e, (void *)(uintptr_t)(mmio + VGACNTRL));
#endif
- write32(mmio + TRANS_HTOTAL(0),
- ((hactive + right_border + hblank - 1) << 16)
- | (hactive - 1));
- write32(mmio + TRANS_HBLANK(0),
- ((hactive + right_border + hblank - 1) << 16)
- | (hactive + right_border - 1));
- write32(mmio + TRANS_HSYNC(0),
- ((hactive + right_border + hfront_porch + hsync - 1) << 16)
- | (hactive + right_border + hfront_porch - 1));
-
- write32(mmio + TRANS_VTOTAL(0),
- ((vactive + bottom_border + vblank - 1) << 16)
- | (vactive - 1));
- write32(mmio + TRANS_VBLANK(0),
- ((vactive + bottom_border + vblank - 1) << 16)
- | (vactive + bottom_border - 1));
- write32(mmio + TRANS_VSYNC(0),
- (vactive + bottom_border + vfront_porch + vsync - 1)
- | (vactive + bottom_border + vfront_porch - 1));
-
- write32(mmio + 0x00060100, 0xb01c4000);
- write32(mmio + 0x000f000c, 0xb01a2050);
+ write32(((hactive + right_border + hblank - 1) << 16) | (hactive - 1),
+ (void *)(uintptr_t)(mmio + TRANS_HTOTAL(0)));
+ write32(((hactive + right_border + hblank - 1) << 16) | (hactive + right_border - 1),
+ (void *)(uintptr_t)(mmio + TRANS_HBLANK(0)));
+ write32(((hactive + right_border + hfront_porch + hsync - 1) << 16) | (hactive + right_border + hfront_porch - 1),
+ (void *)(uintptr_t)(mmio + TRANS_HSYNC(0)));
+
+ write32(((vactive + bottom_border + vblank - 1) << 16) | (vactive - 1),
+ (void *)(uintptr_t)(mmio + TRANS_VTOTAL(0)));
+ write32(((vactive + bottom_border + vblank - 1) << 16) | (vactive + bottom_border - 1),
+ (void *)(uintptr_t)(mmio + TRANS_VBLANK(0)));
+ write32((vactive + bottom_border + vfront_porch + vsync - 1) | (vactive + bottom_border + vfront_porch - 1),
+ (void *)(uintptr_t)(mmio + TRANS_VSYNC(0)));
+
+ write32(0xb01c4000, (void *)(uintptr_t)(mmio + 0x00060100));
+ write32(0xb01a2050, (void *)(uintptr_t)(mmio + 0x000f000c));
mdelay(1);
- write32(mmio + TRANSCONF(0), TRANS_ENABLE | TRANS_6BPC
+ write32(TRANS_ENABLE | TRANS_6BPC
#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
- | TRANS_STATE_MASK
+
+ | TRANS_STATE_MASK
#endif
- );
- write32(mmio + LVDS,
- LVDS_PORT_ENABLE
- | (hpolarity << 20) | (vpolarity << 21)
- | (info->gfx.lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL
- | LVDS_CLOCK_BOTH_POWERUP_ALL : 0)
- | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL);
-
- write32(mmio + PP_CONTROL, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
- write32(mmio + PP_CONTROL, PANEL_UNLOCK_REGS | PANEL_POWER_RESET);
+, (void *)(uintptr_t)(mmio + TRANSCONF(0)));
+ write32(LVDS_PORT_ENABLE | (hpolarity << 20) | (vpolarity << 21) | (info->gfx.lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL,
+ (void *)(uintptr_t)(mmio + LVDS));
+
+ write32(PANEL_UNLOCK_REGS | PANEL_POWER_OFF,
+ (void *)(uintptr_t)(mmio + PP_CONTROL));
+ write32(PANEL_UNLOCK_REGS | PANEL_POWER_RESET,
+ (void *)(uintptr_t)(mmio + PP_CONTROL));
mdelay(1);
- write32(mmio + PP_CONTROL, PANEL_UNLOCK_REGS
- | PANEL_POWER_ON | PANEL_POWER_RESET);
+ write32(PANEL_UNLOCK_REGS | PANEL_POWER_ON | PANEL_POWER_RESET,
+ (void *)(uintptr_t)(mmio + PP_CONTROL));
printk (BIOS_DEBUG, "waiting for panel powerup\n");
while (1) {
u32 reg32;
- reg32 = read32(mmio + PP_STATUS);
+ reg32 = read32((void *)(uintptr_t)(mmio + PP_STATUS));
if (((reg32 >> 28) & 3) == 0)
break;
}
printk (BIOS_DEBUG, "panel powered up\n");
- write32(mmio + PP_CONTROL, PANEL_POWER_ON | PANEL_POWER_RESET);
+ write32(PANEL_POWER_ON | PANEL_POWER_RESET,
+ (void *)(uintptr_t)(mmio + PP_CONTROL));
/* Enable screen memory. */
vga_sr_write(1, vga_sr_read(1) & ~0x20);
/* Clear interrupts. */
- write32(mmio + DEIIR, 0xffffffff);
- write32(mmio + SDEIIR, 0xffffffff);
+ write32(0xffffffff, (void *)(uintptr_t)(mmio + DEIIR));
+ write32(0xffffffff, (void *)(uintptr_t)(mmio + SDEIIR));
#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
memset ((void *) lfb, 0, edid.x_resolution * edid.y_resolution * 4);
diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c
index 60b05bd..487ecc0 100644
--- a/src/northbridge/intel/gm45/raminit.c
+++ b/src/northbridge/intel/gm45/raminit.c
@@ -1579,15 +1579,15 @@ static void jedec_init(const timings_t *const timings,
const u32 rankaddr = raminit_get_rank_addr(ch, r);
printk(BIOS_DEBUG, "Performing Jedec initialization at address 0x%08x.\n", rankaddr);
MCHBAR32(DCC_MCHBAR) = (MCHBAR32(DCC_MCHBAR) & ~DCC_SET_EREG_MASK) | DCC_SET_EREGx(2);
- read32(rankaddr | WL);
+ read32((void *)(uintptr_t)(rankaddr | WL));
MCHBAR32(DCC_MCHBAR) = (MCHBAR32(DCC_MCHBAR) & ~DCC_SET_EREG_MASK) | DCC_SET_EREGx(3);
- read32(rankaddr);
+ read32((void *)(uintptr_t)(rankaddr));
MCHBAR32(DCC_MCHBAR) = (MCHBAR32(DCC_MCHBAR) & ~DCC_SET_EREG_MASK) | DCC_SET_EREGx(1);
- read32(rankaddr | ODT_120OHMS | ODS_34OHMS);
+ read32((void *)(uintptr_t)(rankaddr | ODT_120OHMS | ODS_34OHMS));
MCHBAR32(DCC_MCHBAR) = (MCHBAR32(DCC_MCHBAR) & ~DCC_CMD_MASK) | DCC_SET_MREG;
- read32(rankaddr | WR | DLL1 | CAS | INTERLEAVED);
+ read32((void *)(uintptr_t)(rankaddr | WR | DLL1 | CAS | INTERLEAVED));
MCHBAR32(DCC_MCHBAR) = (MCHBAR32(DCC_MCHBAR) & ~DCC_CMD_MASK) | DCC_SET_MREG;
- read32(rankaddr | WR | CAS | INTERLEAVED);
+ read32((void *)(uintptr_t)(rankaddr | WR | CAS | INTERLEAVED));
}
}
@@ -1701,7 +1701,7 @@ void raminit(sysinfo_t *const sysinfo, const int s3resume)
/* Wait for some bit, maybe TXT clear. */
if (sysinfo->txt_enabled) {
- while (!(read8(0xfed40000) & (1 << 7))) {}
+ while (!(read8((void *)(uintptr_t)(0xfed40000)) & (1 << 7))) {}
}
/* Enable SMBUS. */
diff --git a/src/northbridge/intel/gm45/raminit_read_write_training.c b/src/northbridge/intel/gm45/raminit_read_write_training.c
index 5149c2b..7af3b76 100644
--- a/src/northbridge/intel/gm45/raminit_read_write_training.c
+++ b/src/northbridge/intel/gm45/raminit_read_write_training.c
@@ -114,7 +114,7 @@ static int read_training_test(const int channel, const int lane,
for (i = 0; i < addresses->count; ++i) {
unsigned int offset;
for (offset = lane_offset; offset < 320; offset += 8) {
- const u32 read = read32(addresses->addr[i] + offset);
+ const u32 read = read32((void *)(uintptr_t)(addresses->addr[i] + offset));
const u32 good = read_training_schedule[offset >> 3];
if ((read & lane_mask) != (good & lane_mask))
return 0;
@@ -228,8 +228,8 @@ static void perform_read_training(const dimminfo_t *const dimms)
/* Write test pattern. */
unsigned int offset;
for (offset = 0; offset < 320; offset += 4)
- write32(addresses.addr[i] + offset,
- read_training_schedule[offset >> 3]);
+ write32(read_training_schedule[offset >> 3],
+ (void *)(uintptr_t)(addresses.addr[i] + offset));
}
for (i = 0; i < 8; ++i)
@@ -436,18 +436,18 @@ static int write_training_test(const address_bunch_t *const addresses,
unsigned int off;
for (off = 0; off < 640; off += 8) {
const u32 pattern = write_training_schedule[off >> 3];
- write32(addr + off, pattern);
- write32(addr + off + 4, pattern);
+ write32(pattern, (void *)(uintptr_t)(addr + off));
+ write32(pattern, (void *)(uintptr_t)(addr + off + 4));
}
MCHBAR8(0x78) |= 1;
for (off = 0; off < 640; off += 8) {
const u32 good = write_training_schedule[off >> 3];
- const u32 read1 = read32(addr + off);
+ const u32 read1 = read32((void *)(uintptr_t)(addr + off));
if ((read1 & masks[0]) != (good & masks[0]))
goto _bad_timing_out;
- const u32 read2 = read32(addr + off + 4);
+ const u32 read2 = read32((void *)(uintptr_t)(addr + off + 4));
if ((read2 & masks[1]) != (good & masks[1]))
goto _bad_timing_out;
}
diff --git a/src/northbridge/intel/gm45/raminit_receive_enable_calibration.c b/src/northbridge/intel/gm45/raminit_receive_enable_calibration.c
index 5130b59..3a865ff 100644
--- a/src/northbridge/intel/gm45/raminit_receive_enable_calibration.c
+++ b/src/northbridge/intel/gm45/raminit_receive_enable_calibration.c
@@ -147,7 +147,7 @@ static int read_dqs_level(const int channel, const int lane)
MCHBAR32(mchbar) |= (1 << 9);
/* Read from this channel. */
- read32(raminit_get_rank_addr(channel, 0));
+ read32((void *)(uintptr_t)(raminit_get_rank_addr(channel, 0)));
mchbar = 0x14b0 + (channel * 0x0100) + ((7 - lane) * 4);
return MCHBAR32(mchbar) & (1 << 30);
diff --git a/src/northbridge/intel/haswell/acpi.c b/src/northbridge/intel/haswell/acpi.c
index 488170d..38c6f8d 100644
--- a/src/northbridge/intel/haswell/acpi.c
+++ b/src/northbridge/intel/haswell/acpi.c
@@ -118,7 +118,7 @@ static int init_opregion_vbt(igd_opregion_t *opregion)
optionrom_vbt_t *vbt = (optionrom_vbt_t *)(vbios +
oprom->vbt_offset);
- if (read32((unsigned long)vbt->hdr_signature) != VBT_SIGNATURE) {
+ if (read32((void *)(uintptr_t)((unsigned long)vbt->hdr_signature)) != VBT_SIGNATURE) {
printk(BIOS_DEBUG, "VBT not found!\n");
return 1;
}
diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c
index 325edbd..76941c5 100644
--- a/src/northbridge/intel/haswell/gma.c
+++ b/src/northbridge/intel/haswell/gma.c
@@ -171,14 +171,14 @@ static struct resource *gtt_res = NULL;
u32 gtt_read(u32 reg)
{
u32 val;
- val = read32(gtt_res->base + reg);
+ val = read32((void *)(uintptr_t)(gtt_res->base + reg));
return val;
}
void gtt_write(u32 reg, u32 data)
{
- write32(gtt_res->base + reg, data);
+ write32(data, (void *)(uintptr_t)(gtt_res->base + reg));
}
static inline void gtt_rmw(u32 reg, u32 andmask, u32 ormask)
diff --git a/src/northbridge/intel/haswell/minihd.c b/src/northbridge/intel/haswell/minihd.c
index 4a38b28..599bb8b 100644
--- a/src/northbridge/intel/haswell/minihd.c
+++ b/src/northbridge/intel/haswell/minihd.c
@@ -83,15 +83,15 @@ static void minihd_init(struct device *dev)
pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER);
/* Mini-HD configuration */
- reg32 = read32(base + 0x100c);
+ reg32 = read32((void *)(uintptr_t)(base + 0x100c));
reg32 &= 0xfffc0000;
reg32 |= 0x4;
- write32(base + 0x100c, reg32);
+ write32(reg32, (void *)(uintptr_t)(base + 0x100c));
- reg32 = read32(base + 0x1010);
+ reg32 = read32((void *)(uintptr_t)(base + 0x1010));
reg32 &= 0xfffc0000;
reg32 |= 0x4b;
- write32(base + 0x1010, reg32);
+ write32(reg32, (void *)(uintptr_t)(base + 0x1010));
/* Init the codec and write the verb table */
codec_mask = hda_codec_detect(base);
diff --git a/src/northbridge/intel/i3100/raminit.c b/src/northbridge/intel/i3100/raminit.c
index 4f5a989..0cc7119 100644
--- a/src/northbridge/intel/i3100/raminit.c
+++ b/src/northbridge/intel/i3100/raminit.c
@@ -694,11 +694,12 @@ static void set_on_dimm_termination_enable(const struct mem_controller *ctrl)
for(dimm=0;dimm<8;dimm+=2) {
- write32(MCBAR+DCALADDR, 0x0b840001);
- write32(MCBAR+DCALCSR, 0x81000003 | (dimm << 20));
+ write32(0x0b840001, (void *)(uintptr_t)(MCBAR + DCALADDR));
+ write32(0x81000003 | (dimm << 20),
+ (void *)(uintptr_t)(MCBAR + DCALCSR));
for(i=0;i<1001;i++) {
- data32 = read32(MCBAR+DCALCSR);
+ data32 = read32((void *)(uintptr_t)(MCBAR + DCALCSR));
if(!(data32 & (1<<31)))
break;
}
@@ -726,27 +727,29 @@ static void set_receive_enable(const struct mem_controller *ctrl)
for(dimm=0;dimm<8;dimm+=1) {
if(!(dimm&1)) {
- write32(MCBAR+DCALDATA+(17*4), 0x04020000);
- write32(MCBAR+DCALCSR, 0x81800004 | (dimm << 20));
+ write32(0x04020000,
+ (void *)(uintptr_t)(MCBAR + DCALDATA + (17 * 4)));
+ write32(0x81800004 | (dimm << 20),
+ (void *)(uintptr_t)(MCBAR + DCALCSR));
for(i=0;i<1001;i++) {
- data32 = read32(MCBAR+DCALCSR);
+ data32 = read32((void *)(uintptr_t)(MCBAR + DCALCSR));
if(!(data32 & (1<<31)))
break;
}
if(i>=1000)
continue;
- dcal_data32_0 = read32(MCBAR+DCALDATA + 0);
- dcal_data32_1 = read32(MCBAR+DCALDATA + 4);
- dcal_data32_2 = read32(MCBAR+DCALDATA + 8);
- dcal_data32_3 = read32(MCBAR+DCALDATA + 12);
+ dcal_data32_0 = read32((void *)(uintptr_t)(MCBAR + DCALDATA + 0));
+ dcal_data32_1 = read32((void *)(uintptr_t)(MCBAR + DCALDATA + 4));
+ dcal_data32_2 = read32((void *)(uintptr_t)(MCBAR + DCALDATA + 8));
+ dcal_data32_3 = read32((void *)(uintptr_t)(MCBAR + DCALDATA + 12));
}
else {
- dcal_data32_0 = read32(MCBAR+DCALDATA + 16);
- dcal_data32_1 = read32(MCBAR+DCALDATA + 20);
- dcal_data32_2 = read32(MCBAR+DCALDATA + 24);
- dcal_data32_3 = read32(MCBAR+DCALDATA + 28);
+ dcal_data32_0 = read32((void *)(uintptr_t)(MCBAR + DCALDATA + 16));
+ dcal_data32_1 = read32((void *)(uintptr_t)(MCBAR + DCALDATA + 20));
+ dcal_data32_2 = read32((void *)(uintptr_t)(MCBAR + DCALDATA + 24));
+ dcal_data32_3 = read32((void *)(uintptr_t)(MCBAR + DCALDATA + 28));
}
/* check if bank is installed */
@@ -923,16 +926,16 @@ static void set_receive_enable(const struct mem_controller *ctrl)
print_debug("\n");
/* clear out the calibration area */
- write32(MCBAR+DCALDATA+(16*4), 0x00000000);
- write32(MCBAR+DCALDATA+(17*4), 0x00000000);
- write32(MCBAR+DCALDATA+(18*4), 0x00000000);
- write32(MCBAR+DCALDATA+(19*4), 0x00000000);
+ write32(0x00000000, (void *)(uintptr_t)(MCBAR + DCALDATA + (16 * 4)));
+ write32(0x00000000, (void *)(uintptr_t)(MCBAR + DCALDATA + (17 * 4)));
+ write32(0x00000000, (void *)(uintptr_t)(MCBAR + DCALDATA + (18 * 4)));
+ write32(0x00000000, (void *)(uintptr_t)(MCBAR + DCALDATA + (19 * 4)));
/* No command */
- write32(MCBAR+DCALCSR, 0x0000000f);
+ write32(0x0000000f, (void *)(uintptr_t)(MCBAR + DCALCSR));
- write32(MCBAR+0x150, recena);
- write32(MCBAR+0x154, recenb);
+ write32(recena, (void *)(uintptr_t)(MCBAR + 0x150));
+ write32(recenb, (void *)(uintptr_t)(MCBAR + 0x154));
}
@@ -1019,10 +1022,12 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
/* Apply NOP */
do_delay();
- write32(MCBAR+DCALCSR, (0x01000000 | (i<<20)));
- write32(MCBAR+DCALCSR, (0x81000000 | (i<<20)));
+ write32((0x01000000 | (i << 20)),
+ (void *)(uintptr_t)(MCBAR + DCALCSR));
+ write32((0x81000000 | (i << 20)),
+ (void *)(uintptr_t)(MCBAR + DCALCSR));
- do data32 = read32(MCBAR+DCALCSR);
+ do data32 = read32((void *)(uintptr_t)(MCBAR + DCALCSR));
while(data32 & 0x80000000);
}
@@ -1030,17 +1035,19 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
do_delay();
for(cs=0;cs<8;cs+=2) {
- write32(MCBAR + DCALCSR, (0x81000000 | (cs<<20)));
- do data32 = read32(MCBAR+DCALCSR);
+ write32((0x81000000 | (cs << 20)),
+ (void *)(uintptr_t)(MCBAR + DCALCSR));
+ do data32 = read32((void *)(uintptr_t)(MCBAR + DCALCSR));
while(data32 & 0x80000000);
}
/* Precharg all banks */
do_delay();
for(cs=0;cs<8;cs+=2) {
- write32(MCBAR+DCALADDR, 0x04000000);
- write32(MCBAR+DCALCSR, (0x81000002 | (cs<<20)));
- do data32 = read32(MCBAR+DCALCSR);
+ write32(0x04000000, (void *)(uintptr_t)(MCBAR + DCALADDR));
+ write32((0x81000002 | (cs << 20)),
+ (void *)(uintptr_t)(MCBAR + DCALCSR));
+ do data32 = read32((void *)(uintptr_t)(MCBAR + DCALCSR));
while(data32 & 0x80000000);
}
@@ -1048,9 +1055,10 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
do_delay();
for(cs=0;cs<8;cs+=2) {
/* fixme hard code AL additive latency */
- write32(MCBAR+DCALADDR, 0x0b940001);
- write32(MCBAR+DCALCSR, (0x81000003 | (cs<<20)));
- do data32 = read32(MCBAR+DCALCSR);
+ write32(0x0b940001, (void *)(uintptr_t)(MCBAR + DCALADDR));
+ write32((0x81000003 | (cs << 20)),
+ (void *)(uintptr_t)(MCBAR + DCALCSR));
+ do data32 = read32((void *)(uintptr_t)(MCBAR + DCALCSR));
while(data32 & 0x80000000);
}
/* MRS reset dll's */
@@ -1060,9 +1068,10 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
else
mode_reg = 0x054a0000;
for(cs=0;cs<8;cs+=2) {
- write32(MCBAR+DCALADDR, mode_reg);
- write32(MCBAR+DCALCSR, (0x81000003 | (cs<<20)));
- do data32 = read32(MCBAR+DCALCSR);
+ write32(mode_reg, (void *)(uintptr_t)(MCBAR + DCALADDR));
+ write32((0x81000003 | (cs << 20)),
+ (void *)(uintptr_t)(MCBAR + DCALCSR));
+ do data32 = read32((void *)(uintptr_t)(MCBAR + DCALCSR));
while(data32 & 0x80000000);
}
@@ -1071,72 +1080,84 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
do_delay();
do_delay();
for(cs=0;cs<8;cs+=2) {
- write32(MCBAR+DCALADDR, 0x04000000);
- write32(MCBAR+DCALCSR, (0x81000002 | (cs<<20)));
- do data32 = read32(MCBAR+DCALCSR);
+ write32(0x04000000, (void *)(uintptr_t)(MCBAR + DCALADDR));
+ write32((0x81000002 | (cs << 20)),
+ (void *)(uintptr_t)(MCBAR + DCALCSR));
+ do data32 = read32((void *)(uintptr_t)(MCBAR + DCALCSR));
while(data32 & 0x80000000);
}
/* Do 2 refreshes */
do_delay();
for(cs=0;cs<8;cs+=2) {
- write32(MCBAR+DCALCSR, (0x81000001 | (cs<<20)));
- do data32 = read32(MCBAR+DCALCSR);
+ write32((0x81000001 | (cs << 20)),
+ (void *)(uintptr_t)(MCBAR + DCALCSR));
+ do data32 = read32((void *)(uintptr_t)(MCBAR + DCALCSR));
while(data32 & 0x80000000);
}
do_delay();
for(cs=0;cs<8;cs+=2) {
- write32(MCBAR+DCALCSR, (0x81000001 | (cs<<20)));
- do data32 = read32(MCBAR+DCALCSR);
+ write32((0x81000001 | (cs << 20)),
+ (void *)(uintptr_t)(MCBAR + DCALCSR));
+ do data32 = read32((void *)(uintptr_t)(MCBAR + DCALCSR));
while(data32 & 0x80000000);
}
do_delay();
/* for good luck do 6 more */
for(cs=0;cs<8;cs+=2) {
- write32(MCBAR+DCALCSR, (0x81000001 | (cs<<20)));
+ write32((0x81000001 | (cs << 20)),
+ (void *)(uintptr_t)(MCBAR + DCALCSR));
}
do_delay();
for(cs=0;cs<8;cs+=2) {
- write32(MCBAR+DCALCSR, (0x81000001 | (cs<<20)));
+ write32((0x81000001 | (cs << 20)),
+ (void *)(uintptr_t)(MCBAR + DCALCSR));
}
do_delay();
for(cs=0;cs<8;cs+=2) {
- write32(MCBAR+DCALCSR, (0x81000001 | (cs<<20)));
+ write32((0x81000001 | (cs << 20)),
+ (void *)(uintptr_t)(MCBAR + DCALCSR));
}
do_delay();
for(cs=0;cs<8;cs+=2) {
- write32(MCBAR+DCALCSR, (0x81000001 | (cs<<20)));
+ write32((0x81000001 | (cs << 20)),
+ (void *)(uintptr_t)(MCBAR + DCALCSR));
}
do_delay();
for(cs=0;cs<8;cs+=2) {
- write32(MCBAR+DCALCSR, (0x81000001 | (cs<<20)));
+ write32((0x81000001 | (cs << 20)),
+ (void *)(uintptr_t)(MCBAR + DCALCSR));
}
do_delay();
for(cs=0;cs<8;cs+=2) {
- write32(MCBAR+DCALCSR, (0x81000001 | (cs<<20)));
+ write32((0x81000001 | (cs << 20)),
+ (void *)(uintptr_t)(MCBAR + DCALCSR));
}
do_delay();
/* MRS reset dll's normal */
do_delay();
for(cs=0;cs<8;cs+=2) {
- write32(MCBAR+DCALADDR, (mode_reg & ~(1<<24)));
- write32(MCBAR+DCALCSR, (0x81000003 | (cs<<20)));
- do data32 = read32(MCBAR+DCALCSR);
+ write32((mode_reg & ~(1 << 24)),
+ (void *)(uintptr_t)(MCBAR + DCALADDR));
+ write32((0x81000003 | (cs << 20)),
+ (void *)(uintptr_t)(MCBAR + DCALCSR));
+ do data32 = read32((void *)(uintptr_t)(MCBAR + DCALCSR));
while(data32 & 0x80000000);
}
/* Do only if DDR2 EMRS dll's enabled */
do_delay();
for(cs=0;cs<8;cs+=2) {
- write32(MCBAR+DCALADDR, (0x0b940001));
- write32(MCBAR+DCALCSR, (0x81000003 | (cs<<20)));
- do data32 = read32(MCBAR+DCALCSR);
+ write32((0x0b940001), (void *)(uintptr_t)(MCBAR + DCALADDR));
+ write32((0x81000003 | (cs << 20)),
+ (void *)(uintptr_t)(MCBAR + DCALCSR));
+ do data32 = read32((void *)(uintptr_t)(MCBAR + DCALCSR));
while(data32 & 0x80000000);
}
do_delay();
/* No command */
- write32(MCBAR+DCALCSR, 0x0000000f);
+ write32(0x0000000f, (void *)(uintptr_t)(MCBAR + DCALCSR));
/* enable on dimm termination */
set_on_dimm_termination_enable(ctrl);
@@ -1147,7 +1168,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
/* DQS */
pci_write_config32(ctrl->f0, 0x94, 0x3904aa00);
for(i = 0, cnt = (MCBAR+0x200); i < 24; i++, cnt+=4) {
- write32(cnt, dqs_data[i]);
+ write32(dqs_data[i], (void *)(uintptr_t)(cnt));
}
pci_write_config32(ctrl->f0, 0x94, 0x3900aa00);
@@ -1155,17 +1176,18 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
/* 0x7c DRC */
data32 = drc & ~(3 << 20); /* clear ECC mode */
pci_write_config32(ctrl->f0, DRC, data32);
- write32(MCBAR+DCALCSR, 0x0008000f);
+ write32(0x0008000f, (void *)(uintptr_t)(MCBAR + DCALCSR));
/* clear memory and init ECC */
print_debug("Clearing memory\n");
for(i=0;i<64;i+=4) {
- write32(MCBAR+DCALDATA+i, 0x00000000);
+ write32(0x00000000, (void *)(uintptr_t)(MCBAR + DCALDATA + i));
}
for(cs=0;cs<8;cs+=2) {
- write32(MCBAR+DCALCSR, (0x810831d8 | (cs<<20)));
- do data32 = read32(MCBAR+DCALCSR);
+ write32((0x810831d8 | (cs << 20)),
+ (void *)(uintptr_t)(MCBAR + DCALCSR));
+ do data32 = read32((void *)(uintptr_t)(MCBAR + DCALCSR));
while(data32 & 0x80000000);
}
diff --git a/src/northbridge/intel/i3100/raminit_ep80579.c b/src/northbridge/intel/i3100/raminit_ep80579.c
index 962b7aa..95dc826 100644
--- a/src/northbridge/intel/i3100/raminit_ep80579.c
+++ b/src/northbridge/intel/i3100/raminit_ep80579.c
@@ -533,9 +533,10 @@ static void set_on_dimm_termination_enable(const struct mem_controller *ctrl)
print_debug_hex8(i);
print_debug("\n");
- write32(BAR+DCALADDR, 0x0b840001);
- write32(BAR+DCALCSR, 0x80000003 | ((i+1)<<21));
- do data32 = read32(BAR+DCALCSR);
+ write32(0x0b840001, (void *)(uintptr_t)(BAR + DCALADDR));
+ write32(0x80000003 | ((i + 1) << 21),
+ (void *)(uintptr_t)(BAR + DCALCSR));
+ do data32 = read32((void *)(uintptr_t)(BAR + DCALCSR));
while (data32 & 0x80000000);
}
}
@@ -550,7 +551,7 @@ static void dump_dcal_regs(void)
print_debug_hex16(i);
print_debug(": ");
}
- print_debug_hex32(read32(BAR+i));
+ print_debug_hex32(read32((void *)(uintptr_t)(BAR + i)));
print_debug(" ");
}
print_debug("\n");
@@ -601,9 +602,11 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
print_debug_hex8(cs);
print_debug("\n");
udelay(16);
- write32(BAR+DCALCSR, (0x00000000 | ((cs+1)<<21)));
- write32(BAR+DCALCSR, (0x80000000 | ((cs+1)<<21)));
- do data32 = read32(BAR+DCALCSR);
+ write32((0x00000000 | ((cs + 1) << 21)),
+ (void *)(uintptr_t)(BAR + DCALCSR));
+ write32((0x80000000 | ((cs + 1) << 21)),
+ (void *)(uintptr_t)(BAR + DCALCSR));
+ do data32 = read32((void *)(uintptr_t)(BAR + DCALCSR));
while (data32 & 0x80000000);
}
@@ -613,8 +616,9 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
print_debug("NOP CS");
print_debug_hex8(cs);
print_debug("\n");
- write32(BAR + DCALCSR, (0x80000000 | ((cs+1)<<21)));
- do data32 = read32(BAR+DCALCSR);
+ write32((0x80000000 | ((cs + 1) << 21)),
+ (void *)(uintptr_t)(BAR + DCALCSR));
+ do data32 = read32((void *)(uintptr_t)(BAR + DCALCSR));
while (data32 & 0x80000000);
}
@@ -624,9 +628,10 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
print_debug("Precharge CS");
print_debug_hex8(cs);
print_debug("\n");
- write32(BAR+DCALADDR, 0x04000000);
- write32(BAR+DCALCSR, (0x80000002 | ((cs+1)<<21)));
- do data32 = read32(BAR+DCALCSR);
+ write32(0x04000000, (void *)(uintptr_t)(BAR + DCALADDR));
+ write32((0x80000002 | ((cs + 1) << 21)),
+ (void *)(uintptr_t)(BAR + DCALCSR));
+ do data32 = read32((void *)(uintptr_t)(BAR + DCALCSR));
while (data32 & 0x80000000);
}
@@ -636,9 +641,10 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
print_debug("EMRS CS");
print_debug_hex8(cs);
print_debug("\n");
- write32(BAR+DCALADDR, 0x0b840001);
- write32(BAR+DCALCSR, (0x80000003 | ((cs+1)<<21)));
- do data32 = read32(BAR+DCALCSR);
+ write32(0x0b840001, (void *)(uintptr_t)(BAR + DCALADDR));
+ write32((0x80000003 | ((cs + 1) << 21)),
+ (void *)(uintptr_t)(BAR + DCALCSR));
+ do data32 = read32((void *)(uintptr_t)(BAR + DCALCSR));
while (data32 & 0x80000000);
}
/* MRS: Reset DLLs */
@@ -647,9 +653,10 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
print_debug("MRS CS");
print_debug_hex8(cs);
print_debug("\n");
- write32(BAR+DCALADDR, mode_reg);
- write32(BAR+DCALCSR, (0x80000003 | ((cs+1)<<21)));
- do data32 = read32(BAR+DCALCSR);
+ write32(mode_reg, (void *)(uintptr_t)(BAR + DCALADDR));
+ write32((0x80000003 | ((cs + 1) << 21)),
+ (void *)(uintptr_t)(BAR + DCALCSR));
+ do data32 = read32((void *)(uintptr_t)(BAR + DCALCSR));
while (data32 & 0x80000000);
}
@@ -659,9 +666,10 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
print_debug("Precharge CS");
print_debug_hex8(cs);
print_debug("\n");
- write32(BAR+DCALADDR, 0x04000000);
- write32(BAR+DCALCSR, (0x80000002 | ((cs+1)<<21)));
- do data32 = read32(BAR+DCALCSR);
+ write32(0x04000000, (void *)(uintptr_t)(BAR + DCALADDR));
+ write32((0x80000002 | ((cs + 1) << 21)),
+ (void *)(uintptr_t)(BAR + DCALCSR));
+ do data32 = read32((void *)(uintptr_t)(BAR + DCALCSR));
while (data32 & 0x80000000);
}
@@ -672,8 +680,9 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
print_debug("Refresh CS");
print_debug_hex8(cs);
print_debug("\n");
- write32(BAR+DCALCSR, (0x80000001 | ((cs+1)<<21)));
- do data32 = read32(BAR+DCALCSR);
+ write32((0x80000001 | ((cs + 1) << 21)),
+ (void *)(uintptr_t)(BAR + DCALCSR));
+ do data32 = read32((void *)(uintptr_t)(BAR + DCALCSR));
while (data32 & 0x80000000);
}
}
@@ -684,9 +693,11 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
print_debug("MRS CS");
print_debug_hex8(cs);
print_debug("\n");
- write32(BAR+DCALADDR, (mode_reg & ~(1<<24)));
- write32(BAR+DCALCSR, (0x80000003 | ((cs+1)<<21)));
- do data32 = read32(BAR+DCALCSR);
+ write32((mode_reg & ~(1 << 24)),
+ (void *)(uintptr_t)(BAR + DCALADDR));
+ write32((0x80000003 | ((cs + 1) << 21)),
+ (void *)(uintptr_t)(BAR + DCALCSR));
+ do data32 = read32((void *)(uintptr_t)(BAR + DCALCSR));
while (data32 & 0x80000000);
}
@@ -696,17 +707,18 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
print_debug("EMRS CS");
print_debug_hex8(cs);
print_debug("\n");
- write32(BAR+DCALADDR, 0x0b840001);
- write32(BAR+DCALCSR, (0x80000003 | ((cs+1)<<21)));
- do data32 = read32(BAR+DCALCSR);
+ write32(0x0b840001, (void *)(uintptr_t)(BAR + DCALADDR));
+ write32((0x80000003 | ((cs + 1) << 21)),
+ (void *)(uintptr_t)(BAR + DCALCSR));
+ do data32 = read32((void *)(uintptr_t)(BAR + DCALCSR));
while (data32 & 0x80000000);
}
udelay(16);
/* No command */
- write32(BAR+DCALCSR, 0x0000000f);
+ write32(0x0000000f, (void *)(uintptr_t)(BAR + DCALCSR));
- write32(BAR, 0x00100000);
+ write32(0x00100000, (void *)(uintptr_t)(BAR));
/* Enable on-DIMM termination */
set_on_dimm_termination_enable(ctrl);
@@ -719,24 +731,25 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
print_debug("receive enable calibration CS");
print_debug_hex8(cs);
print_debug("\n");
- write32(BAR+DCALCSR, (0x8000000c | ((cs+1)<<21)));
- do data32 = read32(BAR+DCALCSR);
+ write32((0x8000000c | ((cs + 1) << 21)),
+ (void *)(uintptr_t)(BAR + DCALCSR));
+ do data32 = read32((void *)(uintptr_t)(BAR + DCALCSR));
while (data32 & 0x80000000);
}
dump_dcal_regs();
/* Adjust RCOMP */
- data32 = read32(BAR+DDRIOMC2);
+ data32 = read32((void *)(uintptr_t)(BAR + DDRIOMC2));
data32 &= ~(0xf << 16);
data32 |= (0xb << 16);
- write32(BAR+DDRIOMC2, data32);
+ write32(data32, (void *)(uintptr_t)(BAR + DDRIOMC2));
dump_dcal_regs();
data32 = drc & ~(3 << 20); /* clear ECC mode */
pci_write_config32(ctrl->f0, DRC, data32);
- write32(BAR+DCALCSR, 0x0008000f);
+ write32(0x0008000f, (void *)(uintptr_t)(BAR + DCALCSR));
/* Clear memory and init ECC */
for (cs = 0; cs < 2; cs++) {
@@ -745,8 +758,9 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
print_debug("clear memory CS");
print_debug_hex8(cs);
print_debug("\n");
- write32(BAR+MBCSR, 0xa00000f0 | ((cs+1)<<20) | (0<<16));
- do data32 = read32(BAR+MBCSR);
+ write32(0xa00000f0 | ((cs + 1) << 20) | (0 << 16),
+ (void *)(uintptr_t)(BAR + MBCSR));
+ do data32 = read32((void *)(uintptr_t)(BAR + MBCSR));
while (data32 & 0x80000000);
if (data32 & 0x40000000)
print_debug("failed!\n");
@@ -754,9 +768,11 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
/* Clear read/write FIFO pointers */
print_debug("clear read/write fifo pointers\n");
- write32(BAR+DDRIOMC2, read32(BAR+DDRIOMC2) | (1<<15));
+ write32(read32((void *)(uintptr_t)(BAR + DDRIOMC2)) | (1 << 15),
+ (void *)(uintptr_t)(BAR + DDRIOMC2));
udelay(16);
- write32(BAR+DDRIOMC2, read32(BAR+DDRIOMC2) & ~(1<<15));
+ write32(read32((void *)(uintptr_t)(BAR + DDRIOMC2)) & ~(1 << 15),
+ (void *)(uintptr_t)(BAR + DDRIOMC2));
udelay(16);
dump_dcal_regs();
diff --git a/src/northbridge/intel/i440bx/raminit.c b/src/northbridge/intel/i440bx/raminit.c
index e3cfbdf..4c70189 100644
--- a/src/northbridge/intel/i440bx/raminit.c
+++ b/src/northbridge/intel/i440bx/raminit.c
@@ -431,7 +431,7 @@ static void do_ram_command(u32 command)
reg16, addr);
#endif
- read32(addr);
+ read32((void *)(uintptr_t)(addr));
}
/* Set the start of the next DIMM. */
diff --git a/src/northbridge/intel/i440lx/raminit.c b/src/northbridge/intel/i440lx/raminit.c
index 7d283a1..11aba16 100644
--- a/src/northbridge/intel/i440lx/raminit.c
+++ b/src/northbridge/intel/i440lx/raminit.c
@@ -173,7 +173,7 @@ static void do_ram_command(u32 command)
PRINT_DEBUG("\n");
#endif
- read32(addr);
+ read32((void *)(uintptr_t)(addr));
}
/* Set the start of the next DIMM. */
diff --git a/src/northbridge/intel/i5000/raminit.c b/src/northbridge/intel/i5000/raminit.c
index 5394002..a4bf5c3 100644
--- a/src/northbridge/intel/i5000/raminit.c
+++ b/src/northbridge/intel/i5000/raminit.c
@@ -458,25 +458,28 @@ static int i5000_amb_smbus_read_config32(struct i5000_fbdimm *d,
static void i5000_amb_write_config8(struct i5000_fbdimm *d,
int fn, int reg, u32 val)
{
- write8(DEFAULT_AMBASE + AMB_ADDR(d->ambase, fn, reg), val);
+ write8(val,
+ (void *)(uintptr_t)(DEFAULT_AMBASE + AMB_ADDR(d->ambase, fn, reg)));
}
static void i5000_amb_write_config16(struct i5000_fbdimm *d,
int fn, int reg, u32 val)
{
- write16(DEFAULT_AMBASE + AMB_ADDR(d->ambase, fn, reg), val);
+ write16(val,
+ (void *)(uintptr_t)(DEFAULT_AMBASE + AMB_ADDR(d->ambase, fn, reg)));
}
static void i5000_amb_write_config32(struct i5000_fbdimm *d,
int fn, int reg, u32 val)
{
- write32(DEFAULT_AMBASE + AMB_ADDR(d->ambase, fn, reg), val);
+ write32(val,
+ (void *)(uintptr_t)(DEFAULT_AMBASE + AMB_ADDR(d->ambase, fn, reg)));
}
static u32 i5000_amb_read_config32(struct i5000_fbdimm *d,
int fn, int reg)
{
- return read32(DEFAULT_AMBASE + AMB_ADDR(d->ambase, fn, reg));
+ return read32((void *)(uintptr_t)(DEFAULT_AMBASE + AMB_ADDR(d->ambase, fn, reg)));
}
static int ddr_command(struct i5000_fbdimm *d, int rank, u32 addr, u32 command)
diff --git a/src/northbridge/intel/i82810/raminit.c b/src/northbridge/intel/i82810/raminit.c
index 904c960..81717de 100644
--- a/src/northbridge/intel/i82810/raminit.c
+++ b/src/northbridge/intel/i82810/raminit.c
@@ -193,14 +193,14 @@ static void do_ram_command(u8 command)
if (dimm_size) {
addr = (dimm_start * 1024 * 1024) + addr_offset;
PRINT_DEBUG(" Sending RAM command 0x%02x to 0x%08x\n", reg8, addr);
- read32(addr);
+ read32((void *)(uintptr_t)(addr));
}
dimm_bank = translate_i82810_to_bank[drp];
if (dimm_bank) {
addr = ((dimm_start + dimm_bank) * 1024 * 1024) + addr_offset;
PRINT_DEBUG(" Sending RAM command 0x%02x to 0x%08x\n", reg8, addr);
- read32(addr);
+ read32((void *)(uintptr_t)(addr));
}
dimm_start += dimm_size;
diff --git a/src/northbridge/intel/i82830/raminit.c b/src/northbridge/intel/i82830/raminit.c
index a42374c..4a9ba56 100644
--- a/src/northbridge/intel/i82830/raminit.c
+++ b/src/northbridge/intel/i82830/raminit.c
@@ -77,15 +77,15 @@ static void ram_read32(u8 dimm_start, u32 offset)
{
u32 reg32, base_addr = 32 * 1024 * 1024 * dimm_start;
if (offset == 0x55aa55aa) {
- reg32 = read32(base_addr);
+ reg32 = read32((void *)(uintptr_t)(base_addr));
PRINTK_DEBUG(" Reading RAM at 0x%08x => 0x%08x\n", base_addr, reg32);
PRINTK_DEBUG(" Writing RAM at 0x%08x <= 0x%08x\n", base_addr, offset);
- write32(base_addr, offset);
- reg32 = read32(base_addr);
+ write32(offset, (void *)(uintptr_t)(base_addr));
+ reg32 = read32((void *)(uintptr_t)(base_addr));
PRINTK_DEBUG(" Reading RAM at 0x%08x => 0x%08x\n", base_addr, reg32);
} else {
PRINTK_DEBUG(" to 0x%08x\n", base_addr + offset);
- read32(base_addr + offset);
+ read32((void *)(uintptr_t)(base_addr + offset));
}
}
diff --git a/src/northbridge/intel/i82830/smihandler.c b/src/northbridge/intel/i82830/smihandler.c
index e4d93cf..4facf30 100644
--- a/src/northbridge/intel/i82830/smihandler.c
+++ b/src/northbridge/intel/i82830/smihandler.c
@@ -317,7 +317,7 @@ static void smi_interface_call(void)
swsmi |= (PC13 << 8);
pci_write_config16(PCI_DEV(0, 0x02, 0), 0xe0, swsmi);
// write magic
- write32(mmio + 0x71428, 0x494e5443);
+ write32(0x494e5443, (void *)(uintptr_t)(mmio + 0x71428));
return;
case 4:
printk(BIOS_DEBUG, "Get BIOS Data.\n");
@@ -325,7 +325,8 @@ static void smi_interface_call(void)
break;
case 5:
printk(BIOS_DEBUG, "Call MBI Functions.\n");
- mbi_call(swsmi >> 8, (banner_id_t *)((read32(mmio + 0x71428) & 0x000fffff) + OBJ_OFFSET) );
+ mbi_call(swsmi >> 8,
+ (banner_id_t *)((read32((void *)(uintptr_t)(mmio + 0x71428)) & 0x000fffff) + OBJ_OFFSET) );
// swsmi = 0x0000;
swsmi &= ~(7 << 5); // Exit: Result
swsmi |= (SMI_IFC_SUCCESS << 5);
diff --git a/src/northbridge/intel/i855/raminit.c b/src/northbridge/intel/i855/raminit.c
index 0ab4d38..1412674 100644
--- a/src/northbridge/intel/i855/raminit.c
+++ b/src/northbridge/intel/i855/raminit.c
@@ -393,7 +393,7 @@ static void do_ram_command(uint8_t command, uint16_t jedec_mode_bits)
uint32_t dimm_start_address = dimm_start_32M_multiple << 25;
PRINTK_DEBUG(" Sending RAM command to 0x%08x\n", dimm_start_address + i855_mode_bits);
- read32(dimm_start_address + i855_mode_bits);
+ read32((void *)(uintptr_t)(dimm_start_address + i855_mode_bits));
// Set the start of the next DIMM
dimm_start_32M_multiple = dimm_end_32M_multiple;
diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c
index 204ba01..044a41d 100644
--- a/src/northbridge/intel/i945/gma.c
+++ b/src/northbridge/intel/i945/gma.c
@@ -69,18 +69,18 @@ static int gtt_setup(unsigned int mmiobase)
PGETBL_save |= PGETBL_ENABLED;
PGETBL_save |= 2; /* set GTT to 256kb */
- write32(mmiobase + GFX_FLSH_CNTL, 0);
+ write32(0, (void *)(uintptr_t)(mmiobase + GFX_FLSH_CNTL));
- write32(mmiobase + PGETBL_CTL, PGETBL_save);
+ write32(PGETBL_save, (void *)(uintptr_t)(mmiobase + PGETBL_CTL));
/* verify */
- if (read32(mmiobase + PGETBL_CTL) & PGETBL_ENABLED) {
+ if (read32((void *)(uintptr_t)(mmiobase + PGETBL_CTL)) & PGETBL_ENABLED) {
printk(BIOS_DEBUG, "gtt_setup is enabled.\n");
} else {
printk(BIOS_DEBUG, "gtt_setup failed!!!\n");
return 1;
}
- write32(mmiobase + GFX_FLSH_CNTL, 0);
+ write32(0, (void *)(uintptr_t)(mmiobase + GFX_FLSH_CNTL));
return 0;
}
@@ -129,41 +129,45 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf,
for (i = 0; i < 2; i++)
for (j = 0; j < 0x100; j++)
/* R=j, G=j, B=j. */
- write32(pmmio + PALETTE(i) + 4 * j, 0x10101 * j);
+ write32(0x10101 * j,
+ (void *)(uintptr_t)(pmmio + PALETTE(i) + 4 * j));
- write32(pmmio + PCH_PP_CONTROL, PANEL_UNLOCK_REGS
- | (read32(pmmio + PCH_PP_CONTROL) & ~PANEL_UNLOCK_MASK));
+ write32(PANEL_UNLOCK_REGS | (read32((void *)(uintptr_t)(pmmio + PCH_PP_CONTROL)) & ~PANEL_UNLOCK_MASK),
+ (void *)(uintptr_t)(pmmio + PCH_PP_CONTROL));
- write32(pmmio + MI_ARB_STATE, MI_ARB_C3_LP_WRITE_ENABLE | (1 << 27));
+ write32(MI_ARB_C3_LP_WRITE_ENABLE | (1 << 27),
+ (void *)(uintptr_t)(pmmio + MI_ARB_STATE));
/* Clean registers. */
for (i = 0; i < 0x20; i += 4)
- write32(pmmio + RENDER_RING_BASE + i, 0);
+ write32(0, (void *)(uintptr_t)(pmmio + RENDER_RING_BASE + i));
for (i = 0; i < 0x20; i += 4)
- write32(pmmio + FENCE_REG_965_0 + i, 0);
- write32(pmmio + PP_ON_DELAYS, 0);
- write32(pmmio + PP_OFF_DELAYS, 0);
+ write32(0, (void *)(uintptr_t)(pmmio + FENCE_REG_965_0 + i));
+ write32(0, (void *)(uintptr_t)(pmmio + PP_ON_DELAYS));
+ write32(0, (void *)(uintptr_t)(pmmio + PP_OFF_DELAYS));
/* Disable VGA. */
- write32(pmmio + VGACNTRL, VGA_DISP_DISABLE);
+ write32(VGA_DISP_DISABLE, (void *)(uintptr_t)(pmmio + VGACNTRL));
/* Disable pipes. */
- write32(pmmio + PIPECONF(0), 0);
- write32(pmmio + PIPECONF(1), 0);
+ write32(0, (void *)(uintptr_t)(pmmio + PIPECONF(0)));
+ write32(0, (void *)(uintptr_t)(pmmio + PIPECONF(1)));
/* Init PRB0. */
- write32(pmmio + HWS_PGA, 0x352d2000);
- write32(pmmio + PRB0_CTL, 0);
- write32(pmmio + PRB0_HEAD, 0);
- write32(pmmio + PRB0_TAIL, 0);
- write32(pmmio + PRB0_START, 0);
- write32(pmmio + PRB0_CTL, 0x0001f001);
-
- write32(pmmio + D_STATE, DSTATE_PLL_D3_OFF
- | DSTATE_GFX_CLOCK_GATING | DSTATE_DOT_CLOCK_GATING);
- write32(pmmio + ECOSKPD, 0x00010000);
- write32(pmmio + HWSTAM, 0xeffe);
- write32(pmmio + PORT_HOTPLUG_EN, conf->gpu_hotplug);
- write32(pmmio + INSTPM, 0x08000000 | INSTPM_AGPBUSY_DIS);
+ write32(0x352d2000, (void *)(uintptr_t)(pmmio + HWS_PGA));
+ write32(0, (void *)(uintptr_t)(pmmio + PRB0_CTL));
+ write32(0, (void *)(uintptr_t)(pmmio + PRB0_HEAD));
+ write32(0, (void *)(uintptr_t)(pmmio + PRB0_TAIL));
+ write32(0, (void *)(uintptr_t)(pmmio + PRB0_START));
+ write32(0x0001f001, (void *)(uintptr_t)(pmmio + PRB0_CTL));
+
+ write32(DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING | DSTATE_DOT_CLOCK_GATING,
+ (void *)(uintptr_t)(pmmio + D_STATE));
+ write32(0x00010000, (void *)(uintptr_t)(pmmio + ECOSKPD));
+ write32(0xeffe, (void *)(uintptr_t)(pmmio + HWSTAM));
+ write32(conf->gpu_hotplug,
+ (void *)(uintptr_t)(pmmio + PORT_HOTPLUG_EN));
+ write32(0x08000000 | INSTPM_AGPBUSY_DIS,
+ (void *)(uintptr_t)(pmmio + INSTPM));
target_frequency = conf->gpu_lvds_is_dual_channel ? edid.pixel_clock
: (2 * edid.pixel_clock);
@@ -227,128 +231,114 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf,
/ (pixel_p1 * 7));
#if !IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
- write32(pmmio + PF_WIN_SZ(0), vactive | (hactive << 16));
- write32(pmmio + PF_WIN_POS(0), 0);
- write32(pmmio + PF_CTL(0),PF_ENABLE | PF_FILTER_MED_3x3);
- write32(pmmio + PFIT_CONTROL, PFIT_ENABLE | (1 << PFIT_PIPE_SHIFT) | HORIZ_AUTO_SCALE | VERT_AUTO_SCALE);
+ write32(vactive | (hactive << 16),
+ (void *)(uintptr_t)(pmmio + PF_WIN_SZ(0)));
+ write32(0, (void *)(uintptr_t)(pmmio + PF_WIN_POS(0)));
+ write32(PF_ENABLE | PF_FILTER_MED_3x3,
+ (void *)(uintptr_t)(pmmio + PF_CTL(0)));
+ write32(PFIT_ENABLE | (1 << PFIT_PIPE_SHIFT) | HORIZ_AUTO_SCALE | VERT_AUTO_SCALE,
+ (void *)(uintptr_t)(pmmio + PFIT_CONTROL));
#else
/* Disable panel fitter (we're in native resolution). */
- write32(pmmio + PF_CTL(0), 0);
- write32(pmmio + PF_WIN_SZ(0), 0);
- write32(pmmio + PF_WIN_POS(0), 0);
- write32(pmmio + PFIT_PGM_RATIOS, 0);
- write32(pmmio + PFIT_CONTROL, 0);
+ write32(0, (void *)(uintptr_t)(pmmio + PF_CTL(0)));
+ write32(0, (void *)(uintptr_t)(pmmio + PF_WIN_SZ(0)));
+ write32(0, (void *)(uintptr_t)(pmmio + PF_WIN_POS(0)));
+ write32(0, (void *)(uintptr_t)(pmmio + PFIT_PGM_RATIOS));
+ write32(0, (void *)(uintptr_t)(pmmio + PFIT_CONTROL));
#endif
mdelay(1);
- write32(pmmio + DSPCNTR(0), DISPPLANE_BGRX888
- | DISPPLANE_SEL_PIPE_B | DISPPLANE_GAMMA_ENABLE);
+ write32(DISPPLANE_BGRX888 | DISPPLANE_SEL_PIPE_B | DISPPLANE_GAMMA_ENABLE,
+ (void *)(uintptr_t)(pmmio + DSPCNTR(0)));
mdelay(1);
- write32(pmmio + PP_CONTROL, PANEL_UNLOCK_REGS
- | (read32(pmmio + PP_CONTROL) & ~PANEL_UNLOCK_MASK));
- write32(pmmio + FP0(1),
- ((pixel_n - 2) << 16)
- | ((pixel_m1 - 2) << 8) | pixel_m2);
- write32(pmmio + DPLL(1),
- DPLL_VGA_MODE_DIS |
- DPLL_VCO_ENABLE | DPLLB_MODE_LVDS
- | (conf->gpu_lvds_is_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7
- : DPLLB_LVDS_P2_CLOCK_DIV_14)
- | (conf->gpu_lvds_use_spread_spectrum_clock
- ? DPLL_INTEGRATED_CLOCK_VLV | DPLL_INTEGRATED_CRI_CLK_VLV
- : 0)
- | (pixel_p1 << 16)
- | (pixel_p1));
+ write32(PANEL_UNLOCK_REGS | (read32((void *)(uintptr_t)(pmmio + PP_CONTROL)) & ~PANEL_UNLOCK_MASK),
+ (void *)(uintptr_t)(pmmio + PP_CONTROL));
+ write32(((pixel_n - 2) << 16) | ((pixel_m1 - 2) << 8) | pixel_m2,
+ (void *)(uintptr_t)(pmmio + FP0(1)));
+ write32(DPLL_VGA_MODE_DIS | DPLL_VCO_ENABLE | DPLLB_MODE_LVDS | (conf->gpu_lvds_is_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 : DPLLB_LVDS_P2_CLOCK_DIV_14) | (conf->gpu_lvds_use_spread_spectrum_clock ? DPLL_INTEGRATED_CLOCK_VLV | DPLL_INTEGRATED_CRI_CLK_VLV : 0) | (pixel_p1 << 16) | (pixel_p1),
+ (void *)(uintptr_t)(pmmio + DPLL(1)));
mdelay(1);
- write32(pmmio + DPLL(1),
- DPLL_VGA_MODE_DIS |
- DPLL_VCO_ENABLE | DPLLB_MODE_LVDS
- | (conf->gpu_lvds_is_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7
- : DPLLB_LVDS_P2_CLOCK_DIV_14)
- | ((conf->gpu_lvds_use_spread_spectrum_clock ? 3 : 0) << 13)
- | (pixel_p1 << 16)
- | (pixel_p1));
+ write32(DPLL_VGA_MODE_DIS | DPLL_VCO_ENABLE | DPLLB_MODE_LVDS | (conf->gpu_lvds_is_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 : DPLLB_LVDS_P2_CLOCK_DIV_14) | ((conf->gpu_lvds_use_spread_spectrum_clock ? 3 : 0) << 13) | (pixel_p1 << 16) | (pixel_p1),
+ (void *)(uintptr_t)(pmmio + DPLL(1)));
mdelay(1);
- write32(pmmio + HTOTAL(1),
- ((hactive + right_border + hblank - 1) << 16)
- | (hactive - 1));
- write32(pmmio + HBLANK(1),
- ((hactive + right_border + hblank - 1) << 16)
- | (hactive + right_border - 1));
- write32(pmmio + HSYNC(1),
- ((hactive + right_border + hfront_porch + hsync - 1) << 16)
- | (hactive + right_border + hfront_porch - 1));
-
- write32(pmmio + VTOTAL(1), ((vactive + bottom_border + vblank - 1) << 16)
- | (vactive - 1));
- write32(pmmio + VBLANK(1), ((vactive + bottom_border + vblank - 1) << 16)
- | (vactive + bottom_border - 1));
- write32(pmmio + VSYNC(1),
- (vactive + bottom_border + vfront_porch + vsync - 1)
- | (vactive + bottom_border + vfront_porch - 1));
+ write32(((hactive + right_border + hblank - 1) << 16) | (hactive - 1),
+ (void *)(uintptr_t)(pmmio + HTOTAL(1)));
+ write32(((hactive + right_border + hblank - 1) << 16) | (hactive + right_border - 1),
+ (void *)(uintptr_t)(pmmio + HBLANK(1)));
+ write32(((hactive + right_border + hfront_porch + hsync - 1) << 16) | (hactive + right_border + hfront_porch - 1),
+ (void *)(uintptr_t)(pmmio + HSYNC(1)));
+
+ write32(((vactive + bottom_border + vblank - 1) << 16) | (vactive - 1),
+ (void *)(uintptr_t)(pmmio + VTOTAL(1)));
+ write32(((vactive + bottom_border + vblank - 1) << 16) | (vactive + bottom_border - 1),
+ (void *)(uintptr_t)(pmmio + VBLANK(1)));
+ write32((vactive + bottom_border + vfront_porch + vsync - 1) | (vactive + bottom_border + vfront_porch - 1),
+ (void *)(uintptr_t)(pmmio + VSYNC(1)));
#if !IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
- write32(pmmio + PIPESRC(1), (639 << 16) | 399);
+ write32((639 << 16) | 399, (void *)(uintptr_t)(pmmio + PIPESRC(1)));
#else
- write32(pmmio + PIPESRC(1), ((hactive - 1) << 16) | (vactive - 1));
+ write32(((hactive - 1) << 16) | (vactive - 1),
+ (void *)(uintptr_t)(pmmio + PIPESRC(1)));
#endif
mdelay(1);
- write32(pmmio + DSPSIZE(0), (hactive - 1) | ((vactive - 1) << 16));
- write32(pmmio + DSPPOS(0), 0);
+ write32((hactive - 1) | ((vactive - 1) << 16),
+ (void *)(uintptr_t)(pmmio + DSPSIZE(0)));
+ write32(0, (void *)(uintptr_t)(pmmio + DSPPOS(0)));
/* Backlight init. */
- write32(pmmio + FW_BLC_SELF, FW_BLC_SELF_EN_MASK);
- write32(pmmio + FW_BLC, 0x011d011a);
- write32(pmmio + FW_BLC2, 0x00000102);
- write32(pmmio + FW_BLC_SELF, FW_BLC_SELF_EN_MASK);
- write32(pmmio + FW_BLC_SELF, 0x0001003f);
- write32(pmmio + FW_BLC, 0x011d0109);
- write32(pmmio + FW_BLC2, 0x00000102);
- write32(pmmio + FW_BLC_SELF, FW_BLC_SELF_EN_MASK);
- write32(pmmio + BLC_PWM_CTL, conf->gpu_backlight);
+ write32(FW_BLC_SELF_EN_MASK, (void *)(uintptr_t)(pmmio + FW_BLC_SELF));
+ write32(0x011d011a, (void *)(uintptr_t)(pmmio + FW_BLC));
+ write32(0x00000102, (void *)(uintptr_t)(pmmio + FW_BLC2));
+ write32(FW_BLC_SELF_EN_MASK, (void *)(uintptr_t)(pmmio + FW_BLC_SELF));
+ write32(0x0001003f, (void *)(uintptr_t)(pmmio + FW_BLC_SELF));
+ write32(0x011d0109, (void *)(uintptr_t)(pmmio + FW_BLC));
+ write32(0x00000102, (void *)(uintptr_t)(pmmio + FW_BLC2));
+ write32(FW_BLC_SELF_EN_MASK, (void *)(uintptr_t)(pmmio + FW_BLC_SELF));
+ write32(conf->gpu_backlight, (void *)(uintptr_t)(pmmio + BLC_PWM_CTL));
edid.bytes_per_line = (edid.bytes_per_line + 63) & ~63;
- write32(pmmio + DSPADDR(0), 0);
- write32(pmmio + DSPSURF(0), 0);
- write32(pmmio + DSPSTRIDE(0), edid.bytes_per_line);
- write32(pmmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888
- | DISPPLANE_SEL_PIPE_B | DISPPLANE_GAMMA_ENABLE);
+ write32(0, (void *)(uintptr_t)(pmmio + DSPADDR(0)));
+ write32(0, (void *)(uintptr_t)(pmmio + DSPSURF(0)));
+ write32(edid.bytes_per_line,
+ (void *)(uintptr_t)(pmmio + DSPSTRIDE(0)));
+ write32(DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888 | DISPPLANE_SEL_PIPE_B | DISPPLANE_GAMMA_ENABLE,
+ (void *)(uintptr_t)(pmmio + DSPCNTR(0)));
mdelay(1);
- write32(pmmio + PIPECONF(1), PIPECONF_ENABLE);
- write32(pmmio + LVDS, LVDS_ON
- | (hpolarity << 20) | (vpolarity << 21)
- | (conf->gpu_lvds_is_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL
- | LVDS_CLOCK_BOTH_POWERUP_ALL : 0)
- | LVDS_CLOCK_A_POWERUP_ALL
- | LVDS_PIPE(1));
+ write32(PIPECONF_ENABLE, (void *)(uintptr_t)(pmmio + PIPECONF(1)));
+ write32(LVDS_ON | (hpolarity << 20) | (vpolarity << 21) | (conf->gpu_lvds_is_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) | LVDS_CLOCK_A_POWERUP_ALL | LVDS_PIPE(1),
+ (void *)(uintptr_t)(pmmio + LVDS));
- write32(pmmio + PP_CONTROL, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
- write32(pmmio + PP_CONTROL, PANEL_UNLOCK_REGS | PANEL_POWER_RESET);
+ write32(PANEL_UNLOCK_REGS | PANEL_POWER_OFF,
+ (void *)(uintptr_t)(pmmio + PP_CONTROL));
+ write32(PANEL_UNLOCK_REGS | PANEL_POWER_RESET,
+ (void *)(uintptr_t)(pmmio + PP_CONTROL));
mdelay(1);
- write32(pmmio + PP_CONTROL, PANEL_UNLOCK_REGS
- | PANEL_POWER_ON | PANEL_POWER_RESET);
+ write32(PANEL_UNLOCK_REGS | PANEL_POWER_ON | PANEL_POWER_RESET,
+ (void *)(uintptr_t)(pmmio + PP_CONTROL));
printk (BIOS_DEBUG, "waiting for panel powerup\n");
while (1) {
u32 reg32;
- reg32 = read32(pmmio + PP_STATUS);
+ reg32 = read32((void *)(uintptr_t)(pmmio + PP_STATUS));
if ((reg32 & PP_SEQUENCE_MASK) == PP_SEQUENCE_NONE)
break;
}
printk (BIOS_DEBUG, "panel powered up\n");
- write32(pmmio + PP_CONTROL, PANEL_POWER_ON | PANEL_POWER_RESET);
+ write32(PANEL_POWER_ON | PANEL_POWER_RESET,
+ (void *)(uintptr_t)(pmmio + PP_CONTROL));
/* Clear interrupts. */
- write32(pmmio + DEIIR, 0xffffffff);
- write32(pmmio + SDEIIR, 0xffffffff);
- write32(pmmio + IIR, 0xffffffff);
- write32(pmmio + IMR, 0xffffffff);
- write32(pmmio + EIR, 0xffffffff);
+ write32(0xffffffff, (void *)(uintptr_t)(pmmio + DEIIR));
+ write32(0xffffffff, (void *)(uintptr_t)(pmmio + SDEIIR));
+ write32(0xffffffff, (void *)(uintptr_t)(pmmio + IIR));
+ write32(0xffffffff, (void *)(uintptr_t)(pmmio + IMR));
+ write32(0xffffffff, (void *)(uintptr_t)(pmmio + EIR));
if (gtt_setup(pmmio)) {
printk(BIOS_ERR, "ERROR: GTT Setup Failed!!!\n");
@@ -380,7 +370,7 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf,
outl(pphysbase + (i << 12) + 1, piobase + 4);
}
- temp = read32(pmmio + PGETBL_CTL);
+ temp = read32((void *)(uintptr_t)(pmmio + PGETBL_CTL));
printk(BIOS_INFO, "GTT PGETBL_CTL register: 0x%lx\n", temp);
if (temp & 1)
@@ -391,9 +381,10 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf,
#if !IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
vga_misc_write(0x67);
- write32(pmmio + DSPCNTR(0), DISPPLANE_SEL_PIPE_B);
+ write32(DISPPLANE_SEL_PIPE_B, (void *)(uintptr_t)(pmmio + DSPCNTR(0)));
- write32(pmmio + VGACNTRL, 0x02c4008e | VGA_PIPE_B_SELECT);
+ write32(0x02c4008e | VGA_PIPE_B_SELECT,
+ (void *)(uintptr_t)(pmmio + VGACNTRL));
vga_textmode_init();
#else
diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c
index e9b6e3f..0b2c3f2 100644
--- a/src/northbridge/intel/i945/raminit.c
+++ b/src/northbridge/intel/i945/raminit.c
@@ -90,7 +90,7 @@ static void ram_read32(u32 offset)
{
PRINTK_DEBUG(" ram read: %08x\n", offset);
- read32(offset);
+ read32((void *)(uintptr_t)(offset));
}
#if CONFIG_DEBUG_RAM_SETUP
diff --git a/src/northbridge/intel/i945/rcven.c b/src/northbridge/intel/i945/rcven.c
index 88d6a00..0973d36 100644
--- a/src/northbridge/intel/i945/rcven.c
+++ b/src/northbridge/intel/i945/rcven.c
@@ -42,8 +42,8 @@ static u32 sample_strobes(int channel_offset, struct sys_info *sysinfo)
}
for (i = 0; i < 28; i++) {
- read32(addr);
- read32(addr + 0x80);
+ read32((void *)(uintptr_t)(addr));
+ read32((void *)(uintptr_t)(addr + 0x80));
}
reg32 = MCHBAR32(RCVENMT);
diff --git a/src/northbridge/intel/nehalem/acpi.c b/src/northbridge/intel/nehalem/acpi.c
index 460942f..8600d6f 100644
--- a/src/northbridge/intel/nehalem/acpi.c
+++ b/src/northbridge/intel/nehalem/acpi.c
@@ -120,7 +120,7 @@ static int init_opregion_vbt(igd_opregion_t * opregion)
optionrom_header_t *oprom = (optionrom_header_t *) vbios;
optionrom_vbt_t *vbt = (optionrom_vbt_t *) (vbios + oprom->vbt_offset);
- if (read32((unsigned long)vbt->hdr_signature) != VBT_SIGNATURE) {
+ if (read32((void *)(uintptr_t)((unsigned long)vbt->hdr_signature)) != VBT_SIGNATURE) {
printk(BIOS_DEBUG, "VBT not found!\n");
return 1;
}
diff --git a/src/northbridge/intel/nehalem/gma.c b/src/northbridge/intel/nehalem/gma.c
index c3e2a49..ab3c1b3 100644
--- a/src/northbridge/intel/nehalem/gma.c
+++ b/src/northbridge/intel/nehalem/gma.c
@@ -274,12 +274,12 @@ static struct resource *gtt_res = NULL;
u32 gtt_read(u32 reg)
{
- return read32(gtt_res->base + reg);
+ return read32((void *)(uintptr_t)(gtt_res->base + reg));
}
void gtt_write(u32 reg, u32 data)
{
- write32(gtt_res->base + reg, data);
+ write32(data, (void *)(uintptr_t)(gtt_res->base + reg));
}
static inline void gtt_write_powermeter(const struct gt_powermeter *pm)
@@ -564,78 +564,78 @@ static void gma_pm_init_post_vbios(struct device *dev)
static void train_link(u32 mmio)
{
/* Clear interrupts. */
- write32(mmio + DEIIR, 0xffffffff);
-
- write32(mmio + 0x000f0018, 0x000000ff);
- write32(mmio + 0x000f1018, 0x000000ff);
- write32(mmio + 0x000f000c, 0x001a2050);
- write32(mmio + 0x00060100, 0x001c4000);
- write32(mmio + 0x00060100, 0x801c4000);
- write32(mmio + 0x000f000c, 0x801a2050);
- write32(mmio + 0x00060100, 0x801c4000);
- write32(mmio + 0x000f000c, 0x801a2050);
+ write32(0xffffffff, (void *)(uintptr_t)(mmio + DEIIR));
+
+ write32(0x000000ff, (void *)(uintptr_t)(mmio + 0x000f0018));
+ write32(0x000000ff, (void *)(uintptr_t)(mmio + 0x000f1018));
+ write32(0x001a2050, (void *)(uintptr_t)(mmio + 0x000f000c));
+ write32(0x001c4000, (void *)(uintptr_t)(mmio + 0x00060100));
+ write32(0x801c4000, (void *)(uintptr_t)(mmio + 0x00060100));
+ write32(0x801a2050, (void *)(uintptr_t)(mmio + 0x000f000c));
+ write32(0x801c4000, (void *)(uintptr_t)(mmio + 0x00060100));
+ write32(0x801a2050, (void *)(uintptr_t)(mmio + 0x000f000c));
mdelay(1);
- read32(mmio + 0x000f0014); // = 0x00000100
- write32(mmio + 0x000f0014, 0x00000100);
- write32(mmio + 0x00060100, 0x901c4000);
- write32(mmio + 0x000f000c, 0x901a2050);
+ read32((void *)(uintptr_t)(mmio + 0x000f0014)); // = 0x00000100
+ write32(0x00000100, (void *)(uintptr_t)(mmio + 0x000f0014));
+ write32(0x901c4000, (void *)(uintptr_t)(mmio + 0x00060100));
+ write32(0x901a2050, (void *)(uintptr_t)(mmio + 0x000f000c));
mdelay(1);
- read32(mmio + 0x000f0014); // = 0x00000600
+ read32((void *)(uintptr_t)(mmio + 0x000f0014)); // = 0x00000600
}
static void power_port(u32 mmio)
{
- read32(mmio + 0x000e1100); // = 0x00000000
- write32(mmio + 0x000e1100, 0x00000000);
- write32(mmio + 0x000e1100, 0x00010000);
- read32(mmio + 0x000e1100); // = 0x00010000
- read32(mmio + 0x000e1100); // = 0x00010000
- read32(mmio + 0x000e1100); // = 0x00000000
- write32(mmio + 0x000e1100, 0x00000000);
- read32(mmio + 0x000e1100); // = 0x00000000
- read32(mmio + 0x000e4200); // = 0x0000001c
- write32(mmio + 0x000e4210, 0x8004003e);
- write32(mmio + 0x000e4214, 0x80060002);
- write32(mmio + 0x000e4218, 0x01000000);
- read32(mmio + 0x000e4210); // = 0x5144003e
- write32(mmio + 0x000e4210, 0x5344003e);
- read32(mmio + 0x000e4210); // = 0x0144003e
- write32(mmio + 0x000e4210, 0x8074003e);
- read32(mmio + 0x000e4210); // = 0x5144003e
- read32(mmio + 0x000e4210); // = 0x5144003e
- write32(mmio + 0x000e4210, 0x5344003e);
- read32(mmio + 0x000e4210); // = 0x0144003e
- write32(mmio + 0x000e4210, 0x8074003e);
- read32(mmio + 0x000e4210); // = 0x5144003e
- read32(mmio + 0x000e4210); // = 0x5144003e
- write32(mmio + 0x000e4210, 0x5344003e);
- read32(mmio + 0x000e4210); // = 0x0144003e
- write32(mmio + 0x000e4210, 0x8074003e);
- read32(mmio + 0x000e4210); // = 0x5144003e
- read32(mmio + 0x000e4210); // = 0x5144003e
- write32(mmio + 0x000e4210, 0x5344003e);
- write32(mmio + 0x000e4f00, 0x0100030c);
- write32(mmio + 0x000e4f04, 0x00b8230c);
- write32(mmio + 0x000e4f08, 0x06f8930c);
- write32(mmio + 0x000e4f0c, 0x09f8e38e);
- write32(mmio + 0x000e4f10, 0x00b8030c);
- write32(mmio + 0x000e4f14, 0x0b78830c);
- write32(mmio + 0x000e4f18, 0x0ff8d3cf);
- write32(mmio + 0x000e4f1c, 0x01e8030c);
- write32(mmio + 0x000e4f20, 0x0ff863cf);
- write32(mmio + 0x000e4f24, 0x0ff803cf);
- write32(mmio + 0x000c4030, 0x00001000);
- read32(mmio + 0x000c4000); // = 0x00000000
- write32(mmio + 0x000c4030, 0x00001000);
- read32(mmio + 0x000e1150); // = 0x0000001c
- write32(mmio + 0x000e1150, 0x0000089c);
- write32(mmio + 0x000fcc00, 0x01986f00);
- write32(mmio + 0x000fcc0c, 0x01986f00);
- write32(mmio + 0x000fcc18, 0x01986f00);
- write32(mmio + 0x000fcc24, 0x01986f00);
- read32(mmio + 0x000c4000); // = 0x00000000
- read32(mmio + 0x000e1180); // = 0x40000002
+ read32((void *)(uintptr_t)(mmio + 0x000e1100)); // = 0x00000000
+ write32(0x00000000, (void *)(uintptr_t)(mmio + 0x000e1100));
+ write32(0x00010000, (void *)(uintptr_t)(mmio + 0x000e1100));
+ read32((void *)(uintptr_t)(mmio + 0x000e1100)); // = 0x00010000
+ read32((void *)(uintptr_t)(mmio + 0x000e1100)); // = 0x00010000
+ read32((void *)(uintptr_t)(mmio + 0x000e1100)); // = 0x00000000
+ write32(0x00000000, (void *)(uintptr_t)(mmio + 0x000e1100));
+ read32((void *)(uintptr_t)(mmio + 0x000e1100)); // = 0x00000000
+ read32((void *)(uintptr_t)(mmio + 0x000e4200)); // = 0x0000001c
+ write32(0x8004003e, (void *)(uintptr_t)(mmio + 0x000e4210));
+ write32(0x80060002, (void *)(uintptr_t)(mmio + 0x000e4214));
+ write32(0x01000000, (void *)(uintptr_t)(mmio + 0x000e4218));
+ read32((void *)(uintptr_t)(mmio + 0x000e4210)); // = 0x5144003e
+ write32(0x5344003e, (void *)(uintptr_t)(mmio + 0x000e4210));
+ read32((void *)(uintptr_t)(mmio + 0x000e4210)); // = 0x0144003e
+ write32(0x8074003e, (void *)(uintptr_t)(mmio + 0x000e4210));
+ read32((void *)(uintptr_t)(mmio + 0x000e4210)); // = 0x5144003e
+ read32((void *)(uintptr_t)(mmio + 0x000e4210)); // = 0x5144003e
+ write32(0x5344003e, (void *)(uintptr_t)(mmio + 0x000e4210));
+ read32((void *)(uintptr_t)(mmio + 0x000e4210)); // = 0x0144003e
+ write32(0x8074003e, (void *)(uintptr_t)(mmio + 0x000e4210));
+ read32((void *)(uintptr_t)(mmio + 0x000e4210)); // = 0x5144003e
+ read32((void *)(uintptr_t)(mmio + 0x000e4210)); // = 0x5144003e
+ write32(0x5344003e, (void *)(uintptr_t)(mmio + 0x000e4210));
+ read32((void *)(uintptr_t)(mmio + 0x000e4210)); // = 0x0144003e
+ write32(0x8074003e, (void *)(uintptr_t)(mmio + 0x000e4210));
+ read32((void *)(uintptr_t)(mmio + 0x000e4210)); // = 0x5144003e
+ read32((void *)(uintptr_t)(mmio + 0x000e4210)); // = 0x5144003e
+ write32(0x5344003e, (void *)(uintptr_t)(mmio + 0x000e4210));
+ write32(0x0100030c, (void *)(uintptr_t)(mmio + 0x000e4f00));
+ write32(0x00b8230c, (void *)(uintptr_t)(mmio + 0x000e4f04));
+ write32(0x06f8930c, (void *)(uintptr_t)(mmio + 0x000e4f08));
+ write32(0x09f8e38e, (void *)(uintptr_t)(mmio + 0x000e4f0c));
+ write32(0x00b8030c, (void *)(uintptr_t)(mmio + 0x000e4f10));
+ write32(0x0b78830c, (void *)(uintptr_t)(mmio + 0x000e4f14));
+ write32(0x0ff8d3cf, (void *)(uintptr_t)(mmio + 0x000e4f18));
+ write32(0x01e8030c, (void *)(uintptr_t)(mmio + 0x000e4f1c));
+ write32(0x0ff863cf, (void *)(uintptr_t)(mmio + 0x000e4f20));
+ write32(0x0ff803cf, (void *)(uintptr_t)(mmio + 0x000e4f24));
+ write32(0x00001000, (void *)(uintptr_t)(mmio + 0x000c4030));
+ read32((void *)(uintptr_t)(mmio + 0x000c4000)); // = 0x00000000
+ write32(0x00001000, (void *)(uintptr_t)(mmio + 0x000c4030));
+ read32((void *)(uintptr_t)(mmio + 0x000e1150)); // = 0x0000001c
+ write32(0x0000089c, (void *)(uintptr_t)(mmio + 0x000e1150));
+ write32(0x01986f00, (void *)(uintptr_t)(mmio + 0x000fcc00));
+ write32(0x01986f00, (void *)(uintptr_t)(mmio + 0x000fcc0c));
+ write32(0x01986f00, (void *)(uintptr_t)(mmio + 0x000fcc18));
+ write32(0x01986f00, (void *)(uintptr_t)(mmio + 0x000fcc24));
+ read32((void *)(uintptr_t)(mmio + 0x000c4000)); // = 0x00000000
+ read32((void *)(uintptr_t)(mmio + 0x000e1180)); // = 0x40000002
}
static void intel_gma_init(const struct northbridge_intel_nehalem_config *info,
@@ -660,23 +660,24 @@ static void intel_gma_init(const struct northbridge_intel_nehalem_config *info,
u32 link_m1;
u32 link_n1 = 0x00080000;
- write32(mmio + 0x00070080, 0x00000000);
- write32(mmio + DSPCNTR(0), 0x00000000);
- write32(mmio + 0x00071180, 0x00000000);
- write32(mmio + CPU_VGACNTRL, 0x0000298e | VGA_DISP_DISABLE);
- write32(mmio + 0x0007019c, 0x00000000);
- write32(mmio + 0x0007119c, 0x00000000);
- write32(mmio + 0x000fc008, 0x2c010000);
- write32(mmio + 0x000fc020, 0x2c010000);
- write32(mmio + 0x000fc038, 0x2c010000);
- write32(mmio + 0x000fc050, 0x2c010000);
- write32(mmio + 0x000fc408, 0x2c010000);
- write32(mmio + 0x000fc420, 0x2c010000);
- write32(mmio + 0x000fc438, 0x2c010000);
- write32(mmio + 0x000fc450, 0x2c010000);
+ write32(0x00000000, (void *)(uintptr_t)(mmio + 0x00070080));
+ write32(0x00000000, (void *)(uintptr_t)(mmio + DSPCNTR(0)));
+ write32(0x00000000, (void *)(uintptr_t)(mmio + 0x00071180));
+ write32(0x0000298e | VGA_DISP_DISABLE,
+ (void *)(uintptr_t)(mmio + CPU_VGACNTRL));
+ write32(0x00000000, (void *)(uintptr_t)(mmio + 0x0007019c));
+ write32(0x00000000, (void *)(uintptr_t)(mmio + 0x0007119c));
+ write32(0x2c010000, (void *)(uintptr_t)(mmio + 0x000fc008));
+ write32(0x2c010000, (void *)(uintptr_t)(mmio + 0x000fc020));
+ write32(0x2c010000, (void *)(uintptr_t)(mmio + 0x000fc038));
+ write32(0x2c010000, (void *)(uintptr_t)(mmio + 0x000fc050));
+ write32(0x2c010000, (void *)(uintptr_t)(mmio + 0x000fc408));
+ write32(0x2c010000, (void *)(uintptr_t)(mmio + 0x000fc420));
+ write32(0x2c010000, (void *)(uintptr_t)(mmio + 0x000fc438));
+ write32(0x2c010000, (void *)(uintptr_t)(mmio + 0x000fc450));
vga_gr_write(0x18, 0);
- write32(mmio + 0x00042004, 0x02000000);
- write32(mmio + 0x000fd034, 0x8421ffe0);
+ write32(0x02000000, (void *)(uintptr_t)(mmio + 0x00042004));
+ write32(0x8421ffe0, (void *)(uintptr_t)(mmio + 0x000fd034));
/* Setup GTT. */
for (i = 0; i < 0x2000; i++)
@@ -742,12 +743,13 @@ static void intel_gma_init(const struct northbridge_intel_nehalem_config *info,
edid.bytes_per_line = (edid.bytes_per_line + 63) & ~63;
- write32(mmio + DSPCNTR(0), DISPPLANE_BGRX888);
- write32(mmio + DSPADDR(0), 0);
- write32(mmio + DSPSTRIDE(0), edid.bytes_per_line);
- write32(mmio + DSPSURF(0), 0);
+ write32(DISPPLANE_BGRX888, (void *)(uintptr_t)(mmio + DSPCNTR(0)));
+ write32(0, (void *)(uintptr_t)(mmio + DSPADDR(0)));
+ write32(edid.bytes_per_line, (void *)(uintptr_t)(mmio + DSPSTRIDE(0)));
+ write32(0, (void *)(uintptr_t)(mmio + DSPSURF(0)));
for (i = 0; i < 0x100; i++)
- write32(mmio + LGC_PALETTE(0) + 4 * i, i * 0x010101);
+ write32(i * 0x010101,
+ (void *)(uintptr_t)(mmio + LGC_PALETTE(0) + 4 * i));
#endif
/* Find suitable divisors. */
@@ -820,167 +822,145 @@ static void intel_gma_init(const struct northbridge_intel_nehalem_config *info,
120000 * (5 * pixel_m1 + pixel_m2) / pixel_n
/ (pixel_p1 * 7));
- write32(mmio + PCH_LVDS,
- (hpolarity << 20) | (vpolarity << 21)
- | (info->gfx.lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL
- | LVDS_CLOCK_BOTH_POWERUP_ALL : 0)
- | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL
- | LVDS_DETECTED);
- write32(mmio + BLC_PWM_CPU_CTL2, (1 << 31));
- write32(mmio + PCH_DREF_CONTROL, (info->gfx.use_spread_spectrum_clock
- ? 0x1002 : 0x400));
+ write32((hpolarity << 20) | (vpolarity << 21) | (info->gfx.lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL | LVDS_DETECTED,
+ (void *)(uintptr_t)(mmio + PCH_LVDS));
+ write32((1 << 31), (void *)(uintptr_t)(mmio + BLC_PWM_CPU_CTL2));
+ write32((info->gfx.use_spread_spectrum_clock ? 0x1002 : 0x400),
+ (void *)(uintptr_t)(mmio + PCH_DREF_CONTROL));
mdelay(1);
- write32(mmio + PCH_PP_CONTROL, PANEL_UNLOCK_REGS
- | (read32(mmio + PCH_PP_CONTROL) & ~PANEL_UNLOCK_MASK));
- write32(mmio + _PCH_FP0(0),
- ((pixel_n - 2) << 16)
- | ((pixel_m1 - 2) << 8) | pixel_m2);
- write32(mmio + _PCH_DPLL(0),
- DPLL_VCO_ENABLE | DPLLB_MODE_LVDS
- | (info->gfx.lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7
- : DPLLB_LVDS_P2_CLOCK_DIV_14)
- | (0x10000 << (pixel_p1 - 1))
- | ((info->gfx.use_spread_spectrum_clock ? 3 : 0) << 13)
- | (0x1 << (pixel_p1 - 1)));
+ write32(PANEL_UNLOCK_REGS | (read32((void *)(uintptr_t)(mmio + PCH_PP_CONTROL)) & ~PANEL_UNLOCK_MASK),
+ (void *)(uintptr_t)(mmio + PCH_PP_CONTROL));
+ write32(((pixel_n - 2) << 16) | ((pixel_m1 - 2) << 8) | pixel_m2,
+ (void *)(uintptr_t)(mmio + _PCH_FP0(0)));
+ write32(DPLL_VCO_ENABLE | DPLLB_MODE_LVDS | (info->gfx.lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 : DPLLB_LVDS_P2_CLOCK_DIV_14) | (0x10000 << (pixel_p1 - 1)) | ((info->gfx.use_spread_spectrum_clock ? 3 : 0) << 13) | (0x1 << (pixel_p1 - 1)),
+ (void *)(uintptr_t)(mmio + _PCH_DPLL(0)));
mdelay(1);
- write32(mmio + _PCH_DPLL(0),
- DPLL_VCO_ENABLE | DPLLB_MODE_LVDS
- | (info->gfx.lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7
- : DPLLB_LVDS_P2_CLOCK_DIV_14)
- | (0x10000 << (pixel_p1 - 1))
- | ((info->gfx.use_spread_spectrum_clock ? 3 : 0) << 13)
- | (0x1 << (pixel_p1 - 1)));
+ write32(DPLL_VCO_ENABLE | DPLLB_MODE_LVDS | (info->gfx.lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 : DPLLB_LVDS_P2_CLOCK_DIV_14) | (0x10000 << (pixel_p1 - 1)) | ((info->gfx.use_spread_spectrum_clock ? 3 : 0) << 13) | (0x1 << (pixel_p1 - 1)),
+ (void *)(uintptr_t)(mmio + _PCH_DPLL(0)));
/* Re-lock the registers. */
- write32(mmio + PCH_PP_CONTROL,
- (read32(mmio + PCH_PP_CONTROL) & ~PANEL_UNLOCK_MASK));
-
- write32(mmio + PCH_LVDS,
- (hpolarity << 20) | (vpolarity << 21)
- | (info->gfx.lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL
- | LVDS_CLOCK_BOTH_POWERUP_ALL : 0)
- | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL
- | LVDS_DETECTED);
-
- write32(mmio + HTOTAL(0),
- ((hactive + right_border + hblank - 1) << 16)
- | (hactive - 1));
- write32(mmio + HBLANK(0),
- ((hactive + right_border + hblank - 1) << 16)
- | (hactive + right_border - 1));
- write32(mmio + HSYNC(0),
- ((hactive + right_border + hfront_porch + hsync - 1) << 16)
- | (hactive + right_border + hfront_porch - 1));
-
- write32(mmio + VTOTAL(0), ((vactive + bottom_border + vblank - 1) << 16)
- | (vactive - 1));
- write32(mmio + VBLANK(0), ((vactive + bottom_border + vblank - 1) << 16)
- | (vactive + bottom_border - 1));
- write32(mmio + VSYNC(0),
- (vactive + bottom_border + vfront_porch + vsync - 1)
- | (vactive + bottom_border + vfront_porch - 1));
-
- write32(mmio + PIPECONF(0), PIPECONF_DISABLE);
-
- write32(mmio + PF_WIN_POS(0), 0);
+ write32((read32((void *)(uintptr_t)(mmio + PCH_PP_CONTROL)) & ~PANEL_UNLOCK_MASK),
+ (void *)(uintptr_t)(mmio + PCH_PP_CONTROL));
+
+ write32((hpolarity << 20) | (vpolarity << 21) | (info->gfx.lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL | LVDS_DETECTED,
+ (void *)(uintptr_t)(mmio + PCH_LVDS));
+
+ write32(((hactive + right_border + hblank - 1) << 16) | (hactive - 1),
+ (void *)(uintptr_t)(mmio + HTOTAL(0)));
+ write32(((hactive + right_border + hblank - 1) << 16) | (hactive + right_border - 1),
+ (void *)(uintptr_t)(mmio + HBLANK(0)));
+ write32(((hactive + right_border + hfront_porch + hsync - 1) << 16) | (hactive + right_border + hfront_porch - 1),
+ (void *)(uintptr_t)(mmio + HSYNC(0)));
+
+ write32(((vactive + bottom_border + vblank - 1) << 16) | (vactive - 1),
+ (void *)(uintptr_t)(mmio + VTOTAL(0)));
+ write32(((vactive + bottom_border + vblank - 1) << 16) | (vactive + bottom_border - 1),
+ (void *)(uintptr_t)(mmio + VBLANK(0)));
+ write32((vactive + bottom_border + vfront_porch + vsync - 1) | (vactive + bottom_border + vfront_porch - 1),
+ (void *)(uintptr_t)(mmio + VSYNC(0)));
+
+ write32(PIPECONF_DISABLE, (void *)(uintptr_t)(mmio + PIPECONF(0)));
+
+ write32(0, (void *)(uintptr_t)(mmio + PF_WIN_POS(0)));
#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
- write32(mmio + PIPESRC(0), ((hactive - 1) << 16) | (vactive - 1));
- write32(mmio + PF_CTL(0),0);
- write32(mmio + PF_WIN_SZ(0), 0);
+ write32(((hactive - 1) << 16) | (vactive - 1),
+ (void *)(uintptr_t)(mmio + PIPESRC(0)));
+ write32(0, (void *)(uintptr_t)(mmio + PF_CTL(0)));
+ write32(0, (void *)(uintptr_t)(mmio + PF_WIN_SZ(0)));
#else
- write32(mmio + PIPESRC(0), (639 << 16) | 399);
- write32(mmio + PF_CTL(0),PF_ENABLE | PF_FILTER_MED_3x3);
- write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16));
+ write32((639 << 16) | 399, (void *)(uintptr_t)(mmio + PIPESRC(0)));
+ write32(PF_ENABLE | PF_FILTER_MED_3x3,
+ (void *)(uintptr_t)(mmio + PF_CTL(0)));
+ write32(vactive | (hactive << 16),
+ (void *)(uintptr_t)(mmio + PF_WIN_SZ(0)));
#endif
mdelay(1);
- write32(mmio + PIPE_DATA_M1(0), 0x7e000000 | data_m1);
- write32(mmio + PIPE_DATA_N1(0), data_n1);
- write32(mmio + PIPE_LINK_M1(0), link_m1);
- write32(mmio + PIPE_LINK_N1(0), link_n1);
+ write32(0x7e000000 | data_m1,
+ (void *)(uintptr_t)(mmio + PIPE_DATA_M1(0)));
+ write32(data_n1, (void *)(uintptr_t)(mmio + PIPE_DATA_N1(0)));
+ write32(link_m1, (void *)(uintptr_t)(mmio + PIPE_LINK_M1(0)));
+ write32(link_n1, (void *)(uintptr_t)(mmio + PIPE_LINK_N1(0)));
- write32(mmio + 0x000f000c, 0x00002040);
+ write32(0x00002040, (void *)(uintptr_t)(mmio + 0x000f000c));
mdelay(1);
- write32(mmio + 0x000f000c, 0x00002050);
- write32(mmio + 0x00060100, 0x00044000);
+ write32(0x00002050, (void *)(uintptr_t)(mmio + 0x000f000c));
+ write32(0x00044000, (void *)(uintptr_t)(mmio + 0x00060100));
mdelay(1);
- write32(mmio + PIPECONF(0), PIPECONF_BPP_6);
- write32(mmio + 0x000f0008, 0x00000040);
- write32(mmio + 0x000f000c, 0x00022050);
- write32(mmio + PIPECONF(0), PIPECONF_BPP_6 | PIPECONF_DITHER_EN);
- write32(mmio + PIPECONF(0), PIPECONF_ENABLE | PIPECONF_BPP_6 | PIPECONF_DITHER_EN);
+ write32(PIPECONF_BPP_6, (void *)(uintptr_t)(mmio + PIPECONF(0)));
+ write32(0x00000040, (void *)(uintptr_t)(mmio + 0x000f0008));
+ write32(0x00022050, (void *)(uintptr_t)(mmio + 0x000f000c));
+ write32(PIPECONF_BPP_6 | PIPECONF_DITHER_EN,
+ (void *)(uintptr_t)(mmio + PIPECONF(0)));
+ write32(PIPECONF_ENABLE | PIPECONF_BPP_6 | PIPECONF_DITHER_EN,
+ (void *)(uintptr_t)(mmio + PIPECONF(0)));
#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
- write32(mmio + CPU_VGACNTRL, 0x20298e | VGA_DISP_DISABLE);
+ write32(0x20298e | VGA_DISP_DISABLE,
+ (void *)(uintptr_t)(mmio + CPU_VGACNTRL));
#else
- write32(mmio + CPU_VGACNTRL, 0x20298e);
+ write32(0x20298e, (void *)(uintptr_t)(mmio + CPU_VGACNTRL));
#endif
train_link(mmio);
#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
- write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888);
+ write32(DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888,
+ (void *)(uintptr_t)(mmio + DSPCNTR(0)));
mdelay(1);
#endif
- write32(mmio + TRANS_HTOTAL(0),
- ((hactive + right_border + hblank - 1) << 16)
- | (hactive - 1));
- write32(mmio + TRANS_HBLANK(0),
- ((hactive + right_border + hblank - 1) << 16)
- | (hactive + right_border - 1));
- write32(mmio + TRANS_HSYNC(0),
- ((hactive + right_border + hfront_porch + hsync - 1) << 16)
- | (hactive + right_border + hfront_porch - 1));
-
- write32(mmio + TRANS_VTOTAL(0),
- ((vactive + bottom_border + vblank - 1) << 16)
- | (vactive - 1));
- write32(mmio + TRANS_VBLANK(0),
- ((vactive + bottom_border + vblank - 1) << 16)
- | (vactive + bottom_border - 1));
- write32(mmio + TRANS_VSYNC(0),
- (vactive + bottom_border + vfront_porch + vsync - 1)
- | (vactive + bottom_border + vfront_porch - 1));
-
- write32(mmio + 0x00060100, 0xb01c4000);
- write32(mmio + 0x000f000c, 0xb01a2050);
+ write32(((hactive + right_border + hblank - 1) << 16) | (hactive - 1),
+ (void *)(uintptr_t)(mmio + TRANS_HTOTAL(0)));
+ write32(((hactive + right_border + hblank - 1) << 16) | (hactive + right_border - 1),
+ (void *)(uintptr_t)(mmio + TRANS_HBLANK(0)));
+ write32(((hactive + right_border + hfront_porch + hsync - 1) << 16) | (hactive + right_border + hfront_porch - 1),
+ (void *)(uintptr_t)(mmio + TRANS_HSYNC(0)));
+
+ write32(((vactive + bottom_border + vblank - 1) << 16) | (vactive - 1),
+ (void *)(uintptr_t)(mmio + TRANS_VTOTAL(0)));
+ write32(((vactive + bottom_border + vblank - 1) << 16) | (vactive + bottom_border - 1),
+ (void *)(uintptr_t)(mmio + TRANS_VBLANK(0)));
+ write32((vactive + bottom_border + vfront_porch + vsync - 1) | (vactive + bottom_border + vfront_porch - 1),
+ (void *)(uintptr_t)(mmio + TRANS_VSYNC(0)));
+
+ write32(0xb01c4000, (void *)(uintptr_t)(mmio + 0x00060100));
+ write32(0xb01a2050, (void *)(uintptr_t)(mmio + 0x000f000c));
mdelay(1);
- write32(mmio + TRANSCONF(0), TRANS_ENABLE | TRANS_6BPC
+ write32(TRANS_ENABLE | TRANS_6BPC
#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
- | TRANS_STATE_MASK
+
+ | TRANS_STATE_MASK
#endif
- );
- write32(mmio + PCH_LVDS,
- LVDS_PORT_ENABLE
- | (hpolarity << 20) | (vpolarity << 21)
- | (info->gfx.lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL
- | LVDS_CLOCK_BOTH_POWERUP_ALL : 0)
- | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL
- | LVDS_DETECTED);
-
- write32(mmio + PCH_PP_CONTROL, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
- write32(mmio + PCH_PP_CONTROL, PANEL_UNLOCK_REGS | PANEL_POWER_RESET);
+, (void *)(uintptr_t)(mmio + TRANSCONF(0)));
+ write32(LVDS_PORT_ENABLE | (hpolarity << 20) | (vpolarity << 21) | (info->gfx.lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL | LVDS_DETECTED,
+ (void *)(uintptr_t)(mmio + PCH_LVDS));
+
+ write32(PANEL_UNLOCK_REGS | PANEL_POWER_OFF,
+ (void *)(uintptr_t)(mmio + PCH_PP_CONTROL));
+ write32(PANEL_UNLOCK_REGS | PANEL_POWER_RESET,
+ (void *)(uintptr_t)(mmio + PCH_PP_CONTROL));
mdelay(1);
- write32(mmio + PCH_PP_CONTROL, PANEL_UNLOCK_REGS
- | PANEL_POWER_ON | PANEL_POWER_RESET);
+ write32(PANEL_UNLOCK_REGS | PANEL_POWER_ON | PANEL_POWER_RESET,
+ (void *)(uintptr_t)(mmio + PCH_PP_CONTROL));
printk (BIOS_DEBUG, "waiting for panel powerup\n");
while (1) {
u32 reg32;
- reg32 = read32(mmio + PCH_PP_STATUS);
+ reg32 = read32((void *)(uintptr_t)(mmio + PCH_PP_STATUS));
if (((reg32 >> 28) & 3) == 0)
break;
}
printk (BIOS_DEBUG, "panel powered up\n");
- write32(mmio + PCH_PP_CONTROL, PANEL_POWER_ON | PANEL_POWER_RESET);
+ write32(PANEL_POWER_ON | PANEL_POWER_RESET,
+ (void *)(uintptr_t)(mmio + PCH_PP_CONTROL));
/* Enable screen memory. */
vga_sr_write(1, vga_sr_read(1) & ~0x20);
/* Clear interrupts. */
- write32(mmio + DEIIR, 0xffffffff);
- write32(mmio + SDEIIR, 0xffffffff);
+ write32(0xffffffff, (void *)(uintptr_t)(mmio + DEIIR));
+ write32(0xffffffff, (void *)(uintptr_t)(mmio + SDEIIR));
#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
memset ((void *) lfb, 0, edid.x_resolution * edid.y_resolution * 4);
diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c
index 9ca98d5..5d6bd09 100644
--- a/src/northbridge/intel/nehalem/raminit.c
+++ b/src/northbridge/intel/nehalem/raminit.c
@@ -319,36 +319,36 @@ static int rw_test(int rank)
int ok = 0xff;
int i;
for (i = 0; i < 64; i++)
- write32((rank << 28) | (i << 2), 0);
+ write32(0, (void *)(uintptr_t)((rank << 28) | (i << 2)));
sfence();
for (i = 0; i < 64; i++)
- gav(read32((rank << 28) | (i << 2)));
+ gav(read32((void *)(uintptr_t)((rank << 28) | (i << 2))));
sfence();
for (i = 0; i < 32; i++) {
u32 pat = (((mask >> i) & 1) ? 0xffffffff : 0);
- write32((rank << 28) | (i << 3), pat);
- write32((rank << 28) | (i << 3) | 4, pat);
+ write32(pat, (void *)(uintptr_t)((rank << 28) | (i << 3)));
+ write32(pat, (void *)(uintptr_t)((rank << 28) | (i << 3) | 4));
}
sfence();
for (i = 0; i < 32; i++) {
u8 pat = (((mask >> i) & 1) ? 0xff : 0);
int j;
u32 val;
- gav(val = read32((rank << 28) | (i << 3)));
+ gav(val = read32((void *)(uintptr_t)((rank << 28) | (i << 3))));
for (j = 0; j < 4; j++)
if (((val >> (j * 8)) & 0xff) != pat)
ok &= ~(1 << j);
- gav(val = read32((rank << 28) | (i << 3) | 4));
+ gav(val = read32((void *)(uintptr_t)((rank << 28) | (i << 3) | 4)));
for (j = 0; j < 4; j++)
if (((val >> (j * 8)) & 0xff) != pat)
ok &= ~(16 << j);
}
sfence();
for (i = 0; i < 64; i++)
- write32((rank << 28) | (i << 2), 0);
+ write32(0, (void *)(uintptr_t)((rank << 28) | (i << 2)));
sfence();
for (i = 0; i < 64; i++)
- gav(read32((rank << 28) | (i << 2)));
+ gav(read32((void *)(uintptr_t)((rank << 28) | (i << 2))));
return ok;
}
@@ -1077,12 +1077,12 @@ static void jedec_read(struct raminfo *info,
(value & ~0x1f8) | ((value >> 1) & 0xa8) | ((value & 0xa8)
<< 1);
- read32((value << 3) | (total_rank << 28));
+ read32((void *)(uintptr_t)((value << 3) | (total_rank << 28)));
write_mchbar8(0x271, (read_mchbar8(0x271) & 0xC3) | 2);
write_mchbar8(0x671, (read_mchbar8(0x671) & 0xC3) | 2);
- read32(total_rank << 28);
+ read32((void *)(uintptr_t)(total_rank << 28));
}
enum {
@@ -1567,7 +1567,7 @@ static void collect_system_info(struct raminfo *info)
unsigned channel;
/* Wait for some bit, maybe TXT clear. */
- while (!(read8(0xfed40000) & (1 << 7))) ;
+ while (!(read8((void *)(uintptr_t)(0xfed40000)) & (1 << 7))) ;
if (!info->heci_bar)
gav(info->heci_bar =
@@ -1751,9 +1751,9 @@ static const struct ram_training *get_cached_training(void)
/* FIXME: add timeout. */
static void wait_heci_ready(void)
{
- while (!(read32(DEFAULT_HECIBAR | 0xc) & 8)) ; // = 0x8000000c
- write32((DEFAULT_HECIBAR | 0x4),
- (read32(DEFAULT_HECIBAR | 0x4) & ~0x10) | 0xc);
+ while (!(read32((void *)(uintptr_t)(DEFAULT_HECIBAR | 0xc)) & 8)) ; // = 0x8000000c
+ write32((read32((void *)(uintptr_t)(DEFAULT_HECIBAR | 0x4)) & ~0x10) | 0xc,
+ (void *)(uintptr_t)((DEFAULT_HECIBAR | 0x4)));
}
/* FIXME: add timeout. */
@@ -1764,10 +1764,10 @@ static void wait_heci_cb_avail(int len)
u32 raw;
} csr;
- while (!(read32(DEFAULT_HECIBAR | 0xc) & 8)) ;
+ while (!(read32((void *)(uintptr_t)(DEFAULT_HECIBAR | 0xc)) & 8)) ;
do
- csr.raw = read32(DEFAULT_HECIBAR | 0x4);
+ csr.raw = read32((void *)(uintptr_t)(DEFAULT_HECIBAR | 0x4));
while (len >
csr.csr.buffer_depth - (csr.csr.buffer_write_ptr -
csr.csr.buffer_read_ptr));
@@ -1781,12 +1781,14 @@ static void send_heci_packet(struct mei_header *head, u32 * payload)
wait_heci_cb_avail(len + 1);
/* FIXME: handle leftovers correctly. */
- write32(DEFAULT_HECIBAR | 0, *(u32 *) head);
+ write32(*(u32 *)head, (void *)(uintptr_t)(DEFAULT_HECIBAR | 0));
for (i = 0; i < len - 1; i++)
- write32(DEFAULT_HECIBAR | 0, payload[i]);
+ write32(payload[i], (void *)(uintptr_t)(DEFAULT_HECIBAR | 0));
- write32(DEFAULT_HECIBAR | 0, payload[i] & ((1 << (8 * len)) - 1));
- write32(DEFAULT_HECIBAR | 0x4, read32(DEFAULT_HECIBAR | 0x4) | 0x4);
+ write32(payload[i] & ((1 << (8 * len)) - 1),
+ (void *)(uintptr_t)(DEFAULT_HECIBAR | 0));
+ write32(read32((void *)(uintptr_t)(DEFAULT_HECIBAR | 0x4)) | 0x4,
+ (void *)(uintptr_t)(DEFAULT_HECIBAR | 0x4));
}
static void
@@ -1796,7 +1798,7 @@ send_heci_message(u8 * msg, int len, u8 hostaddress, u8 clientaddress)
int maxlen;
wait_heci_ready();
- maxlen = (read32(DEFAULT_HECIBAR | 0x4) >> 24) * 4 - 4;
+ maxlen = (read32((void *)(uintptr_t)(DEFAULT_HECIBAR | 0x4)) >> 24) * 4 - 4;
while (len) {
int cur = len;
@@ -1826,19 +1828,20 @@ recv_heci_packet(struct raminfo *info, struct mei_header *head, u32 * packet,
} csr;
int i = 0;
- write32(DEFAULT_HECIBAR | 0x4, read32(DEFAULT_HECIBAR | 0x4) | 2);
+ write32(read32((void *)(uintptr_t)(DEFAULT_HECIBAR | 0x4)) | 2,
+ (void *)(uintptr_t)(DEFAULT_HECIBAR | 0x4));
do {
- csr.raw = read32(DEFAULT_HECIBAR | 0xc);
+ csr.raw = read32((void *)(uintptr_t)(DEFAULT_HECIBAR | 0xc));
#if !REAL
if (i++ > 346)
return -1;
#endif
}
while (csr.csr.buffer_write_ptr == csr.csr.buffer_read_ptr);
- *(u32 *) head = read32(DEFAULT_HECIBAR | 0x8);
+ *(u32 *) head = read32((void *)(uintptr_t)(DEFAULT_HECIBAR | 0x8));
if (!head->length) {
- write32(DEFAULT_HECIBAR | 0x4,
- read32(DEFAULT_HECIBAR | 0x4) | 2);
+ write32(read32((void *)(uintptr_t)(DEFAULT_HECIBAR | 0x4)) | 2,
+ (void *)(uintptr_t)(DEFAULT_HECIBAR | 0x4));
*packet_size = 0;
return 0;
}
@@ -1849,16 +1852,17 @@ recv_heci_packet(struct raminfo *info, struct mei_header *head, u32 * packet,
}
do
- csr.raw = read32(DEFAULT_HECIBAR | 0xc);
+ csr.raw = read32((void *)(uintptr_t)(DEFAULT_HECIBAR | 0xc));
while ((head->length + 3) >> 2 >
csr.csr.buffer_write_ptr - csr.csr.buffer_read_ptr);
for (i = 0; i < (head->length + 3) >> 2; i++)
- packet[i++] = read32(DEFAULT_HECIBAR | 0x8);
+ packet[i++] = read32((void *)(uintptr_t)(DEFAULT_HECIBAR | 0x8));
*packet_size = head->length;
if (!csr.csr.ready)
*packet_size = 0;
- write32(DEFAULT_HECIBAR | 0x4, read32(DEFAULT_HECIBAR | 0x4) | 4);
+ write32(read32((void *)(uintptr_t)(DEFAULT_HECIBAR | 0x4)) | 4,
+ (void *)(uintptr_t)(DEFAULT_HECIBAR | 0x4));
return 0;
}
@@ -1946,27 +1950,28 @@ static void setup_heci_uma(struct raminfo *info)
pcie_read_config32(NORTHBRIDGE, DMIBAR);
if (info->memory_reserved_for_heci_mb) {
- write32(DEFAULT_DMIBAR | 0x14,
- read32(DEFAULT_DMIBAR | 0x14) & ~0x80);
- write32(DEFAULT_RCBA | 0x14,
- read32(DEFAULT_RCBA | 0x14) & ~0x80);
- write32(DEFAULT_DMIBAR | 0x20,
- read32(DEFAULT_DMIBAR | 0x20) & ~0x80);
- write32(DEFAULT_RCBA | 0x20,
- read32(DEFAULT_RCBA | 0x20) & ~0x80);
- write32(DEFAULT_DMIBAR | 0x2c,
- read32(DEFAULT_DMIBAR | 0x2c) & ~0x80);
- write32(DEFAULT_RCBA | 0x30,
- read32(DEFAULT_RCBA | 0x30) & ~0x80);
- write32(DEFAULT_DMIBAR | 0x38,
- read32(DEFAULT_DMIBAR | 0x38) & ~0x80);
- write32(DEFAULT_RCBA | 0x40,
- read32(DEFAULT_RCBA | 0x40) & ~0x80);
-
- write32(DEFAULT_RCBA | 0x40, 0x87000080); // OK
- write32(DEFAULT_DMIBAR | 0x38, 0x87000080); // OK
- while (read16(DEFAULT_RCBA | 0x46) & 2
- && read16(DEFAULT_DMIBAR | 0x3e) & 2) ;
+ write32(read32((void *)(uintptr_t)(DEFAULT_DMIBAR | 0x14)) & ~0x80,
+ (void *)(uintptr_t)(DEFAULT_DMIBAR | 0x14));
+ write32(read32((void *)(uintptr_t)(DEFAULT_RCBA | 0x14)) & ~0x80,
+ (void *)(uintptr_t)(DEFAULT_RCBA | 0x14));
+ write32(read32((void *)(uintptr_t)(DEFAULT_DMIBAR | 0x20)) & ~0x80,
+ (void *)(uintptr_t)(DEFAULT_DMIBAR | 0x20));
+ write32(read32((void *)(uintptr_t)(DEFAULT_RCBA | 0x20)) & ~0x80,
+ (void *)(uintptr_t)(DEFAULT_RCBA | 0x20));
+ write32(read32((void *)(uintptr_t)(DEFAULT_DMIBAR | 0x2c)) & ~0x80,
+ (void *)(uintptr_t)(DEFAULT_DMIBAR | 0x2c));
+ write32(read32((void *)(uintptr_t)(DEFAULT_RCBA | 0x30)) & ~0x80,
+ (void *)(uintptr_t)(DEFAULT_RCBA | 0x30));
+ write32(read32((void *)(uintptr_t)(DEFAULT_DMIBAR | 0x38)) & ~0x80,
+ (void *)(uintptr_t)(DEFAULT_DMIBAR | 0x38));
+ write32(read32((void *)(uintptr_t)(DEFAULT_RCBA | 0x40)) & ~0x80,
+ (void *)(uintptr_t)(DEFAULT_RCBA | 0x40));
+
+ write32(0x87000080, (void *)(uintptr_t)(DEFAULT_RCBA | 0x40)); // OK
+ write32(0x87000080,
+ (void *)(uintptr_t)(DEFAULT_DMIBAR | 0x38)); // OK
+ while (read16((void *)(uintptr_t)(DEFAULT_RCBA | 0x46)) & 2
+ && read16((void *)(uintptr_t)(DEFAULT_DMIBAR | 0x3e)) & 2) ;
}
write_mchbar32(0x24, 0x10000 + info->memory_reserved_for_heci_mb);
@@ -2101,10 +2106,14 @@ static void write_testing(struct raminfo *info, int totalrank, int flip)
base = totalrank << 28;
for (offset = 0; offset < 9 * 480; offset += 2) {
- write32(base + offset * 8, get_etalon2(flip, offset));
- write32(base + offset * 8 + 4, get_etalon2(flip, offset));
- write32(base + offset * 8 + 8, get_etalon2(flip, offset + 1));
- write32(base + offset * 8 + 12, get_etalon2(flip, offset + 1));
+ write32(get_etalon2(flip, offset),
+ (void *)(uintptr_t)(base + offset * 8));
+ write32(get_etalon2(flip, offset),
+ (void *)(uintptr_t)(base + offset * 8 + 4));
+ write32(get_etalon2(flip, offset + 1),
+ (void *)(uintptr_t)(base + offset * 8 + 8));
+ write32(get_etalon2(flip, offset + 1),
+ (void *)(uintptr_t)(base + offset * 8 + 12));
nwrites += 4;
if (nwrites >= 320) {
clear_errors();
@@ -2217,8 +2226,8 @@ write_testing_type2(struct raminfo *info, u8 totalrank, u8 region, u8 block,
{
int i;
for (i = 0; i < 2048; i++)
- write32((totalrank << 28) | (region << 25) | (block << 16) |
- (i << 2), get_etalon(flip, (block << 16) | (i << 2)));
+ write32(get_etalon(flip, (block << 16) | (i << 2)),
+ (void *)(uintptr_t)((totalrank << 28) | (region << 25) | (block << 16) | (i << 2)));
}
static u8
@@ -2243,7 +2252,7 @@ check_testing_type2(struct raminfo *info, u8 totalrank, u8 region, u8 block,
| (comp3 << 12) | (comp2 << 6) | (comp1 <<
2);
failxor[comp1 & 1] |=
- read32(addr) ^ get_etalon(flip, addr);
+ read32((void *)(uintptr_t)(addr)) ^ get_etalon(flip, addr);
}
for (i = 0; i < 8; i++)
if ((0xff << (8 * (i % 4))) & failxor[i / 4])
@@ -3779,13 +3788,14 @@ static void restore_274265(struct raminfo *info)
#if REAL
static void dmi_setup(void)
{
- gav(read8(DEFAULT_DMIBAR | 0x254));
- write8(DEFAULT_DMIBAR | 0x254, 0x1);
- write16(DEFAULT_DMIBAR | 0x1b8, 0x18f2);
+ gav(read8((void *)(uintptr_t)(DEFAULT_DMIBAR | 0x254)));
+ write8(0x1, (void *)(uintptr_t)(DEFAULT_DMIBAR | 0x254));
+ write16(0x18f2, (void *)(uintptr_t)(DEFAULT_DMIBAR | 0x1b8));
read_mchbar16(0x48);
write_mchbar16(0x48, 0x2);
- write32(DEFAULT_DMIBAR | 0xd68, read32(DEFAULT_DMIBAR | 0xd68) | 0x08000000);
+ write32(read32((void *)(uintptr_t)(DEFAULT_DMIBAR | 0xd68)) | 0x08000000,
+ (void *)(uintptr_t)(DEFAULT_DMIBAR | 0xd68));
outl((gav(inl(DEFAULT_GPIOBASE | 0x38)) & ~0x140000) | 0x400000,
DEFAULT_GPIOBASE | 0x38);
@@ -3847,18 +3857,18 @@ void chipset_init(const int s3resume)
write_mchbar32(0x2c44, 0x1053687);
pcie_read_config8(GMA, 0x62); // = 0x2
pcie_write_config8(GMA, 0x62, 0x2);
- read8(DEFAULT_RCBA | 0x2318);
- write8(DEFAULT_RCBA | 0x2318, 0x47);
- read8(DEFAULT_RCBA | 0x2320);
- write8(DEFAULT_RCBA | 0x2320, 0xfc);
+ read8((void *)(uintptr_t)(DEFAULT_RCBA | 0x2318));
+ write8(0x47, (void *)(uintptr_t)(DEFAULT_RCBA | 0x2318));
+ read8((void *)(uintptr_t)(DEFAULT_RCBA | 0x2320));
+ write8(0xfc, (void *)(uintptr_t)(DEFAULT_RCBA | 0x2320));
}
read_mchbar32(0x30);
write_mchbar32(0x30, 0x40);
pcie_write_config16(NORTHBRIDGE, D0F0_GGC, ggc);
- gav(read32(DEFAULT_RCBA | 0x3428));
- write32(DEFAULT_RCBA | 0x3428, 0x1d);
+ gav(read32((void *)(uintptr_t)(DEFAULT_RCBA | 0x3428)));
+ write32(0x1d, (void *)(uintptr_t)(DEFAULT_RCBA | 0x3428));
}
void raminit(const int s3resume, const u8 *spd_addrmap)
@@ -4818,17 +4828,19 @@ void raminit(const int s3resume, const u8 *spd_addrmap)
write_mchbar32(0xd40, IOMMU_BASE1 | 1);
write_mchbar32(0xdc0, IOMMU_BASE4 | 1);
- write32(IOMMU_BASE1 | 0xffc, 0x80000000);
- write32(IOMMU_BASE2 | 0xffc, 0xc0000000);
- write32(IOMMU_BASE4 | 0xffc, 0x80000000);
+ write32(0x80000000, (void *)(uintptr_t)(IOMMU_BASE1 | 0xffc));
+ write32(0xc0000000, (void *)(uintptr_t)(IOMMU_BASE2 | 0xffc));
+ write32(0x80000000, (void *)(uintptr_t)(IOMMU_BASE4 | 0xffc));
#else
{
u32 eax;
- eax = read32(0xffc + (read_mchbar32(0xd00) & ~1)) | 0x08000000; // = 0xe911714b// OK
- write32(0xffc + (read_mchbar32(0xd00) & ~1), eax); // OK
- eax = read32(0xffc + (read_mchbar32(0xdc0) & ~1)) | 0x40000000; // = 0xe911714b// OK
- write32(0xffc + (read_mchbar32(0xdc0) & ~1), eax); // OK
+ eax = read32((void *)(uintptr_t)(0xffc + (read_mchbar32(0xd00) & ~1))) | 0x08000000; // = 0xe911714b// OK
+ write32(eax,
+ (void *)(uintptr_t)(0xffc + (read_mchbar32(0xd00) & ~1))); // OK
+ eax = read32((void *)(uintptr_t)(0xffc + (read_mchbar32(0xdc0) & ~1))) | 0x40000000; // = 0xe911714b// OK
+ write32(eax,
+ (void *)(uintptr_t)(0xffc + (read_mchbar32(0xdc0) & ~1))); // OK
}
#endif
@@ -4875,9 +4887,9 @@ void raminit(const int s3resume, const u8 *spd_addrmap)
}
u32 reg1c;
pcie_read_config32(NORTHBRIDGE, 0x40); // = DEFAULT_EPBAR | 0x001 // OK
- reg1c = read32(DEFAULT_EPBAR | 0x01c); // = 0x8001 // OK
+ reg1c = read32((void *)(uintptr_t)(DEFAULT_EPBAR | 0x01c)); // = 0x8001 // OK
pcie_read_config32(NORTHBRIDGE, 0x40); // = DEFAULT_EPBAR | 0x001 // OK
- write32(DEFAULT_EPBAR | 0x01c, reg1c); // OK
+ write32(reg1c, (void *)(uintptr_t)(DEFAULT_EPBAR | 0x01c)); // OK
read_mchbar8(0xe08); // = 0x0
pcie_read_config32(NORTHBRIDGE, 0xe4); // = 0x316126
write_mchbar8(0x1210, read_mchbar8(0x1210) | 2); // OK
diff --git a/src/northbridge/intel/sandybridge/acpi.c b/src/northbridge/intel/sandybridge/acpi.c
index 7a48696..9896c0e 100644
--- a/src/northbridge/intel/sandybridge/acpi.c
+++ b/src/northbridge/intel/sandybridge/acpi.c
@@ -121,7 +121,7 @@ static int init_opregion_vbt(igd_opregion_t *opregion)
optionrom_vbt_t *vbt = (optionrom_vbt_t *)(vbios +
oprom->vbt_offset);
- if (read32((unsigned long)vbt->hdr_signature) != VBT_SIGNATURE) {
+ if (read32((void *)(uintptr_t)((unsigned long)vbt->hdr_signature)) != VBT_SIGNATURE) {
printk(BIOS_DEBUG, "VBT not found!\n");
return 1;
}
diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c
index 247c723..ecda621 100644
--- a/src/northbridge/intel/sandybridge/gma.c
+++ b/src/northbridge/intel/sandybridge/gma.c
@@ -280,12 +280,12 @@ static struct resource *gtt_res = NULL;
u32 gtt_read(u32 reg)
{
- return read32(gtt_res->base + reg);
+ return read32((void *)(uintptr_t)(gtt_res->base + reg));
}
void gtt_write(u32 reg, u32 data)
{
- write32(gtt_res->base + reg, data);
+ write32(data, (void *)(uintptr_t)(gtt_res->base + reg));
}
static inline void gtt_write_powermeter(const struct gt_powermeter *pm)
diff --git a/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c b/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c
index e3e1f4b..bd11362 100644
--- a/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c
+++ b/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c
@@ -38,125 +38,124 @@
static void link_train(u32 mmio)
{
- write32(mmio+0xf000c,0x40);
- write32(mmio+0x60100,0x40000);
- write32(mmio+0xf0018,0x8ff);
- write32(mmio+0xf1018,0x8ff);
- write32(mmio+0xf000c,0x2040);
+ write32(0x40, (void *)(uintptr_t)(mmio + 0xf000c));
+ write32(0x40000, (void *)(uintptr_t)(mmio + 0x60100));
+ write32(0x8ff, (void *)(uintptr_t)(mmio + 0xf0018));
+ write32(0x8ff, (void *)(uintptr_t)(mmio + 0xf1018));
+ write32(0x2040, (void *)(uintptr_t)(mmio + 0xf000c));
mdelay(1);
- write32(mmio+0xf000c,0x2050);
- write32(mmio+0x60100,0x44000);
+ write32(0x2050, (void *)(uintptr_t)(mmio + 0xf000c));
+ write32(0x44000, (void *)(uintptr_t)(mmio + 0x60100));
mdelay(1);
- write32(mmio+0x70008,0x40);
- write32(mmio+0xe0300,0x60000418);
- write32(mmio+0xf000c,0x22050);
- write32(mmio+0x70008,0x50);
- write32(mmio+0x70008,0x80000050);
+ write32(0x40, (void *)(uintptr_t)(mmio + 0x70008));
+ write32(0x60000418, (void *)(uintptr_t)(mmio + 0xe0300));
+ write32(0x22050, (void *)(uintptr_t)(mmio + 0xf000c));
+ write32(0x50, (void *)(uintptr_t)(mmio + 0x70008));
+ write32(0x80000050, (void *)(uintptr_t)(mmio + 0x70008));
}
static void link_normal_operation(u32 mmio)
{
- write32(mmio + FDI_TX_CTL(0), 0x80044f02);
- write32(mmio + FDI_RX_CTL(0),
- FDI_RX_ENABLE | FDI_6BPC
- | 0x2f50);
+ write32(0x80044f02, (void *)(uintptr_t)(mmio + FDI_TX_CTL(0)));
+ write32(FDI_RX_ENABLE | FDI_6BPC | 0x2f50,
+ (void *)(uintptr_t)(mmio + FDI_RX_CTL(0)));
}
static void enable_port(u32 mmio)
{
- write32(mmio + 0xec008, 0x2c010000);
- write32(mmio + 0xec020, 0x2c010000);
- write32(mmio + 0xec038, 0x2c010000);
- write32(mmio + 0xec050, 0x2c010000);
- write32(mmio + 0xec408, 0x2c010000);
- write32(mmio + 0xec420, 0x2c010000);
- write32(mmio + 0xec438, 0x2c010000);
- write32(mmio + 0xec450, 0x2c010000);
- write32(mmio + 0xf0010, 0x200090);
- write32(mmio + 0xf1010, 0x200090);
- write32(mmio + 0xf2010, 0x200090);
- write32(mmio + 0xfd034, 0x8420000);
- write32(mmio + 0x45010, 0x3);
- write32(mmio + 0xf0060, 0x10);
- write32(mmio + 0xf1060, 0x10);
- write32(mmio + 0xf2060, 0x10);
- write32(mmio + 0x9840, 0x0);
- write32(mmio + 0x42000, 0xa0000000);
- write32(mmio + 0xe4f00, 0x100030c);
- write32(mmio + 0xe4f04, 0xb8230c);
- write32(mmio + 0xe4f08, 0x6f8930c);
- write32(mmio + 0xe4f0c, 0x5f8e38e);
- write32(mmio + 0xe4f10, 0xb8030c);
- write32(mmio + 0xe4f14, 0xb78830c);
- write32(mmio + 0xe4f18, 0x9f8d3cf);
- write32(mmio + 0xe4f1c, 0x1e8030c);
- write32(mmio + 0xe4f20, 0x9f863cf);
- write32(mmio + 0xe4f24, 0xff803cf);
- read32(mmio + 0xe4100);
- write32(mmio + 0xc4030, 0x10);
- write32(mmio + 0xe4110, 0x8004003e);
- write32(mmio + 0xe4114, 0x80060000);
- write32(mmio + 0xe4118, 0x1000000);
- read32(mmio + 0xe4110);
- write32(mmio + 0xe4110, 0x5344003e);
- read32(mmio + 0xe4110);
- write32(mmio + 0xe4110, 0x8054003e);
- read32(mmio + 0xe4110);
- read32(mmio + 0xe4110);
- write32(mmio + 0xe4110, 0x5344003e);
+ write32(0x2c010000, (void *)(uintptr_t)(mmio + 0xec008));
+ write32(0x2c010000, (void *)(uintptr_t)(mmio + 0xec020));
+ write32(0x2c010000, (void *)(uintptr_t)(mmio + 0xec038));
+ write32(0x2c010000, (void *)(uintptr_t)(mmio + 0xec050));
+ write32(0x2c010000, (void *)(uintptr_t)(mmio + 0xec408));
+ write32(0x2c010000, (void *)(uintptr_t)(mmio + 0xec420));
+ write32(0x2c010000, (void *)(uintptr_t)(mmio + 0xec438));
+ write32(0x2c010000, (void *)(uintptr_t)(mmio + 0xec450));
+ write32(0x200090, (void *)(uintptr_t)(mmio + 0xf0010));
+ write32(0x200090, (void *)(uintptr_t)(mmio + 0xf1010));
+ write32(0x200090, (void *)(uintptr_t)(mmio + 0xf2010));
+ write32(0x8420000, (void *)(uintptr_t)(mmio + 0xfd034));
+ write32(0x3, (void *)(uintptr_t)(mmio + 0x45010));
+ write32(0x10, (void *)(uintptr_t)(mmio + 0xf0060));
+ write32(0x10, (void *)(uintptr_t)(mmio + 0xf1060));
+ write32(0x10, (void *)(uintptr_t)(mmio + 0xf2060));
+ write32(0x0, (void *)(uintptr_t)(mmio + 0x9840));
+ write32(0xa0000000, (void *)(uintptr_t)(mmio + 0x42000));
+ write32(0x100030c, (void *)(uintptr_t)(mmio + 0xe4f00));
+ write32(0xb8230c, (void *)(uintptr_t)(mmio + 0xe4f04));
+ write32(0x6f8930c, (void *)(uintptr_t)(mmio + 0xe4f08));
+ write32(0x5f8e38e, (void *)(uintptr_t)(mmio + 0xe4f0c));
+ write32(0xb8030c, (void *)(uintptr_t)(mmio + 0xe4f10));
+ write32(0xb78830c, (void *)(uintptr_t)(mmio + 0xe4f14));
+ write32(0x9f8d3cf, (void *)(uintptr_t)(mmio + 0xe4f18));
+ write32(0x1e8030c, (void *)(uintptr_t)(mmio + 0xe4f1c));
+ write32(0x9f863cf, (void *)(uintptr_t)(mmio + 0xe4f20));
+ write32(0xff803cf, (void *)(uintptr_t)(mmio + 0xe4f24));
+ read32((void *)(uintptr_t)(mmio + 0xe4100));
+ write32(0x10, (void *)(uintptr_t)(mmio + 0xc4030));
+ write32(0x8004003e, (void *)(uintptr_t)(mmio + 0xe4110));
+ write32(0x80060000, (void *)(uintptr_t)(mmio + 0xe4114));
+ write32(0x1000000, (void *)(uintptr_t)(mmio + 0xe4118));
+ read32((void *)(uintptr_t)(mmio + 0xe4110));
+ write32(0x5344003e, (void *)(uintptr_t)(mmio + 0xe4110));
+ read32((void *)(uintptr_t)(mmio + 0xe4110));
+ write32(0x8054003e, (void *)(uintptr_t)(mmio + 0xe4110));
+ read32((void *)(uintptr_t)(mmio + 0xe4110));
+ read32((void *)(uintptr_t)(mmio + 0xe4110));
+ write32(0x5344003e, (void *)(uintptr_t)(mmio + 0xe4110));
mdelay(1);
- read32(mmio + 0xe4110);
- write32(mmio + 0xe4110, 0x8054003e);
- read32(mmio + 0xe4110);
- read32(mmio + 0xe4110);
- write32(mmio + 0xe4110, 0x5344003e);
+ read32((void *)(uintptr_t)(mmio + 0xe4110));
+ write32(0x8054003e, (void *)(uintptr_t)(mmio + 0xe4110));
+ read32((void *)(uintptr_t)(mmio + 0xe4110));
+ read32((void *)(uintptr_t)(mmio + 0xe4110));
+ write32(0x5344003e, (void *)(uintptr_t)(mmio + 0xe4110));
mdelay(1);
- read32(mmio + 0xe4110);
- write32(mmio + 0xe4110, 0x8054003e);
- read32(mmio + 0xe4110);
- read32(mmio + 0xe4110);
- write32(mmio + 0xe4110, 0x5344003e);
+ read32((void *)(uintptr_t)(mmio + 0xe4110));
+ write32(0x8054003e, (void *)(uintptr_t)(mmio + 0xe4110));
+ read32((void *)(uintptr_t)(mmio + 0xe4110));
+ read32((void *)(uintptr_t)(mmio + 0xe4110));
+ write32(0x5344003e, (void *)(uintptr_t)(mmio + 0xe4110));
mdelay(1);
- read32(mmio + 0xc4000);
- read32(mmio + 0xe1140);
- write32(mmio + 0xc4030, 0x10);
- read32(mmio + 0xc4000);
- write32(mmio + 0xe4f00, 0x100030c);
- write32(mmio + 0xe4f04, 0xb8230c);
- write32(mmio + 0xe4f08, 0x6f8930c);
- write32(mmio + 0xe4f0c, 0x5f8e38e);
- write32(mmio + 0xe4f10, 0xb8030c);
- write32(mmio + 0xe4f14, 0xb78830c);
- write32(mmio + 0xe4f18, 0x9f8d3cf);
- write32(mmio + 0xe4f1c, 0x1e8030c);
- write32(mmio + 0xe4f20, 0x9f863cf);
- write32(mmio + 0xe4f24, 0xff803cf);
- read32(mmio + 0xe4200);
- write32(mmio + 0xc4030, 0x1010);
- write32(mmio + 0xe4210, 0x8004003e);
- write32(mmio + 0xe4214, 0x80060000);
- write32(mmio + 0xe4218, 0x1002000);
- read32(mmio + 0xe4210);
- write32(mmio + 0xe4210, 0x5344003e);
- read32(mmio + 0xe4210);
- write32(mmio + 0xe4210, 0x8054003e);
- read32(mmio + 0xe4210);
- read32(mmio + 0xe4210);
- write32(mmio + 0xe4210, 0x5344003e);
+ read32((void *)(uintptr_t)(mmio + 0xc4000));
+ read32((void *)(uintptr_t)(mmio + 0xe1140));
+ write32(0x10, (void *)(uintptr_t)(mmio + 0xc4030));
+ read32((void *)(uintptr_t)(mmio + 0xc4000));
+ write32(0x100030c, (void *)(uintptr_t)(mmio + 0xe4f00));
+ write32(0xb8230c, (void *)(uintptr_t)(mmio + 0xe4f04));
+ write32(0x6f8930c, (void *)(uintptr_t)(mmio + 0xe4f08));
+ write32(0x5f8e38e, (void *)(uintptr_t)(mmio + 0xe4f0c));
+ write32(0xb8030c, (void *)(uintptr_t)(mmio + 0xe4f10));
+ write32(0xb78830c, (void *)(uintptr_t)(mmio + 0xe4f14));
+ write32(0x9f8d3cf, (void *)(uintptr_t)(mmio + 0xe4f18));
+ write32(0x1e8030c, (void *)(uintptr_t)(mmio + 0xe4f1c));
+ write32(0x9f863cf, (void *)(uintptr_t)(mmio + 0xe4f20));
+ write32(0xff803cf, (void *)(uintptr_t)(mmio + 0xe4f24));
+ read32((void *)(uintptr_t)(mmio + 0xe4200));
+ write32(0x1010, (void *)(uintptr_t)(mmio + 0xc4030));
+ write32(0x8004003e, (void *)(uintptr_t)(mmio + 0xe4210));
+ write32(0x80060000, (void *)(uintptr_t)(mmio + 0xe4214));
+ write32(0x1002000, (void *)(uintptr_t)(mmio + 0xe4218));
+ read32((void *)(uintptr_t)(mmio + 0xe4210));
+ write32(0x5344003e, (void *)(uintptr_t)(mmio + 0xe4210));
+ read32((void *)(uintptr_t)(mmio + 0xe4210));
+ write32(0x8054003e, (void *)(uintptr_t)(mmio + 0xe4210));
+ read32((void *)(uintptr_t)(mmio + 0xe4210));
+ read32((void *)(uintptr_t)(mmio + 0xe4210));
+ write32(0x5344003e, (void *)(uintptr_t)(mmio + 0xe4210));
mdelay(1);
- read32(mmio + 0xe4210);
- write32(mmio + 0xe4210, 0x8054003e);
- read32(mmio + 0xe4210);
- read32(mmio + 0xe4210);
- write32(mmio + 0xe4210, 0x5344003e);
+ read32((void *)(uintptr_t)(mmio + 0xe4210));
+ write32(0x8054003e, (void *)(uintptr_t)(mmio + 0xe4210));
+ read32((void *)(uintptr_t)(mmio + 0xe4210));
+ read32((void *)(uintptr_t)(mmio + 0xe4210));
+ write32(0x5344003e, (void *)(uintptr_t)(mmio + 0xe4210));
mdelay(1);
- read32(mmio + 0xe4210);
- write32(mmio + 0xe4210, 0x8054003e);
- read32(mmio + 0xe4210);
- read32(mmio + 0xe4210);
- write32(mmio + 0xe4210, 0x5344003e);
+ read32((void *)(uintptr_t)(mmio + 0xe4210));
+ write32(0x8054003e, (void *)(uintptr_t)(mmio + 0xe4210));
+ read32((void *)(uintptr_t)(mmio + 0xe4210));
+ read32((void *)(uintptr_t)(mmio + 0xe4210));
+ write32(0x5344003e, (void *)(uintptr_t)(mmio + 0xe4210));
mdelay(1);
- read32(mmio + 0xc4000);
+ read32((void *)(uintptr_t)(mmio + 0xc4000));
}
int i915lightup_sandy(const struct i915_gpu_controller_info *info,
@@ -166,23 +165,24 @@ int i915lightup_sandy(const struct i915_gpu_controller_info *info,
u8 edid_data[128];
struct edid edid;
- write32(mmio + 0x00070080, 0x00000000);
- write32(mmio + DSPCNTR(0), 0x00000000);
- write32(mmio + 0x00071180, 0x00000000);
- write32(mmio + CPU_VGACNTRL, 0x0000298e | VGA_DISP_DISABLE);
- write32(mmio + 0x0007019c, 0x00000000);
- write32(mmio + 0x0007119c, 0x00000000);
- write32(mmio + 0x000fc008, 0x2c010000);
- write32(mmio + 0x000fc020, 0x2c010000);
- write32(mmio + 0x000fc038, 0x2c010000);
- write32(mmio + 0x000fc050, 0x2c010000);
- write32(mmio + 0x000fc408, 0x2c010000);
- write32(mmio + 0x000fc420, 0x2c010000);
- write32(mmio + 0x000fc438, 0x2c010000);
- write32(mmio + 0x000fc450, 0x2c010000);
+ write32(0x00000000, (void *)(uintptr_t)(mmio + 0x00070080));
+ write32(0x00000000, (void *)(uintptr_t)(mmio + DSPCNTR(0)));
+ write32(0x00000000, (void *)(uintptr_t)(mmio + 0x00071180));
+ write32(0x0000298e | VGA_DISP_DISABLE,
+ (void *)(uintptr_t)(mmio + CPU_VGACNTRL));
+ write32(0x00000000, (void *)(uintptr_t)(mmio + 0x0007019c));
+ write32(0x00000000, (void *)(uintptr_t)(mmio + 0x0007119c));
+ write32(0x2c010000, (void *)(uintptr_t)(mmio + 0x000fc008));
+ write32(0x2c010000, (void *)(uintptr_t)(mmio + 0x000fc020));
+ write32(0x2c010000, (void *)(uintptr_t)(mmio + 0x000fc038));
+ write32(0x2c010000, (void *)(uintptr_t)(mmio + 0x000fc050));
+ write32(0x2c010000, (void *)(uintptr_t)(mmio + 0x000fc408));
+ write32(0x2c010000, (void *)(uintptr_t)(mmio + 0x000fc420));
+ write32(0x2c010000, (void *)(uintptr_t)(mmio + 0x000fc438));
+ write32(0x2c010000, (void *)(uintptr_t)(mmio + 0x000fc450));
vga_gr_write(0x18, 0);
- write32(mmio + 0x00042004, 0x02000000);
- write32(mmio + 0x000fd034, 0x8421ffe0);
+ write32(0x02000000, (void *)(uintptr_t)(mmio + 0x00042004));
+ write32(0x8421ffe0, (void *)(uintptr_t)(mmio + 0x000fd034));
/* Setup GTT. */
for (i = 0; i < 0x2000; i++)
@@ -256,12 +256,13 @@ int i915lightup_sandy(const struct i915_gpu_controller_info *info,
edid.bytes_per_line = (edid.bytes_per_line + 63) & ~63;
- write32(mmio + DSPCNTR(0), DISPPLANE_BGRX888);
- write32(mmio + DSPADDR(0), 0);
- write32(mmio + DSPSTRIDE(0), edid.bytes_per_line);
- write32(mmio + DSPSURF(0), 0);
+ write32(DISPPLANE_BGRX888, (void *)(uintptr_t)(mmio + DSPCNTR(0)));
+ write32(0, (void *)(uintptr_t)(mmio + DSPADDR(0)));
+ write32(edid.bytes_per_line, (void *)(uintptr_t)(mmio + DSPSTRIDE(0)));
+ write32(0, (void *)(uintptr_t)(mmio + DSPSURF(0)));
for (i = 0; i < 0x100; i++)
- write32(mmio + LGC_PALETTE(0) + 4 * i, i * 0x010101);
+ write32(i * 0x010101,
+ (void *)(uintptr_t)(mmio + LGC_PALETTE(0) + 4 * i));
#endif
/* Find suitable divisors. */
@@ -341,172 +342,149 @@ int i915lightup_sandy(const struct i915_gpu_controller_info *info,
120000 * (5 * pixel_m1 + pixel_m2) / pixel_n
/ (pixel_p1 * 7));
- write32(mmio + PCH_LVDS,
- (hpolarity << 20) | (vpolarity << 21)
- | (info->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL
- | LVDS_CLOCK_BOTH_POWERUP_ALL : 0)
- | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL
- | LVDS_DETECTED);
- write32(mmio + BLC_PWM_CPU_CTL2, (1 << 31));
- write32(mmio + PCH_DREF_CONTROL, (info->use_spread_spectrum_clock
- ? 0x1002 : 0x400));
+ write32((hpolarity << 20) | (vpolarity << 21) | (info->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL | LVDS_DETECTED,
+ (void *)(uintptr_t)(mmio + PCH_LVDS));
+ write32((1 << 31), (void *)(uintptr_t)(mmio + BLC_PWM_CPU_CTL2));
+ write32((info->use_spread_spectrum_clock ? 0x1002 : 0x400),
+ (void *)(uintptr_t)(mmio + PCH_DREF_CONTROL));
mdelay(1);
- write32(mmio + PCH_PP_CONTROL, PANEL_UNLOCK_REGS
- | (read32(mmio + PCH_PP_CONTROL) & ~PANEL_UNLOCK_MASK));
- write32(mmio + _PCH_FP0(0),
- ((pixel_n - 2) << 16)
- | ((pixel_m1 - 2) << 8) | pixel_m2);
- write32(mmio + _PCH_DPLL(0),
- DPLL_VCO_ENABLE | DPLLB_MODE_LVDS
- | (info->lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7
- : DPLLB_LVDS_P2_CLOCK_DIV_14)
- | (0x10000 << (pixel_p1 - 1))
- | ((info->use_spread_spectrum_clock ? 3 : 0) << 13)
- | (0x1 << (pixel_p1 - 1)));
+ write32(PANEL_UNLOCK_REGS | (read32((void *)(uintptr_t)(mmio + PCH_PP_CONTROL)) & ~PANEL_UNLOCK_MASK),
+ (void *)(uintptr_t)(mmio + PCH_PP_CONTROL));
+ write32(((pixel_n - 2) << 16) | ((pixel_m1 - 2) << 8) | pixel_m2,
+ (void *)(uintptr_t)(mmio + _PCH_FP0(0)));
+ write32(DPLL_VCO_ENABLE | DPLLB_MODE_LVDS | (info->lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 : DPLLB_LVDS_P2_CLOCK_DIV_14) | (0x10000 << (pixel_p1 - 1)) | ((info->use_spread_spectrum_clock ? 3 : 0) << 13) | (0x1 << (pixel_p1 - 1)),
+ (void *)(uintptr_t)(mmio + _PCH_DPLL(0)));
mdelay(1);
- write32(mmio + 0xc7000, 0x8);
+ write32(0x8, (void *)(uintptr_t)(mmio + 0xc7000));
mdelay(1);
- write32(mmio + _PCH_DPLL(0),
- DPLL_VCO_ENABLE | DPLLB_MODE_LVDS
- | (info->lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7
- : DPLLB_LVDS_P2_CLOCK_DIV_14)
- | (0x10000 << (pixel_p1 - 1))
- | ((info->use_spread_spectrum_clock ? 3 : 0) << 13)
- | (0x1 << (pixel_p1 - 1)));
+ write32(DPLL_VCO_ENABLE | DPLLB_MODE_LVDS | (info->lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 : DPLLB_LVDS_P2_CLOCK_DIV_14) | (0x10000 << (pixel_p1 - 1)) | ((info->use_spread_spectrum_clock ? 3 : 0) << 13) | (0x1 << (pixel_p1 - 1)),
+ (void *)(uintptr_t)(mmio + _PCH_DPLL(0)));
/* Re-lock the registers. */
- write32(mmio + PCH_PP_CONTROL,
- (read32(mmio + PCH_PP_CONTROL) & ~PANEL_UNLOCK_MASK));
-
- write32(mmio + PCH_LVDS,
- (hpolarity << 20) | (vpolarity << 21)
- | (info->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL
- | LVDS_CLOCK_BOTH_POWERUP_ALL : 0)
- | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL
- | LVDS_DETECTED);
-
- write32(mmio + HTOTAL(0),
- ((hactive + right_border + hblank - 1) << 16)
- | (hactive - 1));
- write32(mmio + HBLANK(0),
- ((hactive + right_border + hblank - 1) << 16)
- | (hactive + right_border - 1));
- write32(mmio + HSYNC(0),
- ((hactive + right_border + hfront_porch + hsync - 1) << 16)
- | (hactive + right_border + hfront_porch - 1));
-
- write32(mmio + VTOTAL(0), ((vactive + bottom_border + vblank - 1) << 16)
- | (vactive - 1));
- write32(mmio + VBLANK(0), ((vactive + bottom_border + vblank - 1) << 16)
- | (vactive + bottom_border - 1));
- write32(mmio + VSYNC(0),
- (vactive + bottom_border + vfront_porch + vsync - 1)
- | (vactive + bottom_border + vfront_porch - 1));
-
- write32(mmio + PIPECONF(0), PIPECONF_DISABLE);
-
- write32(mmio + 0xf0008, 0);
+ write32((read32((void *)(uintptr_t)(mmio + PCH_PP_CONTROL)) & ~PANEL_UNLOCK_MASK),
+ (void *)(uintptr_t)(mmio + PCH_PP_CONTROL));
+
+ write32((hpolarity << 20) | (vpolarity << 21) | (info->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL | LVDS_DETECTED,
+ (void *)(uintptr_t)(mmio + PCH_LVDS));
+
+ write32(((hactive + right_border + hblank - 1) << 16) | (hactive - 1),
+ (void *)(uintptr_t)(mmio + HTOTAL(0)));
+ write32(((hactive + right_border + hblank - 1) << 16) | (hactive + right_border - 1),
+ (void *)(uintptr_t)(mmio + HBLANK(0)));
+ write32(((hactive + right_border + hfront_porch + hsync - 1) << 16) | (hactive + right_border + hfront_porch - 1),
+ (void *)(uintptr_t)(mmio + HSYNC(0)));
+
+ write32(((vactive + bottom_border + vblank - 1) << 16) | (vactive - 1),
+ (void *)(uintptr_t)(mmio + VTOTAL(0)));
+ write32(((vactive + bottom_border + vblank - 1) << 16) | (vactive + bottom_border - 1),
+ (void *)(uintptr_t)(mmio + VBLANK(0)));
+ write32((vactive + bottom_border + vfront_porch + vsync - 1) | (vactive + bottom_border + vfront_porch - 1),
+ (void *)(uintptr_t)(mmio + VSYNC(0)));
+
+ write32(PIPECONF_DISABLE, (void *)(uintptr_t)(mmio + PIPECONF(0)));
+
+ write32(0, (void *)(uintptr_t)(mmio + 0xf0008));
#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
- write32(mmio + PIPESRC(0), ((hactive - 1) << 16) | (vactive - 1));
- write32(mmio + PF_CTL(0),0);
- write32(mmio + PF_WIN_SZ(0), 0);
- write32(mmio + PF_WIN_POS(0), 0);
+ write32(((hactive - 1) << 16) | (vactive - 1),
+ (void *)(uintptr_t)(mmio + PIPESRC(0)));
+ write32(0, (void *)(uintptr_t)(mmio + PF_CTL(0)));
+ write32(0, (void *)(uintptr_t)(mmio + PF_WIN_SZ(0)));
+ write32(0, (void *)(uintptr_t)(mmio + PF_WIN_POS(0)));
#else
- write32(mmio + PIPESRC(0), (719 << 16) | 399);
- write32(mmio + PF_WIN_POS(0), 0);
- write32(mmio + PF_CTL(0),PF_ENABLE | PF_FILTER_MED_3x3);
- write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16));
+ write32((719 << 16) | 399, (void *)(uintptr_t)(mmio + PIPESRC(0)));
+ write32(0, (void *)(uintptr_t)(mmio + PF_WIN_POS(0)));
+ write32(PF_ENABLE | PF_FILTER_MED_3x3,
+ (void *)(uintptr_t)(mmio + PF_CTL(0)));
+ write32(vactive | (hactive << 16),
+ (void *)(uintptr_t)(mmio + PF_WIN_SZ(0)));
#endif
mdelay(1);
- write32(mmio + PIPE_DATA_M1(0), 0x7e000000 | data_m1);
- write32(mmio + PIPE_DATA_N1(0), data_n1);
- write32(mmio + PIPE_LINK_M1(0), link_m1);
- write32(mmio + PIPE_LINK_N1(0), link_n1);
+ write32(0x7e000000 | data_m1,
+ (void *)(uintptr_t)(mmio + PIPE_DATA_M1(0)));
+ write32(data_n1, (void *)(uintptr_t)(mmio + PIPE_DATA_N1(0)));
+ write32(link_m1, (void *)(uintptr_t)(mmio + PIPE_LINK_M1(0)));
+ write32(link_n1, (void *)(uintptr_t)(mmio + PIPE_LINK_N1(0)));
link_train(mmio);
#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
- write32(mmio+CPU_VGACNTRL,0x298e | VGA_DISP_DISABLE);
+ write32(0x298e | VGA_DISP_DISABLE,
+ (void *)(uintptr_t)(mmio + CPU_VGACNTRL));
#else
- write32(mmio+CPU_VGACNTRL,0x298e);
+ write32(0x298e, (void *)(uintptr_t)(mmio + CPU_VGACNTRL));
#endif
- write32(mmio+0x60100,0x44300);
- write32(mmio+0x60100,0x80044f00);
+ write32(0x44300, (void *)(uintptr_t)(mmio + 0x60100));
+ write32(0x80044f00, (void *)(uintptr_t)(mmio + 0x60100));
mdelay(1);
- read32(mmio + 0x000f0014); // = 0x00000600
+ read32((void *)(uintptr_t)(mmio + 0x000f0014)); // = 0x00000600
#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
- write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888);
+ write32(DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888,
+ (void *)(uintptr_t)(mmio + DSPCNTR(0)));
mdelay(1);
#endif
- write32(mmio + TRANS_HTOTAL(0),
- ((hactive + right_border + hblank - 1) << 16)
- | (hactive - 1));
- write32(mmio + TRANS_HBLANK(0),
- ((hactive + right_border + hblank - 1) << 16)
- | (hactive + right_border - 1));
- write32(mmio + TRANS_HSYNC(0),
- ((hactive + right_border + hfront_porch + hsync - 1) << 16)
- | (hactive + right_border + hfront_porch - 1));
-
- write32(mmio + TRANS_VTOTAL(0),
- ((vactive + bottom_border + vblank - 1) << 16)
- | (vactive - 1));
- write32(mmio + TRANS_VBLANK(0),
- ((vactive + bottom_border + vblank - 1) << 16)
- | (vactive + bottom_border - 1));
- write32(mmio + TRANS_VSYNC(0),
- (vactive + bottom_border + vfront_porch + vsync - 1)
- | (vactive + bottom_border + vfront_porch - 1));
+ write32(((hactive + right_border + hblank - 1) << 16) | (hactive - 1),
+ (void *)(uintptr_t)(mmio + TRANS_HTOTAL(0)));
+ write32(((hactive + right_border + hblank - 1) << 16) | (hactive + right_border - 1),
+ (void *)(uintptr_t)(mmio + TRANS_HBLANK(0)));
+ write32(((hactive + right_border + hfront_porch + hsync - 1) << 16) | (hactive + right_border + hfront_porch - 1),
+ (void *)(uintptr_t)(mmio + TRANS_HSYNC(0)));
+
+ write32(((vactive + bottom_border + vblank - 1) << 16) | (vactive - 1),
+ (void *)(uintptr_t)(mmio + TRANS_VTOTAL(0)));
+ write32(((vactive + bottom_border + vblank - 1) << 16) | (vactive + bottom_border - 1),
+ (void *)(uintptr_t)(mmio + TRANS_VBLANK(0)));
+ write32((vactive + bottom_border + vfront_porch + vsync - 1) | (vactive + bottom_border + vfront_porch - 1),
+ (void *)(uintptr_t)(mmio + TRANS_VSYNC(0)));
link_normal_operation(mmio);
- write32(mmio + PCH_PP_CONTROL, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
+ write32(PANEL_UNLOCK_REGS | PANEL_POWER_OFF,
+ (void *)(uintptr_t)(mmio + PCH_PP_CONTROL));
mdelay(1);
- write32(mmio + PCH_TRANSCONF(0), TRANS_ENABLE | TRANS_6BPC
+ write32(TRANS_ENABLE | TRANS_6BPC
#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
- | TRANS_STATE_MASK
+
+ | TRANS_STATE_MASK
#endif
- );
- write32(mmio + PCH_LVDS,
- LVDS_PORT_ENABLE
- | (hpolarity << 20) | (vpolarity << 21)
- | (info->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL
- | LVDS_CLOCK_BOTH_POWERUP_ALL : 0)
- | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL
- | LVDS_DETECTED);
-
- write32(mmio + PCH_PP_CONTROL, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
- write32(mmio + PCH_PP_CONTROL, PANEL_UNLOCK_REGS | PANEL_POWER_RESET);
+, (void *)(uintptr_t)(mmio + PCH_TRANSCONF(0)));
+ write32(LVDS_PORT_ENABLE | (hpolarity << 20) | (vpolarity << 21) | (info->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL | LVDS_DETECTED,
+ (void *)(uintptr_t)(mmio + PCH_LVDS));
+
+ write32(PANEL_UNLOCK_REGS | PANEL_POWER_OFF,
+ (void *)(uintptr_t)(mmio + PCH_PP_CONTROL));
+ write32(PANEL_UNLOCK_REGS | PANEL_POWER_RESET,
+ (void *)(uintptr_t)(mmio + PCH_PP_CONTROL));
mdelay(1);
- write32(mmio + PCH_PP_CONTROL, PANEL_UNLOCK_REGS
- | PANEL_POWER_ON | PANEL_POWER_RESET);
+ write32(PANEL_UNLOCK_REGS | PANEL_POWER_ON | PANEL_POWER_RESET,
+ (void *)(uintptr_t)(mmio + PCH_PP_CONTROL));
printk (BIOS_DEBUG, "waiting for panel powerup\n");
while (1)
{
u32 reg32;
- reg32 = read32(mmio + PCH_PP_STATUS);
+ reg32 = read32((void *)(uintptr_t)(mmio + PCH_PP_STATUS));
if (((reg32 >> 28) & 3) == 0)
break;
}
printk (BIOS_DEBUG, "panel powered up\n");
- write32(mmio + PCH_PP_CONTROL, PANEL_POWER_ON | PANEL_POWER_RESET);
+ write32(PANEL_POWER_ON | PANEL_POWER_RESET,
+ (void *)(uintptr_t)(mmio + PCH_PP_CONTROL));
/* Enable screen memory. */
vga_sr_write(1, vga_sr_read(1) & ~0x20);
/* Clear interrupts. */
- write32(mmio + DEIIR, 0xffffffff);
- write32(mmio + SDEIIR, 0xffffffff);
+ write32(0xffffffff, (void *)(uintptr_t)(mmio + DEIIR));
+ write32(0xffffffff, (void *)(uintptr_t)(mmio + SDEIIR));
#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
memset ((void *) lfb, 0, edid.x_resolution * edid.y_resolution * 4);
diff --git a/src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c b/src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c
index 08cceea..166b997 100644
--- a/src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c
+++ b/src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c
@@ -38,88 +38,88 @@
static void train_link(u32 mmio)
{
/* Clear interrupts. */
- write32(mmio + DEIIR, 0xffffffff);
+ write32(0xffffffff, (void *)(uintptr_t)(mmio + DEIIR));
- write32(mmio + 0xf000c, 0x2040);
- write32(mmio + 0xf000c, 0x2050);
- write32(mmio + 0x60100, 0x44000);
- write32(mmio + 0xf000c, 0x22050);
+ write32(0x2040, (void *)(uintptr_t)(mmio + 0xf000c));
+ write32(0x2050, (void *)(uintptr_t)(mmio + 0xf000c));
+ write32(0x44000, (void *)(uintptr_t)(mmio + 0x60100));
+ write32(0x22050, (void *)(uintptr_t)(mmio + 0xf000c));
mdelay(1);
- write32(mmio + 0x000f0018, 0x0000008ff);
- write32(mmio + 0x000f1018, 0x0000008ff);
+ write32(0x0000008ff, (void *)(uintptr_t)(mmio + 0x000f0018));
+ write32(0x0000008ff, (void *)(uintptr_t)(mmio + 0x000f1018));
- write32(mmio + 0x000f000c, 0x001a2050);
- write32(mmio + 0x00060100, 0x001c4000);
+ write32(0x001a2050, (void *)(uintptr_t)(mmio + 0x000f000c));
+ write32(0x001c4000, (void *)(uintptr_t)(mmio + 0x00060100));
- write32(mmio + 0x00060100, 0x801c4000);
- write32(mmio + 0x000f000c, 0x801a2050);
+ write32(0x801c4000, (void *)(uintptr_t)(mmio + 0x00060100));
+ write32(0x801a2050, (void *)(uintptr_t)(mmio + 0x000f000c));
- write32(mmio + 0x00060100, 0x801c4000);
- write32(mmio + 0x000f000c, 0x801a2050);
+ write32(0x801c4000, (void *)(uintptr_t)(mmio + 0x00060100));
+ write32(0x801a2050, (void *)(uintptr_t)(mmio + 0x000f000c));
mdelay(1);
- read32(mmio + 0x000f0014); // = 0x00000100
- write32(mmio + 0x000f0014, 0x00000100);
- write32(mmio + 0x00060100, 0x901c4000);
- write32(mmio + 0x000f000c, 0x801a2150);
+ read32((void *)(uintptr_t)(mmio + 0x000f0014)); // = 0x00000100
+ write32(0x00000100, (void *)(uintptr_t)(mmio + 0x000f0014));
+ write32(0x901c4000, (void *)(uintptr_t)(mmio + 0x00060100));
+ write32(0x801a2150, (void *)(uintptr_t)(mmio + 0x000f000c));
mdelay(1);
- read32(mmio + 0x000f0014); // = 0x00000600
+ read32((void *)(uintptr_t)(mmio + 0x000f0014)); // = 0x00000600
}
static void power_port(u32 mmio)
{
- read32(mmio + 0x000e1100); // = 0x00000000
- write32(mmio + 0x000e1100, 0x00000000);
- write32(mmio + 0x000e1100, 0x00010000);
- read32(mmio + 0x000e1100); // = 0x00010000
- read32(mmio + 0x000e1100); // = 0x00010000
- read32(mmio + 0x000e1100); // = 0x00000000
- write32(mmio + 0x000e1100, 0x00000000);
- read32(mmio + 0x000e1100); // = 0x00000000
- read32(mmio + 0x000e4200); // = 0x0000001c
- write32(mmio + 0x000e4210, 0x8004003e);
- write32(mmio + 0x000e4214, 0x80060002);
- write32(mmio + 0x000e4218, 0x01000000);
- read32(mmio + 0x000e4210); // = 0x5144003e
- write32(mmio + 0x000e4210, 0x5344003e);
- read32(mmio + 0x000e4210); // = 0x0144003e
- write32(mmio + 0x000e4210, 0x8074003e);
- read32(mmio + 0x000e4210); // = 0x5144003e
- read32(mmio + 0x000e4210); // = 0x5144003e
- write32(mmio + 0x000e4210, 0x5344003e);
- read32(mmio + 0x000e4210); // = 0x0144003e
- write32(mmio + 0x000e4210, 0x8074003e);
- read32(mmio + 0x000e4210); // = 0x5144003e
- read32(mmio + 0x000e4210); // = 0x5144003e
- write32(mmio + 0x000e4210, 0x5344003e);
- read32(mmio + 0x000e4210); // = 0x0144003e
- write32(mmio + 0x000e4210, 0x8074003e);
- read32(mmio + 0x000e4210); // = 0x5144003e
- read32(mmio + 0x000e4210); // = 0x5144003e
- write32(mmio + 0x000e4210, 0x5344003e);
- write32(mmio + 0x000e4f00, 0x0100030c);
- write32(mmio + 0x000e4f04, 0x00b8230c);
- write32(mmio + 0x000e4f08, 0x06f8930c);
- write32(mmio + 0x000e4f0c, 0x09f8e38e);
- write32(mmio + 0x000e4f10, 0x00b8030c);
- write32(mmio + 0x000e4f14, 0x0b78830c);
- write32(mmio + 0x000e4f18, 0x0ff8d3cf);
- write32(mmio + 0x000e4f1c, 0x01e8030c);
- write32(mmio + 0x000e4f20, 0x0ff863cf);
- write32(mmio + 0x000e4f24, 0x0ff803cf);
- write32(mmio + 0x000c4030, 0x00001000);
- read32(mmio + 0x000c4000); // = 0x00000000
- write32(mmio + 0x000c4030, 0x00001000);
- read32(mmio + 0x000e1150); // = 0x0000001c
- write32(mmio + 0x000e1150, 0x0000089c);
- write32(mmio + 0x000fcc00, 0x01986f00);
- write32(mmio + 0x000fcc0c, 0x01986f00);
- write32(mmio + 0x000fcc18, 0x01986f00);
- write32(mmio + 0x000fcc24, 0x01986f00);
- read32(mmio + 0x000c4000); // = 0x00000000
- read32(mmio + 0x000e1180); // = 0x40000002
+ read32((void *)(uintptr_t)(mmio + 0x000e1100)); // = 0x00000000
+ write32(0x00000000, (void *)(uintptr_t)(mmio + 0x000e1100));
+ write32(0x00010000, (void *)(uintptr_t)(mmio + 0x000e1100));
+ read32((void *)(uintptr_t)(mmio + 0x000e1100)); // = 0x00010000
+ read32((void *)(uintptr_t)(mmio + 0x000e1100)); // = 0x00010000
+ read32((void *)(uintptr_t)(mmio + 0x000e1100)); // = 0x00000000
+ write32(0x00000000, (void *)(uintptr_t)(mmio + 0x000e1100));
+ read32((void *)(uintptr_t)(mmio + 0x000e1100)); // = 0x00000000
+ read32((void *)(uintptr_t)(mmio + 0x000e4200)); // = 0x0000001c
+ write32(0x8004003e, (void *)(uintptr_t)(mmio + 0x000e4210));
+ write32(0x80060002, (void *)(uintptr_t)(mmio + 0x000e4214));
+ write32(0x01000000, (void *)(uintptr_t)(mmio + 0x000e4218));
+ read32((void *)(uintptr_t)(mmio + 0x000e4210)); // = 0x5144003e
+ write32(0x5344003e, (void *)(uintptr_t)(mmio + 0x000e4210));
+ read32((void *)(uintptr_t)(mmio + 0x000e4210)); // = 0x0144003e
+ write32(0x8074003e, (void *)(uintptr_t)(mmio + 0x000e4210));
+ read32((void *)(uintptr_t)(mmio + 0x000e4210)); // = 0x5144003e
+ read32((void *)(uintptr_t)(mmio + 0x000e4210)); // = 0x5144003e
+ write32(0x5344003e, (void *)(uintptr_t)(mmio + 0x000e4210));
+ read32((void *)(uintptr_t)(mmio + 0x000e4210)); // = 0x0144003e
+ write32(0x8074003e, (void *)(uintptr_t)(mmio + 0x000e4210));
+ read32((void *)(uintptr_t)(mmio + 0x000e4210)); // = 0x5144003e
+ read32((void *)(uintptr_t)(mmio + 0x000e4210)); // = 0x5144003e
+ write32(0x5344003e, (void *)(uintptr_t)(mmio + 0x000e4210));
+ read32((void *)(uintptr_t)(mmio + 0x000e4210)); // = 0x0144003e
+ write32(0x8074003e, (void *)(uintptr_t)(mmio + 0x000e4210));
+ read32((void *)(uintptr_t)(mmio + 0x000e4210)); // = 0x5144003e
+ read32((void *)(uintptr_t)(mmio + 0x000e4210)); // = 0x5144003e
+ write32(0x5344003e, (void *)(uintptr_t)(mmio + 0x000e4210));
+ write32(0x0100030c, (void *)(uintptr_t)(mmio + 0x000e4f00));
+ write32(0x00b8230c, (void *)(uintptr_t)(mmio + 0x000e4f04));
+ write32(0x06f8930c, (void *)(uintptr_t)(mmio + 0x000e4f08));
+ write32(0x09f8e38e, (void *)(uintptr_t)(mmio + 0x000e4f0c));
+ write32(0x00b8030c, (void *)(uintptr_t)(mmio + 0x000e4f10));
+ write32(0x0b78830c, (void *)(uintptr_t)(mmio + 0x000e4f14));
+ write32(0x0ff8d3cf, (void *)(uintptr_t)(mmio + 0x000e4f18));
+ write32(0x01e8030c, (void *)(uintptr_t)(mmio + 0x000e4f1c));
+ write32(0x0ff863cf, (void *)(uintptr_t)(mmio + 0x000e4f20));
+ write32(0x0ff803cf, (void *)(uintptr_t)(mmio + 0x000e4f24));
+ write32(0x00001000, (void *)(uintptr_t)(mmio + 0x000c4030));
+ read32((void *)(uintptr_t)(mmio + 0x000c4000)); // = 0x00000000
+ write32(0x00001000, (void *)(uintptr_t)(mmio + 0x000c4030));
+ read32((void *)(uintptr_t)(mmio + 0x000e1150)); // = 0x0000001c
+ write32(0x0000089c, (void *)(uintptr_t)(mmio + 0x000e1150));
+ write32(0x01986f00, (void *)(uintptr_t)(mmio + 0x000fcc00));
+ write32(0x01986f00, (void *)(uintptr_t)(mmio + 0x000fcc0c));
+ write32(0x01986f00, (void *)(uintptr_t)(mmio + 0x000fcc18));
+ write32(0x01986f00, (void *)(uintptr_t)(mmio + 0x000fcc24));
+ read32((void *)(uintptr_t)(mmio + 0x000c4000)); // = 0x00000000
+ read32((void *)(uintptr_t)(mmio + 0x000e1180)); // = 0x40000002
}
int i915lightup_sandy(const struct i915_gpu_controller_info *info,
@@ -144,23 +144,24 @@ int i915lightup_sandy(const struct i915_gpu_controller_info *info,
u32 link_m1;
u32 link_n1 = 0x00080000;
- write32(mmio + 0x00070080, 0x00000000);
- write32(mmio + DSPCNTR(0), 0x00000000);
- write32(mmio + 0x00071180, 0x00000000);
- write32(mmio + CPU_VGACNTRL, 0x0000298e | VGA_DISP_DISABLE);
- write32(mmio + 0x0007019c, 0x00000000);
- write32(mmio + 0x0007119c, 0x00000000);
- write32(mmio + 0x000ec008, 0x2c010000);
- write32(mmio + 0x000ec020, 0x2c010000);
- write32(mmio + 0x000ec038, 0x2c010000);
- write32(mmio + 0x000ec050, 0x2c010000);
- write32(mmio + 0x000ec408, 0x2c010000);
- write32(mmio + 0x000ec420, 0x2c010000);
- write32(mmio + 0x000ec438, 0x2c010000);
- write32(mmio + 0x000ec450, 0x2c010000);
+ write32(0x00000000, (void *)(uintptr_t)(mmio + 0x00070080));
+ write32(0x00000000, (void *)(uintptr_t)(mmio + DSPCNTR(0)));
+ write32(0x00000000, (void *)(uintptr_t)(mmio + 0x00071180));
+ write32(0x0000298e | VGA_DISP_DISABLE,
+ (void *)(uintptr_t)(mmio + CPU_VGACNTRL));
+ write32(0x00000000, (void *)(uintptr_t)(mmio + 0x0007019c));
+ write32(0x00000000, (void *)(uintptr_t)(mmio + 0x0007119c));
+ write32(0x2c010000, (void *)(uintptr_t)(mmio + 0x000ec008));
+ write32(0x2c010000, (void *)(uintptr_t)(mmio + 0x000ec020));
+ write32(0x2c010000, (void *)(uintptr_t)(mmio + 0x000ec038));
+ write32(0x2c010000, (void *)(uintptr_t)(mmio + 0x000ec050));
+ write32(0x2c010000, (void *)(uintptr_t)(mmio + 0x000ec408));
+ write32(0x2c010000, (void *)(uintptr_t)(mmio + 0x000ec420));
+ write32(0x2c010000, (void *)(uintptr_t)(mmio + 0x000ec438));
+ write32(0x2c010000, (void *)(uintptr_t)(mmio + 0x000ec450));
vga_gr_write(0x18, 0);
- write32(mmio + 0x00042004, 0x02000000);
- write32(mmio + 0x000fd034, 0x8421ffe0);
+ write32(0x02000000, (void *)(uintptr_t)(mmio + 0x00042004));
+ write32(0x8421ffe0, (void *)(uintptr_t)(mmio + 0x000fd034));
/* Setup GTT. */
for (i = 0; i < 0x2000; i++)
@@ -226,12 +227,13 @@ int i915lightup_sandy(const struct i915_gpu_controller_info *info,
edid.bytes_per_line = (edid.bytes_per_line + 63) & ~63;
- write32(mmio + DSPCNTR(0), DISPPLANE_BGRX888);
- write32(mmio + DSPADDR(0), 0);
- write32(mmio + DSPSTRIDE(0), edid.bytes_per_line);
- write32(mmio + DSPSURF(0), 0);
+ write32(DISPPLANE_BGRX888, (void *)(uintptr_t)(mmio + DSPCNTR(0)));
+ write32(0, (void *)(uintptr_t)(mmio + DSPADDR(0)));
+ write32(edid.bytes_per_line, (void *)(uintptr_t)(mmio + DSPSTRIDE(0)));
+ write32(0, (void *)(uintptr_t)(mmio + DSPSURF(0)));
for (i = 0; i < 0x100; i++)
- write32(mmio + LGC_PALETTE(0) + 4 * i, i * 0x010101);
+ write32(i * 0x010101,
+ (void *)(uintptr_t)(mmio + LGC_PALETTE(0) + 4 * i));
#endif
/* Find suitable divisors. */
@@ -304,168 +306,146 @@ int i915lightup_sandy(const struct i915_gpu_controller_info *info,
120000 * (5 * pixel_m1 + pixel_m2) / pixel_n
/ (pixel_p1 * 7));
- write32(mmio + PCH_LVDS,
- (hpolarity << 20) | (vpolarity << 21)
- | (info->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL
- | LVDS_CLOCK_BOTH_POWERUP_ALL : 0)
- | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL
- | LVDS_DETECTED);
- write32(mmio + BLC_PWM_CPU_CTL2, (1 << 31));
- write32(mmio + PCH_DREF_CONTROL, (info->use_spread_spectrum_clock
- ? 0x1002 : 0x400));
+ write32((hpolarity << 20) | (vpolarity << 21) | (info->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL | LVDS_DETECTED,
+ (void *)(uintptr_t)(mmio + PCH_LVDS));
+ write32((1 << 31), (void *)(uintptr_t)(mmio + BLC_PWM_CPU_CTL2));
+ write32((info->use_spread_spectrum_clock ? 0x1002 : 0x400),
+ (void *)(uintptr_t)(mmio + PCH_DREF_CONTROL));
mdelay(1);
- write32(mmio + PCH_PP_CONTROL, PANEL_UNLOCK_REGS
- | (read32(mmio + PCH_PP_CONTROL) & ~PANEL_UNLOCK_MASK));
- write32(mmio + _PCH_FP0(0),
- ((pixel_n - 2) << 16)
- | ((pixel_m1 - 2) << 8) | pixel_m2);
- write32(mmio + PCH_DPLL_SEL, 8);
- write32(mmio + _PCH_DPLL(0),
- DPLL_VCO_ENABLE | DPLLB_MODE_LVDS
- | (info->lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7
- : DPLLB_LVDS_P2_CLOCK_DIV_14)
- | (0x10000 << (pixel_p1 - 1))
- | ((info->use_spread_spectrum_clock ? 3 : 0) << 13)
- | (0x1 << (pixel_p1 - 1)));
+ write32(PANEL_UNLOCK_REGS | (read32((void *)(uintptr_t)(mmio + PCH_PP_CONTROL)) & ~PANEL_UNLOCK_MASK),
+ (void *)(uintptr_t)(mmio + PCH_PP_CONTROL));
+ write32(((pixel_n - 2) << 16) | ((pixel_m1 - 2) << 8) | pixel_m2,
+ (void *)(uintptr_t)(mmio + _PCH_FP0(0)));
+ write32(8, (void *)(uintptr_t)(mmio + PCH_DPLL_SEL));
+ write32(DPLL_VCO_ENABLE | DPLLB_MODE_LVDS | (info->lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 : DPLLB_LVDS_P2_CLOCK_DIV_14) | (0x10000 << (pixel_p1 - 1)) | ((info->use_spread_spectrum_clock ? 3 : 0) << 13) | (0x1 << (pixel_p1 - 1)),
+ (void *)(uintptr_t)(mmio + _PCH_DPLL(0)));
mdelay(1);
- write32(mmio + _PCH_DPLL(0),
- DPLL_VCO_ENABLE | DPLLB_MODE_LVDS
- | (info->lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7
- : DPLLB_LVDS_P2_CLOCK_DIV_14)
- | (0x10000 << (pixel_p1 - 1))
- | ((info->use_spread_spectrum_clock ? 3 : 0) << 13)
- | (0x1 << (pixel_p1 - 1)));
+ write32(DPLL_VCO_ENABLE | DPLLB_MODE_LVDS | (info->lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 : DPLLB_LVDS_P2_CLOCK_DIV_14) | (0x10000 << (pixel_p1 - 1)) | ((info->use_spread_spectrum_clock ? 3 : 0) << 13) | (0x1 << (pixel_p1 - 1)),
+ (void *)(uintptr_t)(mmio + _PCH_DPLL(0)));
/* Re-lock the registers. */
- write32(mmio + PCH_PP_CONTROL,
- (read32(mmio + PCH_PP_CONTROL) & ~PANEL_UNLOCK_MASK));
-
- write32(mmio + PCH_LVDS,
- (hpolarity << 20) | (vpolarity << 21)
- | (info->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL
- | LVDS_CLOCK_BOTH_POWERUP_ALL : 0)
- | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL
- | LVDS_DETECTED);
-
- write32(mmio + HTOTAL(0),
- ((hactive + right_border + hblank - 1) << 16)
- | (hactive - 1));
- write32(mmio + HBLANK(0),
- ((hactive + right_border + hblank - 1) << 16)
- | (hactive + right_border - 1));
- write32(mmio + HSYNC(0),
- ((hactive + right_border + hfront_porch + hsync - 1) << 16)
- | (hactive + right_border + hfront_porch - 1));
-
- write32(mmio + VTOTAL(0), ((vactive + bottom_border + vblank - 1) << 16)
- | (vactive - 1));
- write32(mmio + VBLANK(0), ((vactive + bottom_border + vblank - 1) << 16)
- | (vactive + bottom_border - 1));
- write32(mmio + VSYNC(0),
- (vactive + bottom_border + vfront_porch + vsync - 1)
- | (vactive + bottom_border + vfront_porch - 1));
-
- write32(mmio + PIPECONF(0), PIPECONF_DISABLE);
-
- write32(mmio + PF_WIN_POS(0), 0);
+ write32((read32((void *)(uintptr_t)(mmio + PCH_PP_CONTROL)) & ~PANEL_UNLOCK_MASK),
+ (void *)(uintptr_t)(mmio + PCH_PP_CONTROL));
+
+ write32((hpolarity << 20) | (vpolarity << 21) | (info->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL | LVDS_DETECTED,
+ (void *)(uintptr_t)(mmio + PCH_LVDS));
+
+ write32(((hactive + right_border + hblank - 1) << 16) | (hactive - 1),
+ (void *)(uintptr_t)(mmio + HTOTAL(0)));
+ write32(((hactive + right_border + hblank - 1) << 16) | (hactive + right_border - 1),
+ (void *)(uintptr_t)(mmio + HBLANK(0)));
+ write32(((hactive + right_border + hfront_porch + hsync - 1) << 16) | (hactive + right_border + hfront_porch - 1),
+ (void *)(uintptr_t)(mmio + HSYNC(0)));
+
+ write32(((vactive + bottom_border + vblank - 1) << 16) | (vactive - 1),
+ (void *)(uintptr_t)(mmio + VTOTAL(0)));
+ write32(((vactive + bottom_border + vblank - 1) << 16) | (vactive + bottom_border - 1),
+ (void *)(uintptr_t)(mmio + VBLANK(0)));
+ write32((vactive + bottom_border + vfront_porch + vsync - 1) | (vactive + bottom_border + vfront_porch - 1),
+ (void *)(uintptr_t)(mmio + VSYNC(0)));
+
+ write32(PIPECONF_DISABLE, (void *)(uintptr_t)(mmio + PIPECONF(0)));
+
+ write32(0, (void *)(uintptr_t)(mmio + PF_WIN_POS(0)));
#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
- write32(mmio + PIPESRC(0), ((hactive - 1) << 16) | (vactive - 1));
- write32(mmio + PF_CTL(0),0);
- write32(mmio + PF_WIN_SZ(0), 0);
+ write32(((hactive - 1) << 16) | (vactive - 1),
+ (void *)(uintptr_t)(mmio + PIPESRC(0)));
+ write32(0, (void *)(uintptr_t)(mmio + PF_CTL(0)));
+ write32(0, (void *)(uintptr_t)(mmio + PF_WIN_SZ(0)));
#else
- write32(mmio + PIPESRC(0), (639 << 16) | 399);
- write32(mmio + PF_CTL(0),PF_ENABLE | PF_FILTER_MED_3x3);
- write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16));
+ write32((639 << 16) | 399, (void *)(uintptr_t)(mmio + PIPESRC(0)));
+ write32(PF_ENABLE | PF_FILTER_MED_3x3,
+ (void *)(uintptr_t)(mmio + PF_CTL(0)));
+ write32(vactive | (hactive << 16),
+ (void *)(uintptr_t)(mmio + PF_WIN_SZ(0)));
#endif
mdelay(1);
- write32(mmio + PIPE_DATA_M1(0), 0x7e000000 | data_m1);
- write32(mmio + PIPE_DATA_N1(0), data_n1);
- write32(mmio + PIPE_LINK_M1(0), link_m1);
- write32(mmio + PIPE_LINK_N1(0), link_n1);
+ write32(0x7e000000 | data_m1,
+ (void *)(uintptr_t)(mmio + PIPE_DATA_M1(0)));
+ write32(data_n1, (void *)(uintptr_t)(mmio + PIPE_DATA_N1(0)));
+ write32(link_m1, (void *)(uintptr_t)(mmio + PIPE_LINK_M1(0)));
+ write32(link_n1, (void *)(uintptr_t)(mmio + PIPE_LINK_N1(0)));
- write32(mmio + 0x000f000c, 0x00002040);
+ write32(0x00002040, (void *)(uintptr_t)(mmio + 0x000f000c));
mdelay(1);
- write32(mmio + 0x000f000c, 0x00002050);
- write32(mmio + 0x00060100, 0x00044000);
+ write32(0x00002050, (void *)(uintptr_t)(mmio + 0x000f000c));
+ write32(0x00044000, (void *)(uintptr_t)(mmio + 0x00060100));
mdelay(1);
- write32(mmio + PIPECONF(0), PIPECONF_BPP_6);
- write32(mmio + 0x000f000c, 0x00022050);
- write32(mmio + PIPECONF(0), PIPECONF_BPP_6 | PIPECONF_DITHER_EN);
- write32(mmio + PIPECONF(0), PIPECONF_ENABLE | PIPECONF_BPP_6 | PIPECONF_DITHER_EN);
+ write32(PIPECONF_BPP_6, (void *)(uintptr_t)(mmio + PIPECONF(0)));
+ write32(0x00022050, (void *)(uintptr_t)(mmio + 0x000f000c));
+ write32(PIPECONF_BPP_6 | PIPECONF_DITHER_EN,
+ (void *)(uintptr_t)(mmio + PIPECONF(0)));
+ write32(PIPECONF_ENABLE | PIPECONF_BPP_6 | PIPECONF_DITHER_EN,
+ (void *)(uintptr_t)(mmio + PIPECONF(0)));
#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
- write32(mmio + CPU_VGACNTRL, 0x20298e | VGA_DISP_DISABLE);
+ write32(0x20298e | VGA_DISP_DISABLE,
+ (void *)(uintptr_t)(mmio + CPU_VGACNTRL));
#else
- write32(mmio + CPU_VGACNTRL, 0x20298e);
+ write32(0x20298e, (void *)(uintptr_t)(mmio + CPU_VGACNTRL));
#endif
train_link(mmio);
#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
- write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888);
+ write32(DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888,
+ (void *)(uintptr_t)(mmio + DSPCNTR(0)));
mdelay(1);
#endif
- write32(mmio + TRANS_HTOTAL(0),
- ((hactive + right_border + hblank - 1) << 16)
- | (hactive - 1));
- write32(mmio + TRANS_HBLANK(0),
- ((hactive + right_border + hblank - 1) << 16)
- | (hactive + right_border - 1));
- write32(mmio + TRANS_HSYNC(0),
- ((hactive + right_border + hfront_porch + hsync - 1) << 16)
- | (hactive + right_border + hfront_porch - 1));
-
- write32(mmio + TRANS_VTOTAL(0),
- ((vactive + bottom_border + vblank - 1) << 16)
- | (vactive - 1));
- write32(mmio + TRANS_VBLANK(0),
- ((vactive + bottom_border + vblank - 1) << 16)
- | (vactive + bottom_border - 1));
- write32(mmio + TRANS_VSYNC(0),
- (vactive + bottom_border + vfront_porch + vsync - 1)
- | (vactive + bottom_border + vfront_porch - 1));
-
- write32(mmio + 0x00060100, 0xb01c4000);
- write32(mmio + 0x000f000c, 0x801a2350);
+ write32(((hactive + right_border + hblank - 1) << 16) | (hactive - 1),
+ (void *)(uintptr_t)(mmio + TRANS_HTOTAL(0)));
+ write32(((hactive + right_border + hblank - 1) << 16) | (hactive + right_border - 1),
+ (void *)(uintptr_t)(mmio + TRANS_HBLANK(0)));
+ write32(((hactive + right_border + hfront_porch + hsync - 1) << 16) | (hactive + right_border + hfront_porch - 1),
+ (void *)(uintptr_t)(mmio + TRANS_HSYNC(0)));
+
+ write32(((vactive + bottom_border + vblank - 1) << 16) | (vactive - 1),
+ (void *)(uintptr_t)(mmio + TRANS_VTOTAL(0)));
+ write32(((vactive + bottom_border + vblank - 1) << 16) | (vactive + bottom_border - 1),
+ (void *)(uintptr_t)(mmio + TRANS_VBLANK(0)));
+ write32((vactive + bottom_border + vfront_porch + vsync - 1) | (vactive + bottom_border + vfront_porch - 1),
+ (void *)(uintptr_t)(mmio + TRANS_VSYNC(0)));
+
+ write32(0xb01c4000, (void *)(uintptr_t)(mmio + 0x00060100));
+ write32(0x801a2350, (void *)(uintptr_t)(mmio + 0x000f000c));
mdelay(1);
- write32(mmio + TRANSCONF(0), TRANS_ENABLE | TRANS_6BPC
+ write32(TRANS_ENABLE | TRANS_6BPC
#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
- | TRANS_STATE_MASK
+
+ | TRANS_STATE_MASK
#endif
- );
-
- write32(mmio + PCH_LVDS,
- LVDS_PORT_ENABLE
- | (hpolarity << 20) | (vpolarity << 21)
- | (info->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL
- | LVDS_CLOCK_BOTH_POWERUP_ALL : 0)
- | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL
- | LVDS_DETECTED);
-
- write32(mmio + PCH_PP_CONTROL, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
- write32(mmio + PCH_PP_CONTROL, PANEL_UNLOCK_REGS | PANEL_POWER_RESET);
+, (void *)(uintptr_t)(mmio + TRANSCONF(0)));
+
+ write32(LVDS_PORT_ENABLE | (hpolarity << 20) | (vpolarity << 21) | (info->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL | LVDS_DETECTED,
+ (void *)(uintptr_t)(mmio + PCH_LVDS));
+
+ write32(PANEL_UNLOCK_REGS | PANEL_POWER_OFF,
+ (void *)(uintptr_t)(mmio + PCH_PP_CONTROL));
+ write32(PANEL_UNLOCK_REGS | PANEL_POWER_RESET,
+ (void *)(uintptr_t)(mmio + PCH_PP_CONTROL));
mdelay(1);
- write32(mmio + PCH_PP_CONTROL, PANEL_UNLOCK_REGS
- | PANEL_POWER_ON | PANEL_POWER_RESET);
+ write32(PANEL_UNLOCK_REGS | PANEL_POWER_ON | PANEL_POWER_RESET,
+ (void *)(uintptr_t)(mmio + PCH_PP_CONTROL));
printk (BIOS_DEBUG, "waiting for panel powerup\n");
while (1) {
u32 reg32;
- reg32 = read32(mmio + PCH_PP_STATUS);
+ reg32 = read32((void *)(uintptr_t)(mmio + PCH_PP_STATUS));
if (((reg32 >> 28) & 3) == 0)
break;
}
printk (BIOS_DEBUG, "panel powered up\n");
- write32(mmio + PCH_PP_CONTROL, PANEL_POWER_ON | PANEL_POWER_RESET);
+ write32(PANEL_POWER_ON | PANEL_POWER_RESET,
+ (void *)(uintptr_t)(mmio + PCH_PP_CONTROL));
/* Enable screen memory. */
vga_sr_write(1, vga_sr_read(1) & ~0x20);
/* Clear interrupts. */
- write32(mmio + DEIIR, 0xffffffff);
- write32(mmio + SDEIIR, 0xffffffff);
+ write32(0xffffffff, (void *)(uintptr_t)(mmio + DEIIR));
+ write32(0xffffffff, (void *)(uintptr_t)(mmio + SDEIIR));
#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
memset ((void *) lfb, 0, edid.x_resolution * edid.y_resolution * 4);
diff --git a/src/northbridge/intel/sandybridge/raminit_native.c b/src/northbridge/intel/sandybridge/raminit_native.c
index de6dac7..3189c1b 100644
--- a/src/northbridge/intel/sandybridge/raminit_native.c
+++ b/src/northbridge/intel/sandybridge/raminit_native.c
@@ -181,10 +181,10 @@ static void wait_txt_clear(void)
if (!(cp.ecx & 0x40))
return;
/* Some TXT public bit. */
- if (!(read32(0xfed30010) & 1))
+ if (!(read32((void *)(uintptr_t)(0xfed30010)) & 1))
return;
/* Wait for TXT clear. */
- while (!(read8(0xfed40000) & (1 << 7))) ;
+ while (!(read8((void *)(uintptr_t)(0xfed40000)) & (1 << 7))) ;
}
static void sfence(void)
@@ -1105,7 +1105,7 @@ static void dram_ioregs(ramctr_timing * ctrl)
static void wait_428c(int channel)
{
while (1) {
- if (read32(DEFAULT_MCHBAR | 0x428c | (channel << 10)) & 0x50)
+ if (read32((void *)(uintptr_t)(DEFAULT_MCHBAR | 0x428c | (channel << 10))) & 0x50)
return;
}
}
@@ -1122,15 +1122,19 @@ static void write_reset(ramctr_timing * ctrl)
/* choose a populated rank. */
slotrank = (ctrl->rankmap[channel] & 1) ? 0 : 2;
- write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x0f003);
- write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel, 0x80c01);
+ write32(0x0f003,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel));
+ write32(0x80c01,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel));
- write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel,
- (slotrank << 24) | 0x60000);
+ write32((slotrank << 24) | 0x60000,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel));
- write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0);
+ write32(0,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel));
- write32(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel, 0x400001);
+ write32(0x400001,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel));
wait_428c(channel);
}
@@ -1229,25 +1233,34 @@ static void write_mrreg(ramctr_timing * ctrl, int channel, int slotrank,
printram("MRd: %x <= %x\n", reg, val);
- write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x0f000);
- write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel, 0x41001);
- write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel,
- (slotrank << 24) | (reg << 20) | val | 0x60000);
- write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0);
-
- write32(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel, 0x1f000);
- write32(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel, 0x41001);
- write32(DEFAULT_MCHBAR + 0x4204 + 0x400 * channel,
- (slotrank << 24) | (reg << 20) | val | 0x60000);
- write32(DEFAULT_MCHBAR + 0x4214 + 0x400 * channel, 0);
-
- write32(DEFAULT_MCHBAR + 0x4228 + 0x400 * channel, 0x0f000);
- write32(DEFAULT_MCHBAR + 0x4238 + 0x400 * channel,
- 0x1001 | (ctrl->tMOD << 16));
- write32(DEFAULT_MCHBAR + 0x4208 + 0x400 * channel,
- (slotrank << 24) | (reg << 20) | val | 0x60000);
- write32(DEFAULT_MCHBAR + 0x4218 + 0x400 * channel, 0);
- write32(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel, 0x80001);
+ write32(0x0f000,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel));
+ write32(0x41001,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel));
+ write32((slotrank << 24) | (reg << 20) | val | 0x60000,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel));
+ write32(0,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel));
+
+ write32(0x1f000,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel));
+ write32(0x41001,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel));
+ write32((slotrank << 24) | (reg << 20) | val | 0x60000,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4204 + 0x400 * channel));
+ write32(0,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4214 + 0x400 * channel));
+
+ write32(0x0f000,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4228 + 0x400 * channel));
+ write32(0x1001 | (ctrl->tMOD << 16),
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4238 + 0x400 * channel));
+ write32((slotrank << 24) | (reg << 20) | val | 0x60000,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4208 + 0x400 * channel));
+ write32(0,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4218 + 0x400 * channel));
+ write32(0x80001,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel));
}
static u32 make_mr0(ramctr_timing * ctrl, u8 rank)
@@ -1385,15 +1398,15 @@ static void dram_mrscommands(ramctr_timing * ctrl)
printram("done\n");
}
- write32(DEFAULT_MCHBAR + 0x4e20, 0x7);
- write32(DEFAULT_MCHBAR + 0x4e30, 0xf1001);
- write32(DEFAULT_MCHBAR + 0x4e00, 0x60002);
- write32(DEFAULT_MCHBAR + 0x4e10, 0);
- write32(DEFAULT_MCHBAR + 0x4e24, 0x1f003);
- write32(DEFAULT_MCHBAR + 0x4e34, 0x1901001);
- write32(DEFAULT_MCHBAR + 0x4e04, 0x60400);
- write32(DEFAULT_MCHBAR + 0x4e14, 0x288);
- write32(DEFAULT_MCHBAR + 0x4e84, 0x40004);
+ write32(0x7, (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4e20));
+ write32(0xf1001, (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4e30));
+ write32(0x60002, (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4e00));
+ write32(0, (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4e10));
+ write32(0x1f003, (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4e24));
+ write32(0x1901001, (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4e34));
+ write32(0x60400, (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4e04));
+ write32(0x288, (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4e14));
+ write32(0x40004, (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4e84));
// Drain
FOR_ALL_CHANNELS {
@@ -1417,12 +1430,16 @@ static void dram_mrscommands(ramctr_timing * ctrl)
// Drain
wait_428c(channel);
- write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x0f003);
- write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel, 0x659001);
- write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel,
- (rank << 24) | 0x60000);
- write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0x3e0);
- write32(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel, 0x1);
+ write32(0x0f003,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel));
+ write32(0x659001,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel));
+ write32((rank << 24) | 0x60000,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel));
+ write32(0x3e0,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel));
+ write32(0x1,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel));
// Drain
wait_428c(channel);
@@ -1593,33 +1610,44 @@ static void test_timA(ramctr_timing * ctrl, int channel, int slotrank)
{
wait_428c(channel);
- write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x1f000);
- write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel,
- (0xc01 | (ctrl->tMOD << 16)));
- write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel,
- (slotrank << 24) | 0x360004);
- write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0);
-
- write32(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel, 0x1f105);
- write32(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel, 0x4040c01);
- write32(DEFAULT_MCHBAR + 0x4204 + 0x400 * channel, (slotrank << 24));
- write32(DEFAULT_MCHBAR + 0x4214 + 0x400 * channel, 0);
-
- write32(DEFAULT_MCHBAR + 0x4228 + 0x400 * channel, 0x1f105);
- write32(DEFAULT_MCHBAR + 0x4238 + 0x400 * channel,
- 0x100f | ((ctrl->CAS + 36) << 16));
- write32(DEFAULT_MCHBAR + 0x4208 + 0x400 * channel,
- (slotrank << 24) | 0x60000);
- write32(DEFAULT_MCHBAR + 0x4218 + 0x400 * channel, 0);
-
- write32(DEFAULT_MCHBAR + 0x422c + 0x400 * channel, 0x1f000);
- write32(DEFAULT_MCHBAR + 0x423c + 0x400 * channel,
- (0xc01 | (ctrl->tMOD << 16)));
- write32(DEFAULT_MCHBAR + 0x420c + 0x400 * channel,
- (slotrank << 24) | 0x360000);
- write32(DEFAULT_MCHBAR + 0x421c + 0x400 * channel, 0);
-
- write32(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel, 0xc0001);
+ write32(0x1f000,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel));
+ write32((0xc01 | (ctrl->tMOD << 16)),
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel));
+ write32((slotrank << 24) | 0x360004,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel));
+ write32(0,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel));
+
+ write32(0x1f105,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel));
+ write32(0x4040c01,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel));
+ write32((slotrank << 24),
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4204 + 0x400 * channel));
+ write32(0,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4214 + 0x400 * channel));
+
+ write32(0x1f105,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4228 + 0x400 * channel));
+ write32(0x100f | ((ctrl->CAS + 36) << 16),
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4238 + 0x400 * channel));
+ write32((slotrank << 24) | 0x60000,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4208 + 0x400 * channel));
+ write32(0,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4218 + 0x400 * channel));
+
+ write32(0x1f000,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x422c + 0x400 * channel));
+ write32((0xc01 | (ctrl->tMOD << 16)),
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x423c + 0x400 * channel));
+ write32((slotrank << 24) | 0x360000,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x420c + 0x400 * channel));
+ write32(0,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x421c + 0x400 * channel));
+
+ write32(0xc0001,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel));
wait_428c(channel);
}
@@ -1628,9 +1656,7 @@ static int does_lane_work(ramctr_timing * ctrl, int channel, int slotrank,
int lane)
{
u32 timA = ctrl->timings[channel][slotrank].lanes[lane].timA;
- return ((read32
- (DEFAULT_MCHBAR + lane_registers[lane] + channel * 0x100 + 4 +
- ((timA / 32) & 1) * 4)
+ return ((read32((void *)(uintptr_t)(DEFAULT_MCHBAR + lane_registers[lane] + channel * 0x100 + 4 + ((timA / 32) & 1) * 4))
>> (timA % 32)) & 1);
}
@@ -1854,15 +1880,19 @@ static void read_training(ramctr_timing * ctrl)
struct timA_minmax mnmx;
wait_428c(channel);
- write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x1f002);
- write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel,
- 0xc01 | (ctrl->tRP << 16));
- write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel,
- (slotrank << 24) | 0x60400);
- write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0);
- write32(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel, 1);
-
- write32(DEFAULT_MCHBAR + 0x3400, (slotrank << 2) | 0x8001);
+ write32(0x1f002,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel));
+ write32(0xc01 | (ctrl->tRP << 16),
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel));
+ write32((slotrank << 24) | 0x60400,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel));
+ write32(0,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel));
+ write32(1,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel));
+
+ write32((slotrank << 2) | 0x8001,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x3400));
ctrl->timings[channel][slotrank].val_4028 = 4;
ctrl->timings[channel][slotrank].val_4024 = 55;
@@ -1927,13 +1957,15 @@ static void read_training(ramctr_timing * ctrl)
lane,
ctrl->timings[channel][slotrank].lanes[lane].timA);
- write32(DEFAULT_MCHBAR + 0x3400, 0);
+ write32(0, (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x3400));
- r32 = read32(DEFAULT_MCHBAR + 0x5030);
- write32(DEFAULT_MCHBAR + 0x5030, r32 | 0x20);
+ r32 = read32((void *)(uintptr_t)(DEFAULT_MCHBAR + 0x5030));
+ write32(r32 | 0x20,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x5030));
udelay(1);
- write32(DEFAULT_MCHBAR + 0x5030, r32 & ~0x20);
+ write32(r32 & ~0x20,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x5030));
udelay(1);
}
@@ -1942,8 +1974,8 @@ static void read_training(ramctr_timing * ctrl)
program_timings(ctrl, channel);
}
FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES {
- write32(DEFAULT_MCHBAR + 0x4080 + 0x400 * channel
- + 4 * lane, 0);
+ write32(0,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4080 + 0x400 * channel + 4 * lane));
}
}
@@ -1952,74 +1984,95 @@ static void test_timC(ramctr_timing * ctrl, int channel, int slotrank)
int lane;
FOR_ALL_LANES {
- write32(DEFAULT_MCHBAR + 0x4340 + 0x400 * channel + 4 * lane, 0);
- read32(DEFAULT_MCHBAR + 0x4140 + 0x400 * channel + 4 * lane);
+ write32(0,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4340 + 0x400 * channel + 4 * lane));
+ read32((void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4140 + 0x400 * channel + 4 * lane));
}
wait_428c(channel);
- write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x1f006);
- write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel,
- (max((ctrl->tFAW >> 2) + 1, ctrl->tRRD) << 10)
- | 4 | (ctrl->tRCD << 16));
-
- write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel,
- (slotrank << 24) | (6 << 16));
-
- write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0x244);
-
- write32(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel, 0x1f207);
- write32(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel, 0x8041001);
- write32(DEFAULT_MCHBAR + 0x4204 + 0x400 * channel,
- (slotrank << 24) | 8);
- write32(DEFAULT_MCHBAR + 0x4214 + 0x400 * channel, 0x3e0);
-
- write32(DEFAULT_MCHBAR + 0x4228 + 0x400 * channel, 0x1f201);
- write32(DEFAULT_MCHBAR + 0x4238 + 0x400 * channel, 0x80411f4);
- write32(DEFAULT_MCHBAR + 0x4208 + 0x400 * channel, (slotrank << 24));
- write32(DEFAULT_MCHBAR + 0x4218 + 0x400 * channel, 0x242);
-
- write32(DEFAULT_MCHBAR + 0x422c + 0x400 * channel, 0x1f207);
- write32(DEFAULT_MCHBAR + 0x423c + 0x400 * channel,
- 0x8000c01 | ((ctrl->CWL + ctrl->tWTR + 5) << 16));
- write32(DEFAULT_MCHBAR + 0x420c + 0x400 * channel,
- (slotrank << 24) | 8);
- write32(DEFAULT_MCHBAR + 0x421c + 0x400 * channel, 0x3e0);
-
- write32(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel, 0xc0001);
+ write32(0x1f006,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel));
+ write32((max((ctrl->tFAW >> 2) + 1, ctrl->tRRD) << 10) | 4 | (ctrl->tRCD << 16),
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel));
+
+ write32((slotrank << 24) | (6 << 16),
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel));
+
+ write32(0x244,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel));
+
+ write32(0x1f207,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel));
+ write32(0x8041001,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel));
+ write32((slotrank << 24) | 8,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4204 + 0x400 * channel));
+ write32(0x3e0,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4214 + 0x400 * channel));
+
+ write32(0x1f201,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4228 + 0x400 * channel));
+ write32(0x80411f4,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4238 + 0x400 * channel));
+ write32((slotrank << 24),
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4208 + 0x400 * channel));
+ write32(0x242,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4218 + 0x400 * channel));
+
+ write32(0x1f207,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x422c + 0x400 * channel));
+ write32(0x8000c01 | ((ctrl->CWL + ctrl->tWTR + 5) << 16),
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x423c + 0x400 * channel));
+ write32((slotrank << 24) | 8,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x420c + 0x400 * channel));
+ write32(0x3e0,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x421c + 0x400 * channel));
+
+ write32(0xc0001,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel));
wait_428c(channel);
- write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x1f002);
- write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel,
- 0xc01 | (ctrl->tRP << 16));
- write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel,
- (slotrank << 24) | 0x60400);
- write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0x240);
-
- write32(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel, 0x1f006);
- write32(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel,
- (max(ctrl->tRRD, (ctrl->tFAW >> 2) + 1) << 10)
- | 8 | (ctrl->CAS << 16));
-
- write32(DEFAULT_MCHBAR + 0x4204 + 0x400 * channel,
- (slotrank << 24) | 0x60000);
-
- write32(DEFAULT_MCHBAR + 0x4214 + 0x400 * channel, 0x244);
-
- write32(DEFAULT_MCHBAR + 0x4228 + 0x400 * channel, 0x1f105);
- write32(DEFAULT_MCHBAR + 0x4238 + 0x400 * channel,
- 0x40011f4 | (max(ctrl->tRTP, 8) << 16));
- write32(DEFAULT_MCHBAR + 0x4208 + 0x400 * channel, (slotrank << 24));
- write32(DEFAULT_MCHBAR + 0x4218 + 0x400 * channel, 0x242);
-
- write32(DEFAULT_MCHBAR + 0x422c + 0x400 * channel, 0x1f002);
- write32(DEFAULT_MCHBAR + 0x423c + 0x400 * channel,
- 0xc01 | (ctrl->tRP << 16));
- write32(DEFAULT_MCHBAR + 0x420c + 0x400 * channel,
- (slotrank << 24) | 0x60400);
- write32(DEFAULT_MCHBAR + 0x421c + 0x400 * channel, 0x240);
- write32(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel, 0xc0001);
+ write32(0x1f002,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel));
+ write32(0xc01 | (ctrl->tRP << 16),
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel));
+ write32((slotrank << 24) | 0x60400,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel));
+ write32(0x240,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel));
+
+ write32(0x1f006,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel));
+ write32((max(ctrl->tRRD, (ctrl->tFAW >> 2) + 1) << 10) | 8 | (ctrl->CAS << 16),
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel));
+
+ write32((slotrank << 24) | 0x60000,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4204 + 0x400 * channel));
+
+ write32(0x244,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4214 + 0x400 * channel));
+
+ write32(0x1f105,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4228 + 0x400 * channel));
+ write32(0x40011f4 | (max(ctrl->tRTP, 8) << 16),
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4238 + 0x400 * channel));
+ write32((slotrank << 24),
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4208 + 0x400 * channel));
+ write32(0x242,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4218 + 0x400 * channel));
+
+ write32(0x1f002,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x422c + 0x400 * channel));
+ write32(0xc01 | (ctrl->tRP << 16),
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x423c + 0x400 * channel));
+ write32((slotrank << 24) | 0x60400,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x420c + 0x400 * channel));
+ write32(0x240,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x421c + 0x400 * channel));
+ write32(0xc0001,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel));
wait_428c(channel);
}
@@ -2031,13 +2084,16 @@ static void discover_timC(ramctr_timing * ctrl, int channel, int slotrank)
wait_428c(channel);
- write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x1f002);
- write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel,
- 0xc01 | (ctrl->tRP << 16));
- write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel,
- (slotrank << 24) | 0x60400);
- write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0x240);
- write32(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel, 1);
+ write32(0x1f002,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel));
+ write32(0xc01 | (ctrl->tRP << 16),
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel));
+ write32((slotrank << 24) | 0x60400,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel));
+ write32(0x240,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel));
+ write32(1,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel));
for (timC = 0; timC <= MAX_TIMC; timC++) {
FOR_ALL_LANES ctrl->timings[channel][slotrank].lanes[lane].
@@ -2048,8 +2104,7 @@ static void discover_timC(ramctr_timing * ctrl, int channel, int slotrank)
FOR_ALL_LANES {
statistics[lane][timC] =
- read32(DEFAULT_MCHBAR + 0x4340 + 4 * lane +
- 0x400 * channel);
+ read32((void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4340 + 4 * lane + 0x400 * channel));
printram("Cstat: %d, %d, %d, %x, %x\n",
channel, slotrank, lane, timC,
statistics[lane][timC]);
@@ -2081,7 +2136,8 @@ static void fill_pattern0(ramctr_timing * ctrl, int channel, u32 a, u32 b)
get_precedening_channels(ctrl, channel) * 0x40;
printram("channel_offset=%x\n", channel_offset);
for (j = 0; j < 16; j++)
- write32(0x04000000 + channel_offset + 4 * j, j & 2 ? b : a);
+ write32(j & 2 ? b : a,
+ (void *)(uintptr_t)(0x04000000 + channel_offset + 4 * j));
sfence();
}
@@ -2100,9 +2156,11 @@ static void fill_pattern1(ramctr_timing * ctrl, int channel)
get_precedening_channels(ctrl, channel) * 0x40;
unsigned channel_step = 0x40 * num_of_channels(ctrl);
for (j = 0; j < 16; j++)
- write32(0x04000000 + channel_offset + j * 4, 0xffffffff);
+ write32(0xffffffff,
+ (void *)(uintptr_t)(0x04000000 + channel_offset + j * 4));
for (j = 0; j < 16; j++)
- write32(0x04000000 + channel_offset + channel_step + j * 4, 0);
+ write32(0,
+ (void *)(uintptr_t)(0x04000000 + channel_offset + channel_step + j * 4));
sfence();
}
@@ -2121,39 +2179,43 @@ static void precharge(ramctr_timing * ctrl)
FOR_ALL_POPULATED_RANKS {
wait_428c(channel);
- write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel,
- 0x1f000);
- write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel,
- 0xc01 | (ctrl->tMOD << 16));
- write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel,
- (slotrank << 24) | 0x360004);
- write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0);
-
- write32(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel,
- 0x1f105);
- write32(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel,
- 0x4041003);
- write32(DEFAULT_MCHBAR + 0x4204 + 0x400 * channel,
- (slotrank << 24) | 0);
- write32(DEFAULT_MCHBAR + 0x4214 + 0x400 * channel, 0);
-
- write32(DEFAULT_MCHBAR + 0x4228 + 0x400 * channel,
- 0x1f105);
- write32(DEFAULT_MCHBAR + 0x4238 + 0x400 * channel,
- 0x1001 | ((ctrl->CAS + 8) << 16));
- write32(DEFAULT_MCHBAR + 0x4208 + 0x400 * channel,
- (slotrank << 24) | 0x60000);
- write32(DEFAULT_MCHBAR + 0x4218 + 0x400 * channel, 0);
-
- write32(DEFAULT_MCHBAR + 0x422c + 0x400 * channel,
- 0x1f000);
- write32(DEFAULT_MCHBAR + 0x423c + 0x400 * channel,
- 0xc01 | (ctrl->tMOD << 16));
- write32(DEFAULT_MCHBAR + 0x420c + 0x400 * channel,
- (slotrank << 24) | 0x360000);
- write32(DEFAULT_MCHBAR + 0x421c + 0x400 * channel, 0);
- write32(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel,
- 0xc0001);
+ write32(0x1f000,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel));
+ write32(0xc01 | (ctrl->tMOD << 16),
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel));
+ write32((slotrank << 24) | 0x360004,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel));
+ write32(0,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel));
+
+ write32(0x1f105,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel));
+ write32(0x4041003,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel));
+ write32((slotrank << 24) | 0,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4204 + 0x400 * channel));
+ write32(0,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4214 + 0x400 * channel));
+
+ write32(0x1f105,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4228 + 0x400 * channel));
+ write32(0x1001 | ((ctrl->CAS + 8) << 16),
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4238 + 0x400 * channel));
+ write32((slotrank << 24) | 0x60000,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4208 + 0x400 * channel));
+ write32(0,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4218 + 0x400 * channel));
+
+ write32(0x1f000,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x422c + 0x400 * channel));
+ write32(0xc01 | (ctrl->tMOD << 16),
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x423c + 0x400 * channel));
+ write32((slotrank << 24) | 0x360000,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x420c + 0x400 * channel));
+ write32(0,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x421c + 0x400 * channel));
+ write32(0xc0001,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel));
wait_428c(channel);
}
@@ -2170,41 +2232,45 @@ static void precharge(ramctr_timing * ctrl)
FOR_ALL_POPULATED_RANKS {
wait_428c(channel);
- write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel,
- 0x1f000);
- write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel,
- 0xc01 | (ctrl->tMOD << 16));
- write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel,
- (slotrank << 24) | 0x360004);
- write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0);
-
- write32(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel,
- 0x1f105);
- write32(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel,
- 0x4041003);
- write32(DEFAULT_MCHBAR + 0x4204 + 0x400 * channel,
- (slotrank << 24) | 0);
- write32(DEFAULT_MCHBAR + 0x4214 + 0x400 * channel, 0);
-
- write32(DEFAULT_MCHBAR + 0x4228 + 0x400 * channel,
- 0x1f105);
- write32(DEFAULT_MCHBAR + 0x4238 + 0x400 * channel,
- 0x1001 | ((ctrl->CAS + 8) << 16));
- write32(DEFAULT_MCHBAR + 0x4208 + 0x400 * channel,
- (slotrank << 24) | 0x60000);
- write32(DEFAULT_MCHBAR + 0x4218 + 0x400 * channel, 0);
-
- write32(DEFAULT_MCHBAR + 0x422c + 0x400 * channel,
- 0x1f000);
- write32(DEFAULT_MCHBAR + 0x423c + 0x400 * channel,
- 0xc01 | (ctrl->tMOD << 16));
-
- write32(DEFAULT_MCHBAR + 0x420c + 0x400 * channel,
- (slotrank << 24) | 0x360000);
- write32(DEFAULT_MCHBAR + 0x421c + 0x400 * channel, 0);
-
- write32(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel,
- 0xc0001);
+ write32(0x1f000,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel));
+ write32(0xc01 | (ctrl->tMOD << 16),
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel));
+ write32((slotrank << 24) | 0x360004,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel));
+ write32(0,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel));
+
+ write32(0x1f105,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel));
+ write32(0x4041003,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel));
+ write32((slotrank << 24) | 0,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4204 + 0x400 * channel));
+ write32(0,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4214 + 0x400 * channel));
+
+ write32(0x1f105,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4228 + 0x400 * channel));
+ write32(0x1001 | ((ctrl->CAS + 8) << 16),
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4238 + 0x400 * channel));
+ write32((slotrank << 24) | 0x60000,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4208 + 0x400 * channel));
+ write32(0,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4218 + 0x400 * channel));
+
+ write32(0x1f000,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x422c + 0x400 * channel));
+ write32(0xc01 | (ctrl->tMOD << 16),
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x423c + 0x400 * channel));
+
+ write32((slotrank << 24) | 0x360000,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x420c + 0x400 * channel));
+ write32(0,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x421c + 0x400 * channel));
+
+ write32(0xc0001,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel));
wait_428c(channel);
}
}
@@ -2216,21 +2282,26 @@ static void test_timB(ramctr_timing * ctrl, int channel, int slotrank)
0x80 | make_mr1(ctrl, slotrank));
wait_428c(channel);
- write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x1f207);
- write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel,
- 0x8000c01 | ((ctrl->CWL + ctrl->tWLO) << 16));
- write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel,
- 8 | (slotrank << 24));
- write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0);
-
- write32(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel, 0x1f107);
- write32(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel,
- 0x4000c01 | ((ctrl->CAS + 38) << 16));
- write32(DEFAULT_MCHBAR + 0x4204 + 0x400 * channel,
- (slotrank << 24) | 4);
- write32(DEFAULT_MCHBAR + 0x4214 + 0x400 * channel, 0);
-
- write32(DEFAULT_MCHBAR + 0x400 * channel + 0x4284, 0x40001);
+ write32(0x1f207,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel));
+ write32(0x8000c01 | ((ctrl->CWL + ctrl->tWLO) << 16),
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel));
+ write32(8 | (slotrank << 24),
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel));
+ write32(0,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel));
+
+ write32(0x1f107,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel));
+ write32(0x4000c01 | ((ctrl->CAS + 38) << 16),
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel));
+ write32((slotrank << 24) | 4,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4204 + 0x400 * channel));
+ write32(0,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4214 + 0x400 * channel));
+
+ write32(0x40001,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x400 * channel + 0x4284));
wait_428c(channel);
write_mrreg(ctrl, channel, slotrank, 1,
@@ -2243,7 +2314,8 @@ static void discover_timB(ramctr_timing * ctrl, int channel, int slotrank)
int statistics[NUM_LANES][128];
int lane;
- write32(DEFAULT_MCHBAR + 0x3400, 0x108052 | (slotrank << 2));
+ write32(0x108052 | (slotrank << 2),
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x3400));
for (timB = 0; timB < 128; timB++) {
FOR_ALL_LANES {
@@ -2255,9 +2327,7 @@ static void discover_timB(ramctr_timing * ctrl, int channel, int slotrank)
FOR_ALL_LANES {
statistics[lane][timB] =
- !((read32
- (DEFAULT_MCHBAR + lane_registers[lane] +
- channel * 0x100 + 4 + ((timB / 32) & 1) * 4)
+ !((read32((void *)(uintptr_t)(DEFAULT_MCHBAR + lane_registers[lane] + channel * 0x100 + 4 + ((timB / 32) & 1) * 4))
>> (timB % 32)) & 1);
printram("Bstat: %d, %d, %d, %x, %x\n",
channel, slotrank, lane, timB,
@@ -2295,80 +2365,95 @@ static int get_timB_high_adjust(u64 val)
static void adjust_high_timB(ramctr_timing * ctrl)
{
int channel, slotrank, lane;
- write32(DEFAULT_MCHBAR + 0x3400, 0x200);
+ write32(0x200, (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x3400));
FOR_ALL_POPULATED_CHANNELS {
fill_pattern1(ctrl, channel);
- write32(DEFAULT_MCHBAR | 0x4288 | (channel << 10), 1);
+ write32(1,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR | 0x4288 | (channel << 10)));
}
FOR_ALL_POPULATED_CHANNELS FOR_ALL_POPULATED_RANKS {
- write32(DEFAULT_MCHBAR + 0x4288 + 0x400 * channel, 0x10001);
+ write32(0x10001,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4288 + 0x400 * channel));
wait_428c(channel);
- write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x1f006);
- write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel,
- 0xc01 | (ctrl->tRCD << 16));
- write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel,
- (slotrank << 24) | 0x60000);
- write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0);
-
- write32(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel, 0x1f207);
- write32(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel, 0x8040c01);
- write32(DEFAULT_MCHBAR + 0x4204 + 0x400 * channel,
- (slotrank << 24) | 0x8);
- write32(DEFAULT_MCHBAR + 0x4214 + 0x400 * channel, 0x3e0);
-
- write32(DEFAULT_MCHBAR + 0x4228 + 0x400 * channel, 0x1f201);
- write32(DEFAULT_MCHBAR + 0x4238 + 0x400 * channel, 0x8041003);
- write32(DEFAULT_MCHBAR + 0x4208 + 0x400 * channel,
- (slotrank << 24));
- write32(DEFAULT_MCHBAR + 0x4218 + 0x400 * channel, 0x3e2);
-
- write32(DEFAULT_MCHBAR + 0x422c + 0x400 * channel, 0x1f207);
- write32(DEFAULT_MCHBAR + 0x423c + 0x400 * channel,
- 0x8000c01 | ((ctrl->CWL + ctrl->tWTR + 5) << 16));
- write32(DEFAULT_MCHBAR + 0x420c + 0x400 * channel,
- (slotrank << 24) | 0x8);
- write32(DEFAULT_MCHBAR + 0x421c + 0x400 * channel, 0x3e0);
-
- write32(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel, 0xc0001);
+ write32(0x1f006,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel));
+ write32(0xc01 | (ctrl->tRCD << 16),
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel));
+ write32((slotrank << 24) | 0x60000,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel));
+ write32(0,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel));
+
+ write32(0x1f207,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel));
+ write32(0x8040c01,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel));
+ write32((slotrank << 24) | 0x8,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4204 + 0x400 * channel));
+ write32(0x3e0,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4214 + 0x400 * channel));
+
+ write32(0x1f201,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4228 + 0x400 * channel));
+ write32(0x8041003,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4238 + 0x400 * channel));
+ write32((slotrank << 24),
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4208 + 0x400 * channel));
+ write32(0x3e2,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4218 + 0x400 * channel));
+
+ write32(0x1f207,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x422c + 0x400 * channel));
+ write32(0x8000c01 | ((ctrl->CWL + ctrl->tWTR + 5) << 16),
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x423c + 0x400 * channel));
+ write32((slotrank << 24) | 0x8,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x420c + 0x400 * channel));
+ write32(0x3e0,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x421c + 0x400 * channel));
+
+ write32(0xc0001,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel));
wait_428c(channel);
- write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x1f002);
- write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel,
- 0xc01 | ((ctrl->tRP) << 16));
- write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel,
- (slotrank << 24) | 0x60400);
- write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0x240);
-
- write32(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel, 0x1f006);
- write32(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel,
- 0xc01 | ((ctrl->tRCD) << 16));
- write32(DEFAULT_MCHBAR + 0x4204 + 0x400 * channel,
- (slotrank << 24) | 0x60000);
- write32(DEFAULT_MCHBAR + 0x4214 + 0x400 * channel, 0);
-
- write32(DEFAULT_MCHBAR + 0x4228 + 0x400 * channel, 0x3f105);
- write32(DEFAULT_MCHBAR + 0x4238 + 0x400 * channel,
- 0x4000c01 |
- ((ctrl->tRP +
- ctrl->timings[channel][slotrank].val_4024 +
- ctrl->timings[channel][slotrank].val_4028) << 16));
- write32(DEFAULT_MCHBAR + 0x4208 + 0x400 * channel,
- (slotrank << 24) | 0x60008);
- write32(DEFAULT_MCHBAR + 0x4218 + 0x400 * channel, 0);
-
- write32(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel, 0x80001);
+ write32(0x1f002,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel));
+ write32(0xc01 | ((ctrl->tRP) << 16),
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel));
+ write32((slotrank << 24) | 0x60400,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel));
+ write32(0x240,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel));
+
+ write32(0x1f006,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel));
+ write32(0xc01 | ((ctrl->tRCD) << 16),
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel));
+ write32((slotrank << 24) | 0x60000,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4204 + 0x400 * channel));
+ write32(0,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4214 + 0x400 * channel));
+
+ write32(0x3f105,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4228 + 0x400 * channel));
+ write32(0x4000c01 | ((ctrl->tRP + ctrl->timings[channel][slotrank].val_4024 + ctrl->timings[channel][slotrank].val_4028) << 16),
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4238 + 0x400 * channel));
+ write32((slotrank << 24) | 0x60008,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4208 + 0x400 * channel));
+ write32(0,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4218 + 0x400 * channel));
+
+ write32(0x80001,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel));
wait_428c(channel);
FOR_ALL_LANES {
u64 res =
- read32(DEFAULT_MCHBAR + lane_registers[lane] +
- 0x100 * channel + 4);
+ read32((void *)(uintptr_t)(DEFAULT_MCHBAR + lane_registers[lane] + 0x100 * channel + 4));
res |=
- ((u64) read32(DEFAULT_MCHBAR + lane_registers[lane] +
- 0x100 * channel + 8)) << 32;
+ ((u64) read32((void *)(uintptr_t)(DEFAULT_MCHBAR + lane_registers[lane] + 0x100 * channel + 8))) << 32;
ctrl->timings[channel][slotrank].lanes[lane].timB +=
get_timB_high_adjust(res) * 64;
@@ -2379,7 +2464,7 @@ static void adjust_high_timB(ramctr_timing * ctrl)
timB);
}
}
- write32(DEFAULT_MCHBAR + 0x3400, 0);
+ write32(0, (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x3400));
}
static void write_op(ramctr_timing * ctrl, int channel)
@@ -2391,15 +2476,19 @@ static void write_op(ramctr_timing * ctrl, int channel)
/* choose an existing rank. */
slotrank = !(ctrl->rankmap[channel] & 1) ? 2 : 0;
- write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x0f003);
- write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel, 0x41001);
+ write32(0x0f003,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel));
+ write32(0x41001,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel));
- write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel,
- (slotrank << 24) | 0x60000);
+ write32((slotrank << 24) | 0x60000,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel));
- write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0x3e0);
+ write32(0x3e0,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel));
- write32(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel, 1);
+ write32(1,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel));
wait_428c(channel);
}
@@ -2409,17 +2498,16 @@ static void write_training(ramctr_timing * ctrl)
u32 r32;
FOR_ALL_POPULATED_CHANNELS
- write32(DEFAULT_MCHBAR + 0x4008 + 0x400 * channel,
- read32(DEFAULT_MCHBAR + 0x4008 +
- 0x400 * channel) | 0x8000000);
+ write32(read32((void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4008 + 0x400 * channel)) | 0x8000000,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4008 + 0x400 * channel));
FOR_ALL_POPULATED_CHANNELS {
write_op(ctrl, channel);
- write32(DEFAULT_MCHBAR + 0x4020 + 0x400 * channel,
- read32(DEFAULT_MCHBAR + 0x4020 +
- 0x400 * channel) | 0x200000);
+ write32(read32((void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4020 + 0x400 * channel)) | 0x200000,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4020 + 0x400 * channel));
}
- write32(DEFAULT_MCHBAR + 0x5030, read32(DEFAULT_MCHBAR + 0x5030) & ~8);
+ write32(read32((void *)(uintptr_t)(DEFAULT_MCHBAR + 0x5030)) & ~8,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x5030));
FOR_ALL_POPULATED_CHANNELS {
write_op(ctrl, channel);
}
@@ -2429,13 +2517,13 @@ static void write_training(ramctr_timing * ctrl)
write_mrreg(ctrl, channel, slotrank, 1,
make_mr1(ctrl, slotrank) | 0x1080);
- write32(DEFAULT_MCHBAR + 0x3400, 0x108052);
+ write32(0x108052, (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x3400));
- r32 = read32(DEFAULT_MCHBAR + 0x5030);
- write32(DEFAULT_MCHBAR + 0x5030, r32 | 0x20);
+ r32 = read32((void *)(uintptr_t)(DEFAULT_MCHBAR + 0x5030));
+ write32(r32 | 0x20, (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x5030));
udelay(1);
- write32(DEFAULT_MCHBAR + 0x5030, r32 & ~0x20);
+ write32(r32 & ~0x20, (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x5030));
udelay(1);
@@ -2446,34 +2534,39 @@ static void write_training(ramctr_timing * ctrl)
write_mrreg(ctrl, channel,
slotrank, 1, make_mr1(ctrl, slotrank));
- write32(DEFAULT_MCHBAR + 0x3400, 0);
+ write32(0, (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x3400));
FOR_ALL_POPULATED_CHANNELS
wait_428c(channel);
- write32(DEFAULT_MCHBAR + 0x5030, read32(DEFAULT_MCHBAR + 0x5030) | 8);
+ write32(read32((void *)(uintptr_t)(DEFAULT_MCHBAR + 0x5030)) | 8,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x5030));
FOR_ALL_POPULATED_CHANNELS {
- write32(DEFAULT_MCHBAR + 0x4020 + 0x400 * channel,
- ~0x00200000 & read32(DEFAULT_MCHBAR + 0x4020 +
- 0x400 * channel));
- read32(DEFAULT_MCHBAR + 0x428c + 0x400 * channel);
+ write32(~0x00200000 & read32((void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4020 + 0x400 * channel)),
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4020 + 0x400 * channel));
+ read32((void *)(uintptr_t)(DEFAULT_MCHBAR + 0x428c + 0x400 * channel));
wait_428c(channel);
- write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x0f003);
- write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel, 0x659001);
- write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel, 0x60000);
- write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0x3e0);
-
- write32(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel, 1);
+ write32(0x0f003,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel));
+ write32(0x659001,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel));
+ write32(0x60000,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel));
+ write32(0x3e0,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel));
+
+ write32(1,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel));
wait_428c(channel);
}
- r32 = read32(DEFAULT_MCHBAR + 0x5030);
- write32(DEFAULT_MCHBAR + 0x5030, r32 | 0x20);
+ r32 = read32((void *)(uintptr_t)(DEFAULT_MCHBAR + 0x5030));
+ write32(r32 | 0x20, (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x5030));
udelay(1);
- write32(DEFAULT_MCHBAR + 0x5030, r32 & ~0x20);
+ write32(r32 & ~0x20, (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x5030));
udelay(1);
@@ -2482,14 +2575,15 @@ static void write_training(ramctr_timing * ctrl)
printram("CPF\n");
FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES {
- read32(DEFAULT_MCHBAR + 0x4080 + 0x400 * channel + 4 * lane);
- write32(DEFAULT_MCHBAR + 0x4080 + 0x400 * channel + 4 * lane,
- 0);
+ read32((void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4080 + 0x400 * channel + 4 * lane));
+ write32(0,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4080 + 0x400 * channel + 4 * lane));
}
FOR_ALL_POPULATED_CHANNELS {
fill_pattern0(ctrl, channel, 0xaaaaaaaa, 0x55555555);
- write32(DEFAULT_MCHBAR | 0x4288 | (channel << 10), 0);
+ write32(0,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR | 0x4288 | (channel << 10)));
}
FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS
@@ -2504,9 +2598,9 @@ static void write_training(ramctr_timing * ctrl)
program_timings(ctrl, channel);
FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES {
- read32(DEFAULT_MCHBAR + 0x4080 + 0x400 * channel + 4 * lane);
- write32(DEFAULT_MCHBAR + 0x4080 + 0x400 * channel + 4 * lane,
- 0);
+ read32((void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4080 + 0x400 * channel + 4 * lane));
+ write32(0,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4080 + 0x400 * channel + 4 * lane));
}
}
@@ -2525,51 +2619,63 @@ static int test_320c(ramctr_timing * ctrl, int channel, int slotrank)
}
program_timings(ctrl, channel);
FOR_ALL_LANES {
- write32(DEFAULT_MCHBAR + 4 * lane + 0x4f40, 0);
+ write32(0,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 4 * lane + 0x4f40));
}
- write32(DEFAULT_MCHBAR + 0x4288 + 0x400 * channel, 0x1f);
+ write32(0x1f,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4288 + 0x400 * channel));
wait_428c(channel);
- write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x1f006);
- write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel,
- ((max(ctrl->tRRD, (ctrl->tFAW >> 2) + 1)) << 10)
- | 8 | (ctrl->tRCD << 16));
-
- write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel,
- (slotrank << 24) | ctr | 0x60000);
-
- write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0x244);
-
- write32(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel, 0x1f201);
- write32(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel,
- 0x8001020 | ((ctrl->CWL + ctrl->tWTR + 8) << 16));
- write32(DEFAULT_MCHBAR + 0x4204 + 0x400 * channel,
- (slotrank << 24));
- write32(DEFAULT_MCHBAR + 0x4244 + 0x400 * channel, 0x389abcd);
- write32(DEFAULT_MCHBAR + 0x4214 + 0x400 * channel, 0x20e42);
-
- write32(DEFAULT_MCHBAR + 0x4228 + 0x400 * channel, 0x1f105);
- write32(DEFAULT_MCHBAR + 0x4238 + 0x400 * channel,
- 0x4001020 | (max(ctrl->tRTP, 8) << 16));
- write32(DEFAULT_MCHBAR + 0x4208 + 0x400 * channel,
- (slotrank << 24));
- write32(DEFAULT_MCHBAR + 0x4248 + 0x400 * channel, 0x389abcd);
- write32(DEFAULT_MCHBAR + 0x4218 + 0x400 * channel, 0x20e42);
-
- write32(DEFAULT_MCHBAR + 0x422c + 0x400 * channel, 0x1f002);
- write32(DEFAULT_MCHBAR + 0x423c + 0x400 * channel, 0xf1001);
- write32(DEFAULT_MCHBAR + 0x420c + 0x400 * channel,
- (slotrank << 24) | 0x60400);
- write32(DEFAULT_MCHBAR + 0x421c + 0x400 * channel, 0x240);
-
- write32(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel, 0xc0001);
+ write32(0x1f006,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel));
+ write32(((max(ctrl->tRRD, (ctrl->tFAW >> 2) + 1)) << 10) | 8 | (ctrl->tRCD << 16),
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel));
+
+ write32((slotrank << 24) | ctr | 0x60000,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel));
+
+ write32(0x244,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel));
+
+ write32(0x1f201,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel));
+ write32(0x8001020 | ((ctrl->CWL + ctrl->tWTR + 8) << 16),
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel));
+ write32((slotrank << 24),
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4204 + 0x400 * channel));
+ write32(0x389abcd,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4244 + 0x400 * channel));
+ write32(0x20e42,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4214 + 0x400 * channel));
+
+ write32(0x1f105,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4228 + 0x400 * channel));
+ write32(0x4001020 | (max(ctrl->tRTP, 8) << 16),
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4238 + 0x400 * channel));
+ write32((slotrank << 24),
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4208 + 0x400 * channel));
+ write32(0x389abcd,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4248 + 0x400 * channel));
+ write32(0x20e42,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4218 + 0x400 * channel));
+
+ write32(0x1f002,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x422c + 0x400 * channel));
+ write32(0xf1001,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x423c + 0x400 * channel));
+ write32((slotrank << 24) | 0x60400,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x420c + 0x400 * channel));
+ write32(0x240,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x421c + 0x400 * channel));
+
+ write32(0xc0001,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel));
wait_428c(channel);
FOR_ALL_LANES {
u32 r32 =
- read32(DEFAULT_MCHBAR + 0x4340 + 4 * lane +
- 0x400 * channel);
+ read32((void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4340 + 4 * lane + 0x400 * channel));
if (r32 == 0)
lanes_ok |= 1 << lane;
@@ -2602,16 +2708,16 @@ static void fill_pattern5(ramctr_timing * ctrl, int channel, int patno)
u32 val = use_base[patno - 1][i] & (1 << (j / 2)) ? base : 0;
if (invert[patno - 1][i] & (1 << (j / 2)))
val = ~val;
- write32(0x04000000 + channel_offset + i * channel_step +
- j * 4, val);
+ write32(val,
+ (void *)(uintptr_t)(0x04000000 + channel_offset + i * channel_step + j * 4));
}
}
} else {
for (i = 0; i < sizeof(pattern) / sizeof(pattern[0]); i++) {
for (j = 0; j < 16; j++)
- write32(0x04000000 + channel_offset + i * channel_step +
- j * 4, pattern[i][j]);
+ write32(pattern[i][j],
+ (void *)(uintptr_t)(0x04000000 + channel_offset + i * channel_step + j * 4));
}
sfence();
}
@@ -2628,36 +2734,44 @@ static void reprogram_320c(ramctr_timing * ctrl)
/* choose an existing rank. */
slotrank = !(ctrl->rankmap[channel] & 1) ? 2 : 0;
- write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x0f003);
- write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel, 0x41001);
+ write32(0x0f003,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel));
+ write32(0x41001,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel));
- write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel,
- (slotrank << 24) | 0x60000);
+ write32((slotrank << 24) | 0x60000,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel));
- write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0x3e0);
+ write32(0x3e0,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel));
- write32(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel, 1);
+ write32(1,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel));
wait_428c(channel);
- write32(DEFAULT_MCHBAR + 0x4020 + 0x400 * channel,
- read32(DEFAULT_MCHBAR + 0x4020 +
- 0x400 * channel) | 0x200000);
+ write32(read32((void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4020 + 0x400 * channel)) | 0x200000,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4020 + 0x400 * channel));
}
- write32(DEFAULT_MCHBAR + 0x5030, read32(DEFAULT_MCHBAR + 0x5030) & ~8);
+ write32(read32((void *)(uintptr_t)(DEFAULT_MCHBAR + 0x5030)) & ~8,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x5030));
FOR_ALL_POPULATED_CHANNELS {
wait_428c(channel);
/* choose an existing rank. */
slotrank = !(ctrl->rankmap[channel] & 1) ? 2 : 0;
- write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x0f003);
- write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel, 0x41001);
+ write32(0x0f003,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel));
+ write32(0x41001,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel));
- write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel,
- (slotrank << 24) | 0x60000);
+ write32((slotrank << 24) | 0x60000,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel));
- write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0x3e0);
+ write32(0x3e0,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel));
- write32(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel, 1);
+ write32(1,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel));
wait_428c(channel);
}
@@ -2666,11 +2780,11 @@ static void reprogram_320c(ramctr_timing * ctrl)
/* mrs commands. */
dram_mrscommands(ctrl);
- r32 = read32(DEFAULT_MCHBAR + 0x5030);
- write32(DEFAULT_MCHBAR + 0x5030, r32 | 0x20);
+ r32 = read32((void *)(uintptr_t)(DEFAULT_MCHBAR + 0x5030));
+ write32(r32 | 0x20, (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x5030));
udelay(1);
- write32(DEFAULT_MCHBAR + 0x5030, r32 & ~0x20);
+ write32(r32 & ~0x20, (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x5030));
udelay(1);
}
@@ -2755,7 +2869,8 @@ static void command_training(ramctr_timing * ctrl)
FOR_ALL_POPULATED_CHANNELS {
fill_pattern5(ctrl, channel, 0);
- write32(DEFAULT_MCHBAR + 0x4288 + 0x400 * channel, 0x1f);
+ write32(0x1f,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4288 + 0x400 * channel));
}
if (!try_reg_4004_b30(ctrl, 0) && !try_reg_4004_b30(ctrl, 2))
@@ -2786,49 +2901,57 @@ static void discover_edges_real(ramctr_timing * ctrl, int channel, int slotrank,
program_timings(ctrl, channel);
FOR_ALL_LANES {
- write32(DEFAULT_MCHBAR + 0x4340 + 0x400 * channel +
- 4 * lane, 0);
- read32(DEFAULT_MCHBAR + 0x400 * channel + 4 * lane +
- 0x4140);
+ write32(0,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4340 + 0x400 * channel + 4 * lane));
+ read32((void *)(uintptr_t)(DEFAULT_MCHBAR + 0x400 * channel + 4 * lane + 0x4140));
}
wait_428c(channel);
- write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x1f000);
- write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel,
- (0xc01 | (ctrl->tMOD << 16)));
- write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel,
- (slotrank << 24) | 0x360004);
- write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0);
-
- write32(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel, 0x1f105);
- write32(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel, 0x40411f4);
- write32(DEFAULT_MCHBAR + 0x4204 + 0x400 * channel,
- (slotrank << 24));
- write32(DEFAULT_MCHBAR + 0x4214 + 0x400 * channel, 0);
-
- write32(DEFAULT_MCHBAR + 0x4228 + 0x400 * channel, 0x1f105);
- write32(DEFAULT_MCHBAR + 0x4238 + 0x400 * channel,
- 0x1001 | ((ctrl->CAS + 8) << 16));
- write32(DEFAULT_MCHBAR + 0x4208 + 0x400 * channel,
- (slotrank << 24) | 0x60000);
- write32(DEFAULT_MCHBAR + 0x4218 + 0x400 * channel, 0);
-
- write32(DEFAULT_MCHBAR + 0x422c + 0x400 * channel, 0x1f000);
- write32(DEFAULT_MCHBAR + 0x423c + 0x400 * channel,
- (0xc01 | (ctrl->tMOD << 16)));
- write32(DEFAULT_MCHBAR + 0x420c + 0x400 * channel,
- (slotrank << 24) | 0x360000);
- write32(DEFAULT_MCHBAR + 0x421c + 0x400 * channel, 0);
-
- write32(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel, 0xc0001);
+ write32(0x1f000,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel));
+ write32((0xc01 | (ctrl->tMOD << 16)),
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel));
+ write32((slotrank << 24) | 0x360004,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel));
+ write32(0,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel));
+
+ write32(0x1f105,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel));
+ write32(0x40411f4,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel));
+ write32((slotrank << 24),
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4204 + 0x400 * channel));
+ write32(0,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4214 + 0x400 * channel));
+
+ write32(0x1f105,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4228 + 0x400 * channel));
+ write32(0x1001 | ((ctrl->CAS + 8) << 16),
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4238 + 0x400 * channel));
+ write32((slotrank << 24) | 0x60000,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4208 + 0x400 * channel));
+ write32(0,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4218 + 0x400 * channel));
+
+ write32(0x1f000,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x422c + 0x400 * channel));
+ write32((0xc01 | (ctrl->tMOD << 16)),
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x423c + 0x400 * channel));
+ write32((slotrank << 24) | 0x360000,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x420c + 0x400 * channel));
+ write32(0,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x421c + 0x400 * channel));
+
+ write32(0xc0001,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel));
wait_428c(channel);
FOR_ALL_LANES {
statistics[lane][edge] =
- read32(DEFAULT_MCHBAR + 0x4340 + 0x400 * channel +
- lane * 4);
+ read32((void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4340 + 0x400 * channel + lane * 4));
}
}
FOR_ALL_LANES {
@@ -2849,27 +2972,27 @@ static void discover_edges(ramctr_timing * ctrl)
int channel, slotrank, lane;
u32 r32;
- write32(DEFAULT_MCHBAR + 0x3400, 0);
+ write32(0, (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x3400));
- r32 = read32(DEFAULT_MCHBAR + 0x5030);
- write32(DEFAULT_MCHBAR + 0x5030, r32 | 0x20);
+ r32 = read32((void *)(uintptr_t)(DEFAULT_MCHBAR + 0x5030));
+ write32(r32 | 0x20, (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x5030));
udelay(1);
- write32(DEFAULT_MCHBAR + 0x5030, r32 & ~0x20);
+ write32(r32 & ~0x20, (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x5030));
udelay(1);
FOR_ALL_POPULATED_CHANNELS FOR_ALL_LANES {
- write32(DEFAULT_MCHBAR + 4 * lane +
- 0x400 * channel + 0x4080, 0);
+ write32(0,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 4 * lane + 0x400 * channel + 0x4080));
}
FOR_ALL_POPULATED_CHANNELS {
fill_pattern0(ctrl, channel, 0, 0);
- write32(DEFAULT_MCHBAR | 0x4288 | (channel << 10), 0);
+ write32(0,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR | 0x4288 | (channel << 10)));
FOR_ALL_LANES {
- read32(DEFAULT_MCHBAR + 0x400 * channel +
- lane * 4 + 0x4140);
+ read32((void *)(uintptr_t)(DEFAULT_MCHBAR + 0x400 * channel + lane * 4 + 0x4140));
}
FOR_ALL_POPULATED_RANKS FOR_ALL_LANES {
@@ -2884,39 +3007,43 @@ static void discover_edges(ramctr_timing * ctrl)
FOR_ALL_POPULATED_RANKS {
wait_428c(channel);
- write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel,
- 0x1f000);
- write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel,
- 0xc01 | (ctrl->tMOD << 16));
- write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel,
- (slotrank << 24) | 0x360004);
- write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0);
-
- write32(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel,
- 0x1f105);
- write32(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel,
- 0x4041003);
- write32(DEFAULT_MCHBAR + 0x4204 + 0x400 * channel,
- (slotrank << 24) | 0);
- write32(DEFAULT_MCHBAR + 0x4214 + 0x400 * channel, 0);
-
- write32(DEFAULT_MCHBAR + 0x4228 + 0x400 * channel,
- 0x1f105);
- write32(DEFAULT_MCHBAR + 0x4238 + 0x400 * channel,
- 0x1001 | ((ctrl->CAS + 8) << 16));
- write32(DEFAULT_MCHBAR + 0x4208 + 0x400 * channel,
- (slotrank << 24) | 0x60000);
- write32(DEFAULT_MCHBAR + 0x4218 + 0x400 * channel, 0);
-
- write32(DEFAULT_MCHBAR + 0x422c + 0x400 * channel,
- 0x1f000);
- write32(DEFAULT_MCHBAR + 0x423c + 0x400 * channel,
- 0xc01 | (ctrl->tMOD << 16));
- write32(DEFAULT_MCHBAR + 0x420c + 0x400 * channel,
- (slotrank << 24) | 0x360000);
- write32(DEFAULT_MCHBAR + 0x421c + 0x400 * channel, 0);
- write32(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel,
- 0xc0001);
+ write32(0x1f000,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel));
+ write32(0xc01 | (ctrl->tMOD << 16),
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel));
+ write32((slotrank << 24) | 0x360004,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel));
+ write32(0,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel));
+
+ write32(0x1f105,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel));
+ write32(0x4041003,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel));
+ write32((slotrank << 24) | 0,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4204 + 0x400 * channel));
+ write32(0,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4214 + 0x400 * channel));
+
+ write32(0x1f105,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4228 + 0x400 * channel));
+ write32(0x1001 | ((ctrl->CAS + 8) << 16),
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4238 + 0x400 * channel));
+ write32((slotrank << 24) | 0x60000,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4208 + 0x400 * channel));
+ write32(0,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4218 + 0x400 * channel));
+
+ write32(0x1f000,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x422c + 0x400 * channel));
+ write32(0xc01 | (ctrl->tMOD << 16),
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x423c + 0x400 * channel));
+ write32((slotrank << 24) | 0x360000,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x420c + 0x400 * channel));
+ write32(0,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x421c + 0x400 * channel));
+ write32(0xc0001,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel));
wait_428c(channel);
}
@@ -2933,70 +3060,73 @@ static void discover_edges(ramctr_timing * ctrl)
FOR_ALL_POPULATED_RANKS {
wait_428c(channel);
- write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel,
- 0x1f000);
- write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel,
- 0xc01 | (ctrl->tMOD << 16));
- write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel,
- (slotrank << 24) | 0x360004);
- write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0);
-
- write32(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel,
- 0x1f105);
- write32(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel,
- 0x4041003);
- write32(DEFAULT_MCHBAR + 0x4204 + 0x400 * channel,
- (slotrank << 24) | 0);
- write32(DEFAULT_MCHBAR + 0x4214 + 0x400 * channel, 0);
-
- write32(DEFAULT_MCHBAR + 0x4228 + 0x400 * channel,
- 0x1f105);
- write32(DEFAULT_MCHBAR + 0x4238 + 0x400 * channel,
- 0x1001 | ((ctrl->CAS + 8) << 16));
- write32(DEFAULT_MCHBAR + 0x4208 + 0x400 * channel,
- (slotrank << 24) | 0x60000);
- write32(DEFAULT_MCHBAR + 0x4218 + 0x400 * channel, 0);
-
- write32(DEFAULT_MCHBAR + 0x422c + 0x400 * channel,
- 0x1f000);
- write32(DEFAULT_MCHBAR + 0x423c + 0x400 * channel,
- 0xc01 | (ctrl->tMOD << 16));
- write32(DEFAULT_MCHBAR + 0x420c + 0x400 * channel,
- (slotrank << 24) | 0x360000);
- write32(DEFAULT_MCHBAR + 0x421c + 0x400 * channel, 0);
-
- write32(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel,
- 0xc0001);
+ write32(0x1f000,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel));
+ write32(0xc01 | (ctrl->tMOD << 16),
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel));
+ write32((slotrank << 24) | 0x360004,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel));
+ write32(0,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel));
+
+ write32(0x1f105,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel));
+ write32(0x4041003,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel));
+ write32((slotrank << 24) | 0,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4204 + 0x400 * channel));
+ write32(0,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4214 + 0x400 * channel));
+
+ write32(0x1f105,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4228 + 0x400 * channel));
+ write32(0x1001 | ((ctrl->CAS + 8) << 16),
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4238 + 0x400 * channel));
+ write32((slotrank << 24) | 0x60000,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4208 + 0x400 * channel));
+ write32(0,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4218 + 0x400 * channel));
+
+ write32(0x1f000,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x422c + 0x400 * channel));
+ write32(0xc01 | (ctrl->tMOD << 16),
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x423c + 0x400 * channel));
+ write32((slotrank << 24) | 0x360000,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x420c + 0x400 * channel));
+ write32(0,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x421c + 0x400 * channel));
+
+ write32(0xc0001,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel));
wait_428c(channel);
}
FOR_ALL_LANES {
- write32(DEFAULT_MCHBAR + 0x4080 + 0x400 * channel +
- lane * 4,
- ~read32(DEFAULT_MCHBAR + 0x4040 +
- 0x400 * channel + lane * 4) & 0xff);
+ write32(~read32((void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4040 + 0x400 * channel + lane * 4)) & 0xff,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4080 + 0x400 * channel + lane * 4));
}
fill_pattern0(ctrl, channel, 0, 0xffffffff);
- write32(DEFAULT_MCHBAR | 0x4288 | (channel << 10), 0);
+ write32(0,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR | 0x4288 | (channel << 10)));
}
/* FIXME: under some conditions (older chipsets?) vendor BIOS sets both edges to the same value. */
- write32(DEFAULT_MCHBAR + 0x4eb0, 0x300);
+ write32(0x300, (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4eb0));
FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS {
discover_edges_real(ctrl, channel, slotrank,
falling_edges[channel][slotrank]);
}
- write32(DEFAULT_MCHBAR + 0x4eb0, 0x200);
+ write32(0x200, (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4eb0));
FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS {
discover_edges_real(ctrl, channel, slotrank,
rising_edges[channel][slotrank]);
}
- write32(DEFAULT_MCHBAR + 0x4eb0, 0);
+ write32(0, (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4eb0));
FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES {
ctrl->timings[channel][slotrank].lanes[lane].falling =
@@ -3010,8 +3140,8 @@ static void discover_edges(ramctr_timing * ctrl)
}
FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES {
- write32(DEFAULT_MCHBAR + 0x4080 + 0x400 * channel + 4 * lane,
- 0);
+ write32(0,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4080 + 0x400 * channel + 4 * lane));
}
}
@@ -3033,11 +3163,12 @@ static void discover_edges_write_real(ramctr_timing * ctrl, int channel,
}
for (i = 0; i < 3; i++) {
- write32(DEFAULT_MCHBAR + 0x3000 + 0x100 * channel,
- reg3000b24[i] << 24);
+ write32(reg3000b24[i] << 24,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x3000 + 0x100 * channel));
for (pat = 0; pat < NUM_PATTERNS; pat++) {
fill_pattern5(ctrl, channel, pat);
- write32(DEFAULT_MCHBAR + 0x4288 + 0x400 * channel, 0x1f);
+ write32(0x1f,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4288 + 0x400 * channel));
printram("patterned\n");
printram("[%x] = 0x%08x\n(%d, %d)\n",
0x3000 + 0x100 * channel, reg3000b24[i] << 24, channel,
@@ -3052,57 +3183,53 @@ static void discover_edges_write_real(ramctr_timing * ctrl, int channel,
program_timings(ctrl, channel);
FOR_ALL_LANES {
- write32(DEFAULT_MCHBAR + 0x4340 +
- 0x400 * channel + 4 * lane, 0);
- read32(DEFAULT_MCHBAR + 0x400 * channel +
- 4 * lane + 0x4140);
+ write32(0,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4340 + 0x400 * channel + 4 * lane));
+ read32((void *)(uintptr_t)(DEFAULT_MCHBAR + 0x400 * channel + 4 * lane + 0x4140));
}
wait_428c(channel);
- write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel,
- 0x1f006);
- write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel,
- 0x4 | (ctrl->tRCD << 16)
- | (max(ctrl->tRRD, (ctrl->tFAW >> 2) + 1) <<
- 10));
- write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel,
- (slotrank << 24) | 0x60000);
- write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel,
- 0x240);
-
- write32(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel,
- 0x1f201);
- write32(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel,
- 0x8005020 | ((ctrl->tWTR + ctrl->CWL + 8) <<
- 16));
- write32(DEFAULT_MCHBAR + 0x4204 + 0x400 * channel,
- (slotrank << 24));
- write32(DEFAULT_MCHBAR + 0x4214 + 0x400 * channel,
- 0x242);
-
- write32(DEFAULT_MCHBAR + 0x4228 + 0x400 * channel,
- 0x1f105);
- write32(DEFAULT_MCHBAR + 0x4238 + 0x400 * channel,
- 0x4005020 | (max(ctrl->tRTP, 8) << 16));
- write32(DEFAULT_MCHBAR + 0x4208 + 0x400 * channel,
- (slotrank << 24));
- write32(DEFAULT_MCHBAR + 0x4218 + 0x400 * channel,
- 0x242);
-
- write32(DEFAULT_MCHBAR + 0x422c + 0x400 * channel,
- 0x1f002);
- write32(DEFAULT_MCHBAR + 0x423c + 0x400 * channel,
- 0xc01 | (ctrl->tRP << 16));
- write32(DEFAULT_MCHBAR + 0x420c + 0x400 * channel,
- (slotrank << 24) | 0x60400);
- write32(DEFAULT_MCHBAR + 0x421c + 0x400 * channel, 0);
-
- write32(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel,
- 0xc0001);
+ write32(0x1f006,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel));
+ write32(0x4 | (ctrl->tRCD << 16) | (max(ctrl->tRRD, (ctrl->tFAW >> 2) + 1) << 10),
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel));
+ write32((slotrank << 24) | 0x60000,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel));
+ write32(0x240,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel));
+
+ write32(0x1f201,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel));
+ write32(0x8005020 | ((ctrl->tWTR + ctrl->CWL + 8) << 16),
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel));
+ write32((slotrank << 24),
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4204 + 0x400 * channel));
+ write32(0x242,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4214 + 0x400 * channel));
+
+ write32(0x1f105,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4228 + 0x400 * channel));
+ write32(0x4005020 | (max(ctrl->tRTP, 8) << 16),
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4238 + 0x400 * channel));
+ write32((slotrank << 24),
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4208 + 0x400 * channel));
+ write32(0x242,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4218 + 0x400 * channel));
+
+ write32(0x1f002,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x422c + 0x400 * channel));
+ write32(0xc01 | (ctrl->tRP << 16),
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x423c + 0x400 * channel));
+ write32((slotrank << 24) | 0x60400,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x420c + 0x400 * channel));
+ write32(0,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x421c + 0x400 * channel));
+
+ write32(0xc0001,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel));
wait_428c(channel);
FOR_ALL_LANES {
- read32(DEFAULT_MCHBAR + 0x4340 +
- 0x400 * channel + lane * 4);
+ read32((void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4340 + 0x400 * channel + lane * 4));
}
raw_statistics[edge] =
@@ -3129,7 +3256,7 @@ static void discover_edges_write_real(ramctr_timing * ctrl, int channel,
}
}
- write32(DEFAULT_MCHBAR + 0x3000, 0);
+ write32(0, (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x3000));
printram("CPA\n");
}
@@ -3140,21 +3267,21 @@ static void discover_edges_write(ramctr_timing * ctrl)
int channel, slotrank, lane;
/* FIXME: under some conditions (older chipsets?) vendor BIOS sets both edges to the same value. */
- write32(DEFAULT_MCHBAR + 0x4eb0, 0x300);
+ write32(0x300, (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4eb0));
FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS {
discover_edges_write_real(ctrl, channel, slotrank,
falling_edges[channel][slotrank]);
}
- write32(DEFAULT_MCHBAR + 0x4eb0, 0x200);
+ write32(0x200, (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4eb0));
FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS {
discover_edges_write_real(ctrl, channel, slotrank,
rising_edges[channel][slotrank]);
}
- write32(DEFAULT_MCHBAR + 0x4eb0, 0);
+ write32(0, (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4eb0));
FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES {
ctrl->timings[channel][slotrank].lanes[lane].falling =
@@ -3167,54 +3294,52 @@ static void discover_edges_write(ramctr_timing * ctrl)
program_timings(ctrl, channel);
FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES {
- write32(DEFAULT_MCHBAR + 0x4080 + 0x400 * channel + 4 * lane,
- 0);
+ write32(0,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4080 + 0x400 * channel + 4 * lane));
}
}
static void test_timC_write(ramctr_timing *ctrl, int channel, int slotrank)
{
wait_428c(channel);
- write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x1f006);
- write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel,
- (max((ctrl->tFAW >> 2) + 1, ctrl->tRRD)
- << 10) | (ctrl->tRCD << 16) | 4);
- write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel,
- (slotrank << 24) | 0x60000);
- write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0x244);
-
- write32(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel, 0x1f201);
- write32(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel,
- 0x80011e0 |
- ((ctrl->tWTR + ctrl->CWL + 8) << 16));
- write32(DEFAULT_MCHBAR + 0x4204 +
- 0x400 * channel, (slotrank << 24));
- write32(DEFAULT_MCHBAR + 0x4214 +
- 0x400 * channel, 0x242);
-
- write32(DEFAULT_MCHBAR + 0x4228 +
- 0x400 * channel, 0x1f105);
- write32(DEFAULT_MCHBAR + 0x4238 +
- 0x400 * channel,
- 0x40011e0 | (max(ctrl->tRTP, 8) << 16));
- write32(DEFAULT_MCHBAR + 0x4208 +
- 0x400 * channel, (slotrank << 24));
- write32(DEFAULT_MCHBAR + 0x4218 +
- 0x400 * channel, 0x242);
-
- write32(DEFAULT_MCHBAR + 0x422c +
- 0x400 * channel, 0x1f002);
- write32(DEFAULT_MCHBAR + 0x423c +
- 0x400 * channel,
- 0x1001 | (ctrl->tRP << 16));
- write32(DEFAULT_MCHBAR + 0x420c +
- 0x400 * channel,
- (slotrank << 24) | 0x60400);
- write32(DEFAULT_MCHBAR + 0x421c +
- 0x400 * channel, 0);
-
- write32(DEFAULT_MCHBAR + 0x4284 +
- 0x400 * channel, 0xc0001);
+ write32(0x1f006,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel));
+ write32((max((ctrl->tFAW >> 2) + 1, ctrl->tRRD) << 10) | (ctrl->tRCD << 16) | 4,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel));
+ write32((slotrank << 24) | 0x60000,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel));
+ write32(0x244,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel));
+
+ write32(0x1f201,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel));
+ write32(0x80011e0 | ((ctrl->tWTR + ctrl->CWL + 8) << 16),
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel));
+ write32((slotrank << 24),
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4204 + 0x400 * channel));
+ write32(0x242,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4214 + 0x400 * channel));
+
+ write32(0x1f105,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4228 + 0x400 * channel));
+ write32(0x40011e0 | (max(ctrl->tRTP, 8) << 16),
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4238 + 0x400 * channel));
+ write32((slotrank << 24),
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4208 + 0x400 * channel));
+ write32(0x242,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4218 + 0x400 * channel));
+
+ write32(0x1f002,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x422c + 0x400 * channel));
+ write32(0x1001 | (ctrl->tRP << 16),
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x423c + 0x400 * channel));
+ write32((slotrank << 24) | 0x60400,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x420c + 0x400 * channel));
+ write32(0,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x421c + 0x400 * channel));
+
+ write32(0xc0001,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel));
wait_428c(channel);
}
@@ -3232,14 +3357,12 @@ static void discover_timC_write(ramctr_timing * ctrl)
upper[channel][slotrank][lane] = MAX_TIMC;
}
- write32(DEFAULT_MCHBAR + 0x4ea8, 1);
+ write32(1, (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4ea8));
for (i = 0; i < 3; i++)
FOR_ALL_POPULATED_CHANNELS {
- write32(DEFAULT_MCHBAR + 0xe3c + (channel * 0x100),
- (rege3c_b24[i] << 24)
- | (read32(DEFAULT_MCHBAR + 0xe3c + (channel * 0x100))
- & ~0x3f000000));
+ write32((rege3c_b24[i] << 24) | (read32((void *)(uintptr_t)(DEFAULT_MCHBAR + 0xe3c + (channel * 0x100))) & ~0x3f000000),
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0xe3c + (channel * 0x100)));
udelay(2);
for (pat = 0; pat < NUM_PATTERNS; pat++) {
FOR_ALL_POPULATED_RANKS {
@@ -3248,7 +3371,8 @@ static void discover_timC_write(ramctr_timing * ctrl)
int statistics[MAX_TIMC + 1];
fill_pattern5(ctrl, channel, pat);
- write32(DEFAULT_MCHBAR + 0x4288 + 0x400 * channel, 0x1f);
+ write32(0x1f,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4288 + 0x400 * channel));
for (timC = 0; timC < MAX_TIMC + 1; timC++) {
FOR_ALL_LANES
ctrl->timings[channel][slotrank].lanes[lane].timC = timC;
@@ -3287,13 +3411,12 @@ static void discover_timC_write(ramctr_timing * ctrl)
}
FOR_ALL_CHANNELS {
- write32(DEFAULT_MCHBAR + (channel * 0x100) + 0xe3c,
- 0 | (read32(DEFAULT_MCHBAR + (channel * 0x100) + 0xe3c) &
- ~0x3f000000));
+ write32(0 | (read32((void *)(uintptr_t)(DEFAULT_MCHBAR + (channel * 0x100) + 0xe3c)) & ~0x3f000000),
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + (channel * 0x100) + 0xe3c));
udelay(2);
}
- write32(DEFAULT_MCHBAR + 0x4ea8, 0);
+ write32(0, (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4ea8));
printram("CPB\n");
@@ -3335,10 +3458,10 @@ static void write_controller_mr(ramctr_timing * ctrl)
int channel, slotrank;
FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS {
- write32(DEFAULT_MCHBAR | 0x0004 | (channel << 8) |
- lane_registers[slotrank], make_mr0(ctrl, slotrank));
- write32(DEFAULT_MCHBAR | 0x0008 | (channel << 8) |
- lane_registers[slotrank], make_mr1(ctrl, slotrank));
+ write32(make_mr0(ctrl, slotrank),
+ (void *)(uintptr_t)(DEFAULT_MCHBAR | 0x0004 | (channel << 8) | lane_registers[slotrank]));
+ write32(make_mr1(ctrl, slotrank),
+ (void *)(uintptr_t)(DEFAULT_MCHBAR | 0x0008 | (channel << 8) | lane_registers[slotrank]));
}
}
@@ -3347,46 +3470,62 @@ static void channel_test(ramctr_timing * ctrl)
int channel, slotrank, lane;
FOR_ALL_POPULATED_CHANNELS
- if (read32(DEFAULT_MCHBAR | 0x42a0 | (channel << 10)) & 0xa000)
+ if (read32((void *)(uintptr_t)(DEFAULT_MCHBAR | 0x42a0 | (channel << 10))) & 0xa000)
die("Mini channel test failed (1)\n");
FOR_ALL_POPULATED_CHANNELS {
fill_pattern0(ctrl, channel, 0x12345678, 0x98765432);
- write32(DEFAULT_MCHBAR | 0x4288 | (channel << 10), 0);
+ write32(0,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR | 0x4288 | (channel << 10)));
}
for (slotrank = 0; slotrank < 4; slotrank++)
FOR_ALL_CHANNELS
if (ctrl->rankmap[channel] & (1 << slotrank)) {
FOR_ALL_LANES {
- write32(DEFAULT_MCHBAR | (0x4f40 + 4 * lane), 0);
- write32(DEFAULT_MCHBAR | (0x4d40 + 4 * lane), 0);
+ write32(0,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR | (0x4f40 + 4 * lane)));
+ write32(0,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR | (0x4d40 + 4 * lane)));
}
wait_428c(channel);
- write32(DEFAULT_MCHBAR | 0x4220 | (channel << 10), 0x0001f006);
- write32(DEFAULT_MCHBAR | 0x4230 | (channel << 10), 0x0028a004);
- write32(DEFAULT_MCHBAR | 0x4200 | (channel << 10),
- 0x00060000 | (slotrank << 24));
- write32(DEFAULT_MCHBAR | 0x4210 | (channel << 10), 0x00000244);
- write32(DEFAULT_MCHBAR | 0x4224 | (channel << 10), 0x0001f201);
- write32(DEFAULT_MCHBAR | 0x4234 | (channel << 10), 0x08281064);
- write32(DEFAULT_MCHBAR | 0x4204 | (channel << 10),
- 0x00000000 | (slotrank << 24));
- write32(DEFAULT_MCHBAR | 0x4214 | (channel << 10), 0x00000242);
- write32(DEFAULT_MCHBAR | 0x4228 | (channel << 10), 0x0001f105);
- write32(DEFAULT_MCHBAR | 0x4238 | (channel << 10), 0x04281064);
- write32(DEFAULT_MCHBAR | 0x4208 | (channel << 10),
- 0x00000000 | (slotrank << 24));
- write32(DEFAULT_MCHBAR | 0x4218 | (channel << 10), 0x00000242);
- write32(DEFAULT_MCHBAR | 0x422c | (channel << 10), 0x0001f002);
- write32(DEFAULT_MCHBAR | 0x423c | (channel << 10), 0x00280c01);
- write32(DEFAULT_MCHBAR | 0x420c | (channel << 10),
- 0x00060400 | (slotrank << 24));
- write32(DEFAULT_MCHBAR | 0x421c | (channel << 10), 0x00000240);
- write32(DEFAULT_MCHBAR | 0x4284 | (channel << 10), 0x000c0001);
+ write32(0x0001f006,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR | 0x4220 | (channel << 10)));
+ write32(0x0028a004,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR | 0x4230 | (channel << 10)));
+ write32(0x00060000 | (slotrank << 24),
+ (void *)(uintptr_t)(DEFAULT_MCHBAR | 0x4200 | (channel << 10)));
+ write32(0x00000244,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR | 0x4210 | (channel << 10)));
+ write32(0x0001f201,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR | 0x4224 | (channel << 10)));
+ write32(0x08281064,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR | 0x4234 | (channel << 10)));
+ write32(0x00000000 | (slotrank << 24),
+ (void *)(uintptr_t)(DEFAULT_MCHBAR | 0x4204 | (channel << 10)));
+ write32(0x00000242,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR | 0x4214 | (channel << 10)));
+ write32(0x0001f105,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR | 0x4228 | (channel << 10)));
+ write32(0x04281064,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR | 0x4238 | (channel << 10)));
+ write32(0x00000000 | (slotrank << 24),
+ (void *)(uintptr_t)(DEFAULT_MCHBAR | 0x4208 | (channel << 10)));
+ write32(0x00000242,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR | 0x4218 | (channel << 10)));
+ write32(0x0001f002,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR | 0x422c | (channel << 10)));
+ write32(0x00280c01,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR | 0x423c | (channel << 10)));
+ write32(0x00060400 | (slotrank << 24),
+ (void *)(uintptr_t)(DEFAULT_MCHBAR | 0x420c | (channel << 10)));
+ write32(0x00000240,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR | 0x421c | (channel << 10)));
+ write32(0x000c0001,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR | 0x4284 | (channel << 10)));
wait_428c(channel);
FOR_ALL_LANES
- if (read32(DEFAULT_MCHBAR | 0x4340 | (channel << 10)))
+ if (read32((void *)(uintptr_t)(DEFAULT_MCHBAR | 0x4340 | (channel << 10))))
die("Mini channel test failed (2)\n");
}
}
@@ -3403,9 +3542,12 @@ static void set_scrambling_seed(ramctr_timing * ctrl)
};
FOR_ALL_POPULATED_CHANNELS {
MCHBAR32(0x4020 + 0x400 * channel) &= ~0x10000000;
- write32(DEFAULT_MCHBAR | 0x4034, seeds[channel][0]);
- write32(DEFAULT_MCHBAR | 0x403c, seeds[channel][1]);
- write32(DEFAULT_MCHBAR | 0x4038, seeds[channel][2]);
+ write32(seeds[channel][0],
+ (void *)(uintptr_t)(DEFAULT_MCHBAR | 0x4034));
+ write32(seeds[channel][1],
+ (void *)(uintptr_t)(DEFAULT_MCHBAR | 0x403c));
+ write32(seeds[channel][2],
+ (void *)(uintptr_t)(DEFAULT_MCHBAR | 0x4038));
}
}
@@ -3463,16 +3605,11 @@ static void set_4008c(ramctr_timing * ctrl)
else
b4_8_12 = 0x2220;
- reg = read32(DEFAULT_MCHBAR | 0x400c | (channel << 10));
- write32(DEFAULT_MCHBAR | 0x400c | (channel << 10),
- (reg & 0xFFF0FFFF)
- | (ctrl->ref_card_offset[channel] << 16)
- | (ctrl->ref_card_offset[channel] << 18));
- write32(DEFAULT_MCHBAR | 0x4008 | (channel << 10),
- 0x0a000000
- | (b20 << 20)
- | ((ctrl->ref_card_offset[channel] + 2) << 16)
- | b4_8_12);
+ reg = read32((void *)(uintptr_t)(DEFAULT_MCHBAR | 0x400c | (channel << 10)));
+ write32((reg & 0xFFF0FFFF) | (ctrl->ref_card_offset[channel] << 16) | (ctrl->ref_card_offset[channel] << 18),
+ (void *)(uintptr_t)(DEFAULT_MCHBAR | 0x400c | (channel << 10)));
+ write32(0x0a000000 | (b20 << 20) | ((ctrl->ref_card_offset[channel] + 2) << 16) | b4_8_12,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR | 0x4008 | (channel << 10)));
}
}
@@ -3480,8 +3617,8 @@ static void set_42a0(ramctr_timing * ctrl)
{
int channel;
FOR_ALL_POPULATED_CHANNELS {
- write32(DEFAULT_MCHBAR | (0x42a0 + 0x400 * channel),
- 0x00001000 | ctrl->rankmap[channel]);
+ write32(0x00001000 | ctrl->rankmap[channel],
+ (void *)(uintptr_t)(DEFAULT_MCHBAR | (0x42a0 + 0x400 * channel)));
MCHBAR32(0x4004 + 0x400 * channel) &= ~0x20000000; // OK
}
}
@@ -3499,45 +3636,50 @@ static void final_registers(ramctr_timing * ctrl)
int t3_ns;
u32 r32;
- write32(DEFAULT_MCHBAR | 0x4cd4, 0x00000046);
+ write32(0x00000046, (void *)(uintptr_t)(DEFAULT_MCHBAR | 0x4cd4));
- write32(DEFAULT_MCHBAR | 0x400c, (read32(DEFAULT_MCHBAR | 0x400c) & 0xFFFFCFFF) | 0x1000); // OK
- write32(DEFAULT_MCHBAR | 0x440c, (read32(DEFAULT_MCHBAR | 0x440c) & 0xFFFFCFFF) | 0x1000); // OK
- write32(DEFAULT_MCHBAR | 0x4cb0, 0x00000740);
- write32(DEFAULT_MCHBAR | 0x4380, 0x00000aaa); // OK
- write32(DEFAULT_MCHBAR | 0x4780, 0x00000aaa); // OK
- write32(DEFAULT_MCHBAR | 0x4f88, 0x5f7003ff); // OK
- write32(DEFAULT_MCHBAR | 0x5064, 0x00073000 | ctrl->reg_5064b0); // OK
+ write32((read32((void *)(uintptr_t)(DEFAULT_MCHBAR | 0x400c)) & 0xFFFFCFFF) | 0x1000,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR | 0x400c)); // OK
+ write32((read32((void *)(uintptr_t)(DEFAULT_MCHBAR | 0x440c)) & 0xFFFFCFFF) | 0x1000,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR | 0x440c)); // OK
+ write32(0x00000740, (void *)(uintptr_t)(DEFAULT_MCHBAR | 0x4cb0));
+ write32(0x00000aaa, (void *)(uintptr_t)(DEFAULT_MCHBAR | 0x4380)); // OK
+ write32(0x00000aaa, (void *)(uintptr_t)(DEFAULT_MCHBAR | 0x4780)); // OK
+ write32(0x5f7003ff, (void *)(uintptr_t)(DEFAULT_MCHBAR | 0x4f88)); // OK
+ write32(0x00073000 | ctrl->reg_5064b0,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR | 0x5064)); // OK
FOR_ALL_CHANNELS {
switch (ctrl->rankmap[channel]) {
/* Unpopulated channel. */
case 0:
- write32(DEFAULT_MCHBAR + 0x4384 + channel * 0x400, 0);
+ write32(0,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4384 + channel * 0x400));
break;
/* Only single-ranked dimms. */
case 1:
case 4:
case 5:
- write32(DEFAULT_MCHBAR + 0x4384 + channel * 0x400, 0x373131);
+ write32(0x373131,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4384 + channel * 0x400));
break;
/* Dual-ranked dimms present. */
default:
- write32(DEFAULT_MCHBAR + 0x4384 + channel * 0x400, 0x9b6ea1);
+ write32(0x9b6ea1,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4384 + channel * 0x400));
break;
}
}
- write32 (DEFAULT_MCHBAR | 0x5880, 0xca9171e5);
- write32 (DEFAULT_MCHBAR | 0x5888,
- (read32 (DEFAULT_MCHBAR | 0x5888) & ~0xffffff) | 0xe4d5d0);
- write32 (DEFAULT_MCHBAR | 0x58a8, read32 (DEFAULT_MCHBAR | 0x58a8) & ~0x1f);
- write32 (DEFAULT_MCHBAR | 0x4294,
- (read32 (DEFAULT_MCHBAR | 0x4294) & ~0x30000)
- | (1 << 16));
- write32 (DEFAULT_MCHBAR | 0x4694,
- (read32 (DEFAULT_MCHBAR | 0x4694) & ~0x30000)
- | (1 << 16));
+ write32(0xca9171e5, (void *)(uintptr_t)(DEFAULT_MCHBAR | 0x5880));
+ write32((read32((void *)(uintptr_t)(DEFAULT_MCHBAR | 0x5888)) & ~0xffffff) | 0xe4d5d0,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR | 0x5888));
+ write32(read32((void *)(uintptr_t)(DEFAULT_MCHBAR | 0x58a8)) & ~0x1f,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR | 0x58a8));
+ write32((read32((void *)(uintptr_t)(DEFAULT_MCHBAR | 0x4294)) & ~0x30000) | (1 << 16),
+ (void *)(uintptr_t)(DEFAULT_MCHBAR | 0x4294));
+ write32((read32((void *)(uintptr_t)(DEFAULT_MCHBAR | 0x4694)) & ~0x30000) | (1 << 16),
+ (void *)(uintptr_t)(DEFAULT_MCHBAR | 0x4694));
MCHBAR32(0x5030) |= 1; // OK
MCHBAR32(0x5030) |= 0x80; // OK
@@ -3547,20 +3689,20 @@ static void final_registers(ramctr_timing * ctrl)
FOR_ALL_POPULATED_CHANNELS
break;
- t1_cycles = ((read32(DEFAULT_MCHBAR + 0x4290 + channel * 0x400) >> 8) & 0xff);
- r32 = read32(DEFAULT_MCHBAR + 0x5064);
+ t1_cycles = ((read32((void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4290 + channel * 0x400)) >> 8) & 0xff);
+ r32 = read32((void *)(uintptr_t)(DEFAULT_MCHBAR + 0x5064));
if (r32 & 0x20000)
t1_cycles += (r32 & 0xfff);
- t1_cycles += (read32(DEFAULT_MCHBAR + channel * 0x400 + 0x42a4) & 0xfff);
+ t1_cycles += (read32((void *)(uintptr_t)(DEFAULT_MCHBAR + channel * 0x400 + 0x42a4)) & 0xfff);
t1_ns = t1_cycles * ctrl->tCK / 256 + 544;
if (!(r32 & 0x20000))
t1_ns += 500;
- t2_ns = 10 * ((read32(DEFAULT_MCHBAR + 0x5f10) >> 8) & 0xfff);
- if ( read32(DEFAULT_MCHBAR + 0x5f00) & 8 )
+ t2_ns = 10 * ((read32((void *)(uintptr_t)(DEFAULT_MCHBAR + 0x5f10)) >> 8) & 0xfff);
+ if (read32((void *)(uintptr_t)(DEFAULT_MCHBAR + 0x5f00)) & 8 )
{
- t3_ns = 10 * ((read32(DEFAULT_MCHBAR + 0x5f20) >> 8) & 0xfff);
- t3_ns += 10 * (read32(DEFAULT_MCHBAR + 0x5f18) & 0xff);
+ t3_ns = 10 * ((read32((void *)(uintptr_t)(DEFAULT_MCHBAR + 0x5f20)) >> 8) & 0xfff);
+ t3_ns += 10 * (read32((void *)(uintptr_t)(DEFAULT_MCHBAR + 0x5f18)) & 0xff);
}
else
{
@@ -3568,12 +3710,8 @@ static void final_registers(ramctr_timing * ctrl)
}
printk(BIOS_DEBUG, "t123: %d, %d, %d\n",
t1_ns, t2_ns, t3_ns);
- write32 (DEFAULT_MCHBAR + 0x5d10,
- ((encode_5d10(t1_ns) + encode_5d10(t2_ns)) << 16)
- | (encode_5d10(t1_ns) << 8)
- | ((encode_5d10(t3_ns) + encode_5d10(t2_ns) + encode_5d10(t1_ns)) << 24)
- | (read32(DEFAULT_MCHBAR + 0x5d10) & 0xC0C0C0C0)
- | 0xc);
+ write32(((encode_5d10(t1_ns) + encode_5d10(t2_ns)) << 16) | (encode_5d10(t1_ns) << 8) | ((encode_5d10(t3_ns) + encode_5d10(t2_ns) + encode_5d10(t1_ns)) << 24) | (read32((void *)(uintptr_t)(DEFAULT_MCHBAR + 0x5d10)) & 0xC0C0C0C0) | 0xc,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x5d10));
}
static void save_timings(ramctr_timing * ctrl)
@@ -3624,26 +3762,24 @@ static void restore_timings(ramctr_timing * ctrl)
}
FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES {
- write32(DEFAULT_MCHBAR + 0x4080 + 0x400 * channel
- + 4 * lane, 0);
+ write32(0,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4080 + 0x400 * channel + 4 * lane));
}
FOR_ALL_POPULATED_CHANNELS
- write32(DEFAULT_MCHBAR + 0x4008 + 0x400 * channel,
- read32(DEFAULT_MCHBAR + 0x4008 +
- 0x400 * channel) | 0x8000000);
+ write32(read32((void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4008 + 0x400 * channel)) | 0x8000000,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4008 + 0x400 * channel));
FOR_ALL_POPULATED_CHANNELS {
udelay (1);
- write32(DEFAULT_MCHBAR + 0x4020 + 0x400 * channel,
- read32(DEFAULT_MCHBAR + 0x4020 +
- 0x400 * channel) | 0x200000);
+ write32(read32((void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4020 + 0x400 * channel)) | 0x200000,
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4020 + 0x400 * channel));
}
printram("CPE\n");
- write32(DEFAULT_MCHBAR + 0x3400, 0);
- write32(DEFAULT_MCHBAR + 0x4eb0, 0);
+ write32(0, (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x3400));
+ write32(0, (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4eb0));
printram("CP5b\n");
@@ -3687,16 +3823,15 @@ static void restore_timings(ramctr_timing * ctrl)
printram("CP5c\n");
- write32(DEFAULT_MCHBAR + 0x3000, 0);
+ write32(0, (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x3000));
FOR_ALL_CHANNELS {
- write32(DEFAULT_MCHBAR + (channel * 0x100) + 0xe3c,
- 0 | (read32(DEFAULT_MCHBAR + (channel * 0x100) + 0xe3c) &
- ~0x3f000000));
+ write32(0 | (read32((void *)(uintptr_t)(DEFAULT_MCHBAR + (channel * 0x100) + 0xe3c)) & ~0x3f000000),
+ (void *)(uintptr_t)(DEFAULT_MCHBAR + (channel * 0x100) + 0xe3c));
udelay(2);
}
- write32(DEFAULT_MCHBAR + 0x4ea8, 0);
+ write32(0, (void *)(uintptr_t)(DEFAULT_MCHBAR + 0x4ea8));
}
void init_dram_ddr3(spd_raw_data * spds, int mobile, int min_tck,
@@ -3721,10 +3856,10 @@ void init_dram_ddr3(spd_raw_data * spds, int mobile, int min_tck,
wrmsr(0x000002e6, (msr_t) { .lo = 0, .hi = 0 });
- reg_5d10 = read32(DEFAULT_MCHBAR | 0x5d10); // !!! = 0x00000000
+ reg_5d10 = read32((void *)(uintptr_t)(DEFAULT_MCHBAR | 0x5d10)); // !!! = 0x00000000
if ((pcie_read_config16(SOUTHBRIDGE, 0xa2) & 0xa0) == 0x20 /* 0x0004 */
&& reg_5d10 && !s3resume) {
- write32(DEFAULT_MCHBAR | 0x5d10, 0);
+ write32(0, (void *)(uintptr_t)(DEFAULT_MCHBAR | 0x5d10));
/* Need reset. */
outb(0x6, 0xcf9);
@@ -3858,7 +3993,7 @@ void init_dram_ddr3(spd_raw_data * spds, int mobile, int min_tck,
}
/* FIXME: should be hardware revision-dependent. */
- write32(DEFAULT_MCHBAR | 0x5024, 0x00a030ce);
+ write32(0x00a030ce, (void *)(uintptr_t)(DEFAULT_MCHBAR | 0x5024));
set_scrambling_seed(&ctrl);
diff --git a/src/northbridge/via/cn700/raminit.c b/src/northbridge/via/cn700/raminit.c
index 0103c4f..22f0a24 100644
--- a/src/northbridge/via/cn700/raminit.c
+++ b/src/northbridge/via/cn700/raminit.c
@@ -401,30 +401,30 @@ static void sdram_enable(device_t dev, unsigned long rank_address)
PRINT_DEBUG_MEM("RAM Enable 1: Apply NOP\n");
do_ram_command(dev, RAM_COMMAND_NOP);
udelay(100);
- read32(rank_address + 0x10);
+ read32((void *)(uintptr_t)(rank_address + 0x10));
/* 2. Precharge all. */
udelay(400);
PRINT_DEBUG_MEM("RAM Enable 2: Precharge all\n");
do_ram_command(dev, RAM_COMMAND_PRECHARGE);
- read32(rank_address + 0x10);
+ read32((void *)(uintptr_t)(rank_address + 0x10));
/* 3. Mode register set. */
PRINT_DEBUG_MEM("RAM Enable 3: Mode register set\n");
do_ram_command(dev, RAM_COMMAND_MRS);
- read32(rank_address + 0x120000); /* EMRS DLL Enable */
- read32(rank_address + 0x800); /* MRS DLL Reset */
+ read32((void *)(uintptr_t)(rank_address + 0x120000)); /* EMRS DLL Enable */
+ read32((void *)(uintptr_t)(rank_address + 0x800)); /* MRS DLL Reset */
/* 4. Precharge all again. */
PRINT_DEBUG_MEM("RAM Enable 4: Precharge all\n");
do_ram_command(dev, RAM_COMMAND_PRECHARGE);
- read32(rank_address + 0x0);
+ read32((void *)(uintptr_t)(rank_address + 0x0));
/* 5. Perform 8 refresh cycles. Wait tRC each time. */
PRINT_DEBUG_MEM("RAM Enable 5: CBR\n");
do_ram_command(dev, RAM_COMMAND_CBR);
for (i = 0; i < 8; i++) {
- read32(rank_address + 0x20);
+ read32((void *)(uintptr_t)(rank_address + 0x20));
udelay(100);
}
@@ -437,14 +437,14 @@ static void sdram_enable(device_t dev, unsigned long rank_address)
* (JESD79-2C).
*/
do_ram_command(dev, RAM_COMMAND_MRS);
- read32(rank_address + 0x002258); /* MRS command */
- read32(rank_address + 0x121c20); /* EMRS OCD Default */
- read32(rank_address + 0x120020); /* EMRS OCD Calibration Mode Exit */
+ read32((void *)(uintptr_t)(rank_address + 0x002258)); /* MRS command */
+ read32((void *)(uintptr_t)(rank_address + 0x121c20)); /* EMRS OCD Default */
+ read32((void *)(uintptr_t)(rank_address + 0x120020)); /* EMRS OCD Calibration Mode Exit */
/* 8. Normal operation */
PRINT_DEBUG_MEM("RAM Enable 7: Normal operation\n");
do_ram_command(dev, RAM_COMMAND_NORMAL);
- read32(rank_address + 0x30);
+ read32((void *)(uintptr_t)(rank_address + 0x30));
}
/*
diff --git a/src/northbridge/via/cx700/raminit.c b/src/northbridge/via/cx700/raminit.c
index a2e6dad..aa049b0 100644
--- a/src/northbridge/via/cx700/raminit.c
+++ b/src/northbridge/via/cx700/raminit.c
@@ -967,9 +967,9 @@ static void step_20_21(const struct mem_controller *ctrl)
val = pci_read_config8(PCI_DEV(0, 0, 4), SCRATCH_DRAM_NB_ODT);
if (val & DDR2_ODT_150ohm)
- read32(0x102200);
+ read32((void *)(uintptr_t)(0x102200));
else
- read32(0x102020);
+ read32((void *)(uintptr_t)(0x102020));
/* Step 21. Normal operation */
print_spew("RAM Enable 5: Normal operation\n");
@@ -995,7 +995,7 @@ static void step_2_19(const struct mem_controller *ctrl)
// Step 4
print_spew("SEND: ");
- read32(0);
+ read32((void *)(uintptr_t)(0));
print_spew("OK\n");
// Step 5
@@ -1007,7 +1007,7 @@ static void step_2_19(const struct mem_controller *ctrl)
// Step 7
print_spew("SEND: ");
- read32(0);
+ read32((void *)(uintptr_t)(0));
print_spew("OK\n");
/* Step 8. Mode register set. */
@@ -1019,14 +1019,14 @@ static void step_2_19(const struct mem_controller *ctrl)
val = pci_read_config8(PCI_DEV(0, 0, 4), SCRATCH_DRAM_NB_ODT);
if (val & DDR2_ODT_150ohm)
- read32(0x102200); //DDR2_ODT_150ohm
+ read32((void *)(uintptr_t)(0x102200)); //DDR2_ODT_150ohm
else
- read32(0x102020);
+ read32((void *)(uintptr_t)(0x102020));
print_spew("OK\n");
// Step 10
print_spew("SEND: ");
- read32(0x800);
+ read32((void *)(uintptr_t)(0x800));
print_spew("OK\n");
/* Step 11. Precharge all. Wait tRP. */
@@ -1035,7 +1035,7 @@ static void step_2_19(const struct mem_controller *ctrl)
// Step 12
print_spew("SEND: ");
- read32(0x0);
+ read32((void *)(uintptr_t)(0x0));
print_spew("OK\n");
/* Step 13. Perform 8 refresh cycles. Wait tRC each time. */
@@ -1046,7 +1046,7 @@ static void step_2_19(const struct mem_controller *ctrl)
// Step 16: Repeat Step 14 and 15 another 7 times
for (i = 0; i < 8; i++) {
// Step 14
- read32(0);
+ read32((void *)(uintptr_t)(0));
print_spew(".");
// Step 15
@@ -1076,7 +1076,7 @@ static void step_2_19(const struct mem_controller *ctrl)
val = pci_read_config8(MEMCTRL, 0x61);
val = val >> 6;
i |= DDR2_Twr_table[val];
- read32(i);
+ read32((void *)(uintptr_t)(i));
printk(BIOS_DEBUG, "MRS = %08x\n", i);
@@ -1085,9 +1085,9 @@ static void step_2_19(const struct mem_controller *ctrl)
// Step 19
val = pci_read_config8(PCI_DEV(0, 0, 4), SCRATCH_DRAM_NB_ODT);
if (val & DDR2_ODT_150ohm)
- read32(0x103e00); //EMRS OCD Default
+ read32((void *)(uintptr_t)(0x103e00)); //EMRS OCD Default
else
- read32(0x103c20);
+ read32((void *)(uintptr_t)(0x103c20));
}
static void sdram_set_vr(const struct mem_controller *ctrl, u8 num)
@@ -1133,45 +1133,45 @@ static void sdram_calc_size(const struct mem_controller *ctrl, u8 num)
u8 ca, ra, ba, reg;
ba = pci_read_config8(PCI_DEV(0, 0, 4), SCRATCH_FLAGS);
if (ba == 8) {
- write8(0, 0x0d);
- ra = read8(0);
- write8((1 << SDRAM1X_RA_12_8bk), 0x0c);
- ra = read8(0);
-
- write8(0, 0x0a);
- ca = read8(0);
- write8((1 << SDRAM1X_CA_09_8bk), 0x0c);
- ca = read8(0);
-
- write8(0, 0x03);
- ba = read8(0);
- write8((1 << SDRAM1X_BA2_8bk), 0x02);
- ba = read8(0);
- write8((1 << SDRAM1X_BA1_8bk), 0x01);
- ba = read8(0);
+ write8(0x0d, (void *)(uintptr_t)(0));
+ ra = read8((void *)(uintptr_t)(0));
+ write8(0x0c, (void *)(uintptr_t)((1 << SDRAM1X_RA_12_8bk)));
+ ra = read8((void *)(uintptr_t)(0));
+
+ write8(0x0a, (void *)(uintptr_t)(0));
+ ca = read8((void *)(uintptr_t)(0));
+ write8(0x0c, (void *)(uintptr_t)((1 << SDRAM1X_CA_09_8bk)));
+ ca = read8((void *)(uintptr_t)(0));
+
+ write8(0x03, (void *)(uintptr_t)(0));
+ ba = read8((void *)(uintptr_t)(0));
+ write8(0x02, (void *)(uintptr_t)((1 << SDRAM1X_BA2_8bk)));
+ ba = read8((void *)(uintptr_t)(0));
+ write8(0x01, (void *)(uintptr_t)((1 << SDRAM1X_BA1_8bk)));
+ ba = read8((void *)(uintptr_t)(0));
} else {
- write8(0, 0x0f);
- ra = read8(0);
- write8((1 << SDRAM1X_RA_14), 0x0e);
- ra = read8(0);
- write8((1 << SDRAM1X_RA_13), 0x0d);
- ra = read8(0);
- write8((1 << SDRAM1X_RA_12), 0x0c);
- ra = read8(0);
-
- write8(0, 0x0c);
- ca = read8(0);
- write8((1 << SDRAM1X_CA_12), 0x0b);
- ca = read8(0);
- write8((1 << SDRAM1X_CA_11), 0x0a);
- ca = read8(0);
- write8((1 << SDRAM1X_CA_09), 0x09);
- ca = read8(0);
-
- write8(0, 0x02);
- ba = read8(0);
- write8((1 << SDRAM1X_BA1), 0x01);
- ba = read8(0);
+ write8(0x0f, (void *)(uintptr_t)(0));
+ ra = read8((void *)(uintptr_t)(0));
+ write8(0x0e, (void *)(uintptr_t)((1 << SDRAM1X_RA_14)));
+ ra = read8((void *)(uintptr_t)(0));
+ write8(0x0d, (void *)(uintptr_t)((1 << SDRAM1X_RA_13)));
+ ra = read8((void *)(uintptr_t)(0));
+ write8(0x0c, (void *)(uintptr_t)((1 << SDRAM1X_RA_12)));
+ ra = read8((void *)(uintptr_t)(0));
+
+ write8(0x0c, (void *)(uintptr_t)(0));
+ ca = read8((void *)(uintptr_t)(0));
+ write8(0x0b, (void *)(uintptr_t)((1 << SDRAM1X_CA_12)));
+ ca = read8((void *)(uintptr_t)(0));
+ write8(0x0a, (void *)(uintptr_t)((1 << SDRAM1X_CA_11)));
+ ca = read8((void *)(uintptr_t)(0));
+ write8(0x09, (void *)(uintptr_t)((1 << SDRAM1X_CA_09)));
+ ca = read8((void *)(uintptr_t)(0));
+
+ write8(0x02, (void *)(uintptr_t)(0));
+ ba = read8((void *)(uintptr_t)(0));
+ write8(0x01, (void *)(uintptr_t)((1 << SDRAM1X_BA1)));
+ ba = read8((void *)(uintptr_t)(0));
}
if (ra < 10 || ra > 15)
@@ -1277,19 +1277,19 @@ static void sdram_enable(const struct mem_controller *ctrl)
if (reg8) {
sdram_set_vr(ctrl, i);
sdram_ending_addr(ctrl, i);
- write32(0, 0x55555555);
- write32(4, 0x55555555);
+ write32(0x55555555, (void *)(uintptr_t)(0));
+ write32(0x55555555, (void *)(uintptr_t)(4));
udelay(15);
- if (read32(0) != 0x55555555)
+ if (read32((void *)(uintptr_t)(0)) != 0x55555555)
break;
- if (read32(4) != 0x55555555)
+ if (read32((void *)(uintptr_t)(4)) != 0x55555555)
break;
- write32(0, 0xaaaaaaaa);
- write32(4, 0xaaaaaaaa);
+ write32(0xaaaaaaaa, (void *)(uintptr_t)(0));
+ write32(0xaaaaaaaa, (void *)(uintptr_t)(4));
udelay(15);
- if (read32(0) != 0xaaaaaaaa)
+ if (read32((void *)(uintptr_t)(0)) != 0xaaaaaaaa)
break;
- if (read32(4) != 0xaaaaaaaa)
+ if (read32((void *)(uintptr_t)(4)) != 0xaaaaaaaa)
break;
sdram_clear_vr_addr(ctrl, i);
}
@@ -1310,19 +1310,19 @@ static void sdram_enable(const struct mem_controller *ctrl)
sdram_set_vr(ctrl, i);
sdram_ending_addr(ctrl, i);
- write32(0, 0x55555555);
- write32(4, 0x55555555);
+ write32(0x55555555, (void *)(uintptr_t)(0));
+ write32(0x55555555, (void *)(uintptr_t)(4));
udelay(15);
- if (read32(0) != 0x55555555)
+ if (read32((void *)(uintptr_t)(0)) != 0x55555555)
break;
- if (read32(4) != 0x55555555)
+ if (read32((void *)(uintptr_t)(4)) != 0x55555555)
break;
- write32(0, 0xaaaaaaaa);
- write32(4, 0xaaaaaaaa);
+ write32(0xaaaaaaaa, (void *)(uintptr_t)(0));
+ write32(0xaaaaaaaa, (void *)(uintptr_t)(4));
udelay(15);
- if (read32(0) != 0xaaaaaaaa)
+ if (read32((void *)(uintptr_t)(0)) != 0xaaaaaaaa)
break;
- if (read32(4) != 0xaaaaaaaa)
+ if (read32((void *)(uintptr_t)(4)) != 0xaaaaaaaa)
break;
sdram_clear_vr_addr(ctrl, i);
}
@@ -1364,17 +1364,20 @@ static void sdram_enable(const struct mem_controller *ctrl)
sdram_set_vr(ctrl, i);
sdram_ending_addr(ctrl, i);
if (reg8 == 4) {
- write8(0, 0x02);
- val = read8(0);
- write8((1 << SDRAM1X_BA1), 0x01);
- val = read8(0);
+ write8(0x02, (void *)(uintptr_t)(0));
+ val = read8((void *)(uintptr_t)(0));
+ write8(0x01,
+ (void *)(uintptr_t)((1 << SDRAM1X_BA1)));
+ val = read8((void *)(uintptr_t)(0));
} else {
- write8(0, 0x03);
- val = read8(0);
- write8((1 << SDRAM1X_BA2_8bk), 0x02);
- val = read8(0);
- write8((1 << SDRAM1X_BA1_8bk), 0x01);
- val = read8(0);
+ write8(0x03, (void *)(uintptr_t)(0));
+ val = read8((void *)(uintptr_t)(0));
+ write8(0x02,
+ (void *)(uintptr_t)((1 << SDRAM1X_BA2_8bk)));
+ val = read8((void *)(uintptr_t)(0));
+ write8(0x01,
+ (void *)(uintptr_t)((1 << SDRAM1X_BA1_8bk)));
+ val = read8((void *)(uintptr_t)(0));
}
if (val < dl)
dl = val;
diff --git a/src/soc/intel/baytrail/acpi.c b/src/soc/intel/baytrail/acpi.c
index aae0c99..99fff0e 100644
--- a/src/soc/intel/baytrail/acpi.c
+++ b/src/soc/intel/baytrail/acpi.c
@@ -114,7 +114,7 @@ static int acpi_sci_irq(void)
return sci_irq;
/* Determine how SCI is routed. */
- scis = read32(actl) & SCIS_MASK;
+ scis = read32((void *)(uintptr_t)(actl)) & SCIS_MASK;
switch (scis) {
case SCIS_IRQ9:
case SCIS_IRQ10:
diff --git a/src/soc/intel/baytrail/baytrail/gpio.h b/src/soc/intel/baytrail/baytrail/gpio.h
index a431324..964f035 100644
--- a/src/soc/intel/baytrail/baytrail/gpio.h
+++ b/src/soc/intel/baytrail/baytrail/gpio.h
@@ -360,10 +360,10 @@ static inline void score_select_func(int pad, int func)
uint32_t reg;
uint32_t pconf0_addr = score_pconf0(pad);
- reg = read32(pconf0_addr);
+ reg = read32((void *)(uintptr_t)(pconf0_addr));
reg &= ~0x7;
reg |= func & 0x7;
- write32(pconf0_addr, reg);
+ write32(reg, (void *)(uintptr_t)(pconf0_addr));
}
static inline void ssus_select_func(int pad, int func)
@@ -371,10 +371,10 @@ static inline void ssus_select_func(int pad, int func)
uint32_t reg;
uint32_t pconf0_addr = ssus_pconf0(pad);
- reg = read32(pconf0_addr);
+ reg = read32((void *)(uintptr_t)(pconf0_addr));
reg &= ~0x7;
reg |= func & 0x7;
- write32(pconf0_addr, reg);
+ write32(reg, (void *)(uintptr_t)(pconf0_addr));
}
/* These functions require that the input pad be configured as an input GPIO */
@@ -382,20 +382,21 @@ static inline int score_get_gpio(int pad)
{
uint32_t val_addr = score_pconf0(pad) + PAD_VAL_REG;
- return read32(val_addr) & PAD_VAL_HIGH;
+ return read32((void *)(uintptr_t)(val_addr)) & PAD_VAL_HIGH;
}
static inline int ssus_get_gpio(int pad)
{
uint32_t val_addr = ssus_pconf0(pad) + PAD_VAL_REG;
- return read32(val_addr) & PAD_VAL_HIGH;
+ return read32((void *)(uintptr_t)(val_addr)) & PAD_VAL_HIGH;
}
static inline void ssus_disable_internal_pull(int pad)
{
const uint32_t pull_mask = ~(0xf << 7);
- write32(ssus_pconf0(pad), read32(ssus_pconf0(pad)) & pull_mask);
+ write32(read32((void *)(uintptr_t)(ssus_pconf0(pad))) & pull_mask,
+ (void *)(uintptr_t)(ssus_pconf0(pad)));
}
#endif /* _BAYTRAIL_GPIO_H_ */
diff --git a/src/soc/intel/baytrail/gfx.c b/src/soc/intel/baytrail/gfx.c
index 5650d0d..87a4e65 100644
--- a/src/soc/intel/baytrail/gfx.c
+++ b/src/soc/intel/baytrail/gfx.c
@@ -59,7 +59,7 @@ static void gfx_lock_pcbase(device_t dev)
pcbase += (gmsize-1) * wopcmsz - pcsize;
pcbase |= 1; /* Lock */
- write32(res->base + 0x182120, pcbase);
+ write32(pcbase, (void *)(uintptr_t)(res->base + 0x182120));
}
static const struct reg_script gfx_init_script[] = {
diff --git a/src/soc/intel/baytrail/gpio.c b/src/soc/intel/baytrail/gpio.c
index 43e52ef..552845d 100644
--- a/src/soc/intel/baytrail/gpio.c
+++ b/src/soc/intel/baytrail/gpio.c
@@ -142,9 +142,11 @@ static void setup_gpios(const struct soc_gpio_map *gpios,
reg, pad_conf0, config->pad_conf1, config->pad_val);
#endif
- write32(reg + PAD_CONF0_REG, pad_conf0);
- write32(reg + PAD_CONF1_REG, config->pad_conf1);
- write32(reg + PAD_VAL_REG, config->pad_val);
+ write32(pad_conf0, (void *)(uintptr_t)(reg + PAD_CONF0_REG));
+ write32(config->pad_conf1,
+ (void *)(uintptr_t)(reg + PAD_CONF1_REG));
+ write32(config->pad_val,
+ (void *)(uintptr_t)(reg + PAD_VAL_REG));
}
if (bank->legacy_base != GP_LEGACY_BASE_NONE)
@@ -206,7 +208,7 @@ static void setup_dirqs(const u8 dirq[GPIO_MAX_DIRQS],
for (i=0; i<4; ++i) {
val = dirq[i * 4 + 3] << 24 | dirq[i * 4 + 2] << 16 |
dirq[i * 4 + 1] << 8 | dirq[i * 4];
- write32(reg + i * 4, val);
+ write32(val, (void *)(uintptr_t)(reg + i * 4));
#ifdef GPIO_DEBUG
printk(BIOS_DEBUG, "Write DIRQ reg(%x) - %x\n",
reg + i * 4, val);
@@ -233,8 +235,8 @@ void setup_soc_gpios(struct soc_gpio_config *config, u8 enable_xdp_tap)
*/
if (!enable_xdp_tap) {
printk(BIOS_DEBUG, "Tri-state TDO and TMS\n");
- write32(GPSSUS_PAD_BASE + 0x2fc, 0xc);
- write32(GPSSUS_PAD_BASE + 0x2cc, 0xc);
+ write32(0xc, (void *)(uintptr_t)(GPSSUS_PAD_BASE + 0x2fc));
+ write32(0xc, (void *)(uintptr_t)(GPSSUS_PAD_BASE + 0x2cc));
}
}
diff --git a/src/soc/intel/baytrail/iosf.c b/src/soc/intel/baytrail/iosf.c
index 2b07e2b..e78ca58 100644
--- a/src/soc/intel/baytrail/iosf.c
+++ b/src/soc/intel/baytrail/iosf.c
@@ -25,11 +25,11 @@
static inline void write_iosf_reg(int reg, uint32_t value)
{
- write32(IOSF_PCI_BASE + reg, value);
+ write32(value, (void *)(uintptr_t)(IOSF_PCI_BASE + reg));
}
static inline uint32_t read_iosf_reg(int reg)
{
- return read32(IOSF_PCI_BASE + reg);
+ return read32((void *)(uintptr_t)(IOSF_PCI_BASE + reg));
}
#else
static inline void write_iosf_reg(int reg, uint32_t value)
diff --git a/src/soc/intel/baytrail/lpe.c b/src/soc/intel/baytrail/lpe.c
index 581f42b..d02bbf8 100644
--- a/src/soc/intel/baytrail/lpe.c
+++ b/src/soc/intel/baytrail/lpe.c
@@ -122,7 +122,8 @@ static void setup_codec_clock(device_t dev)
clk_reg = PMC_BASE_ADDRESS + PLT_CLK_CTL_0;
clk_reg += 4 * config->lpe_codec_clk_num;
- write32(clk_reg, (read32(clk_reg) & ~0x7) | reg);
+ write32((read32((void *)(uintptr_t)(clk_reg)) & ~0x7) | reg,
+ (void *)(uintptr_t)(clk_reg));
}
static void lpe_stash_firmware_info(device_t dev)
@@ -144,8 +145,10 @@ static void lpe_stash_firmware_info(device_t dev)
/* C0 and later steppings use an offset in the MMIO space. */
if (pattrs->stepping >= STEP_C0) {
mmio = find_resource(dev, PCI_BASE_ADDRESS_0);
- write32(mmio->base + FIRMWARE_REG_BASE_C0, res->base);
- write32(mmio->base + FIRMWARE_REG_LENGTH_C0, res->size);
+ write32(res->base,
+ (void *)(uintptr_t)(mmio->base + FIRMWARE_REG_BASE_C0));
+ write32(res->size,
+ (void *)(uintptr_t)(mmio->base + FIRMWARE_REG_LENGTH_C0));
}
}
diff --git a/src/soc/intel/baytrail/pmutil.c b/src/soc/intel/baytrail/pmutil.c
index aee3726..ceb5756 100644
--- a/src/soc/intel/baytrail/pmutil.c
+++ b/src/soc/intel/baytrail/pmutil.c
@@ -355,10 +355,11 @@ void clear_pmc_status(void)
uint32_t prsts;
uint32_t gen_pmcon1;
- prsts = read32(PMC_BASE_ADDRESS + PRSTS);
- gen_pmcon1 = read32(PMC_BASE_ADDRESS + GEN_PMCON1);
+ prsts = read32((void *)(uintptr_t)(PMC_BASE_ADDRESS + PRSTS));
+ gen_pmcon1 = read32((void *)(uintptr_t)(PMC_BASE_ADDRESS + GEN_PMCON1));
/* Clear the status bits. The RPS field is cleared on a 0 write. */
- write32(PMC_BASE_ADDRESS + GEN_PMCON1, gen_pmcon1 & ~RPS);
- write32(PMC_BASE_ADDRESS + PRSTS, prsts);
+ write32(gen_pmcon1 & ~RPS,
+ (void *)(uintptr_t)(PMC_BASE_ADDRESS + GEN_PMCON1));
+ write32(prsts, (void *)(uintptr_t)(PMC_BASE_ADDRESS + PRSTS));
}
diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c
index b69b532..b81a4b0 100644
--- a/src/soc/intel/baytrail/romstage/romstage.c
+++ b/src/soc/intel/baytrail/romstage/romstage.c
@@ -103,14 +103,15 @@ static void spi_init(void)
uint32_t reg;
/* Disable generating SMI when setting WPD bit. */
- write32(scs, read32(scs) & ~SMIWPEN);
+ write32(read32((void *)(uintptr_t)(scs)) & ~SMIWPEN,
+ (void *)(uintptr_t)(scs));
/*
* Enable caching and prefetching in the SPI controller. Disable
* the SMM-only BIOS write and set WPD bit.
*/
- reg = (read32(bcr) & ~SRC_MASK) | SRC_CACHE_PREFETCH | BCR_WPD;
+ reg = (read32((void *)(uintptr_t)(bcr)) & ~SRC_MASK) | SRC_CACHE_PREFETCH | BCR_WPD;
reg &= ~EISS;
- write32(bcr, reg);
+ write32(reg, (void *)(uintptr_t)(bcr));
}
static inline void mark_ts(struct romstage_params *rp, uint64_t ts)
@@ -190,9 +191,9 @@ static struct chipset_power_state *fill_power_state(void)
ps->gpe0_sts = inl(ACPI_BASE_ADDRESS + GPE0_STS);
ps->gpe0_en = inl(ACPI_BASE_ADDRESS + GPE0_EN);
ps->tco_sts = inl(ACPI_BASE_ADDRESS + TCO_STS);
- ps->prsts = read32(PMC_BASE_ADDRESS + PRSTS);
- ps->gen_pmcon1 = read32(PMC_BASE_ADDRESS + GEN_PMCON1);
- ps->gen_pmcon2 = read32(PMC_BASE_ADDRESS + GEN_PMCON2);
+ ps->prsts = read32((void *)(uintptr_t)(PMC_BASE_ADDRESS + PRSTS));
+ ps->gen_pmcon1 = read32((void *)(uintptr_t)(PMC_BASE_ADDRESS + GEN_PMCON1));
+ ps->gen_pmcon2 = read32((void *)(uintptr_t)(PMC_BASE_ADDRESS + GEN_PMCON2));
printk(BIOS_DEBUG, "pm1_sts: %04x pm1_en: %04x pm1_cnt: %08x\n",
ps->pm1_sts, ps->pm1_en, ps->pm1_cnt);
diff --git a/src/soc/intel/baytrail/sata.c b/src/soc/intel/baytrail/sata.c
index 28a2f8c..64de5b4 100644
--- a/src/soc/intel/baytrail/sata.c
+++ b/src/soc/intel/baytrail/sata.c
@@ -100,45 +100,45 @@ static void sata_init(struct device *dev)
pci_write_config16(dev, 0x04, reg16);
/* Set capability register */
- reg32 = read32(abar + 0x00);
+ reg32 = read32((void *)(uintptr_t)(abar + 0x00));
reg32 |= 0x0c046000; // set PSC+SSC+SALP+SSS+SAM
reg32 &= ~0x00f20060; // clear SXS+EMS+PMS+gen bits
reg32 |= (0x3 << 20); // Gen3 SATA
- write32(abar + 0x00, reg32);
+ write32(reg32, (void *)(uintptr_t)(abar + 0x00));
/* Ports enabled */
- reg32 = read32(abar + 0x0c);
+ reg32 = read32((void *)(uintptr_t)(abar + 0x0c));
reg32 &= (u32)(~0x3f);
reg32 |= config->sata_port_map;
- write32(abar + 0xc, reg32);
+ write32(reg32, (void *)(uintptr_t)(abar + 0xc));
/* Two extra reads to latch */
- read32(abar + 0x0c);
- read32(abar + 0x0c);
+ read32((void *)(uintptr_t)(abar + 0x0c));
+ read32((void *)(uintptr_t)(abar + 0x0c));
/* Set cap2 - Support devslp */
reg32 = (1 << 5) | (1 << 4) | (1 << 3);
- write32(abar + 0x24, reg32);
+ write32(reg32, (void *)(uintptr_t)(abar + 0x24));
/* Set PxCMD registers */
- reg32 = read32(abar + 0x118);
+ reg32 = read32((void *)(uintptr_t)(abar + 0x118));
reg32 &= ~((1 << 27) | (1 << 26) | (1 << 22) | (1 << 21) |
(1 << 19) | (1 << 18) | (1 << 1));
reg32 |= 2;
- write32(abar + 0x118, reg32);
+ write32(reg32, (void *)(uintptr_t)(abar + 0x118));
- reg32 = read32(abar + 0x198);
+ reg32 = read32((void *)(uintptr_t)(abar + 0x198));
reg32 &= ~((1 << 27) | (1 << 26) | (1 << 22) | (1 << 21) |
(1 << 19) | (1 << 18) | (1 << 1));
reg32 |= 2;
- write32(abar + 0x198, reg32);
+ write32(reg32, (void *)(uintptr_t)(abar + 0x198));
/* Clear reset features */
- write32(abar + 0xc8, 0);
+ write32(0, (void *)(uintptr_t)(abar + 0xc8));
/* Enable interrupts */
- reg8 = read8(abar + 0x04);
+ reg8 = read8((void *)(uintptr_t)(abar + 0x04));
reg8 |= 0x02;
- write8(abar + 0x04, reg8);
+ write8(reg8, (void *)(uintptr_t)(abar + 0x04));
} else {
/* TODO(shawnn): Configure IDE SATA speed regs */
diff --git a/src/soc/intel/baytrail/smm.c b/src/soc/intel/baytrail/smm.c
index daf759d..b819825 100644
--- a/src/soc/intel/baytrail/smm.c
+++ b/src/soc/intel/baytrail/smm.c
@@ -75,7 +75,7 @@ static void southcluster_smm_route_gpios(void)
printk(BIOS_DEBUG, "GPIO_ROUT = %08x\n", route_reg);
/* Start the routing for the specific gpios. */
- write32(gpio_rout, route_reg);
+ write32(route_reg, (void *)(uintptr_t)(gpio_rout));
/* Enable SMIs for the gpios that are set to trigger the SMI. */
for (i = 0; i < 16; i++) {
diff --git a/src/soc/intel/baytrail/southcluster.c b/src/soc/intel/baytrail/southcluster.c
index 5274b03..26a0f76 100644
--- a/src/soc/intel/baytrail/southcluster.c
+++ b/src/soc/intel/baytrail/southcluster.c
@@ -134,7 +134,7 @@ static void sc_rtc_init(void)
if (ps != NULL) {
gen_pmcon1 = ps->gen_pmcon1;
} else {
- gen_pmcon1 = read32(PMC_BASE_ADDRESS + GEN_PMCON1);
+ gen_pmcon1 = read32((void *)(uintptr_t)(PMC_BASE_ADDRESS + GEN_PMCON1));
}
rtc_fail = !!(gen_pmcon1 & RPS);
@@ -194,25 +194,28 @@ static void sc_init(device_t dev)
/* Set up the PIRQ PIC routing based on static config. */
for (i = 0; i < NUM_PIRQS; i++) {
- write8(pr_base + i*sizeof(ir->pic[i]), ir->pic[i]);
+ write8(ir->pic[i],
+ (void *)(uintptr_t)(pr_base + i * sizeof(ir->pic[i])));
}
/* Set up the per device PIRQ routing base on static config. */
for (i = 0; i < NUM_IR_DEVS; i++) {
- write16(ir_base + i*sizeof(ir->pcidev[i]), ir->pcidev[i]);
+ write16(ir->pcidev[i],
+ (void *)(uintptr_t)(ir_base + i * sizeof(ir->pcidev[i])));
}
/* Route SCI to IRQ9 */
- write32(actl, (read32(actl) & ~SCIS_MASK) | SCIS_IRQ9);
+ write32((read32((void *)(uintptr_t)(actl)) & ~SCIS_MASK) | SCIS_IRQ9,
+ (void *)(uintptr_t)(actl));
sc_rtc_init();
if (config->disable_slp_x_stretch_sus_fail) {
printk(BIOS_DEBUG, "Disabling slp_x stretching.\n");
- write32(gen_pmcon1,
- read32(gen_pmcon1) | DIS_SLP_X_STRCH_SUS_UP);
+ write32(read32((void *)(uintptr_t)(gen_pmcon1)) | DIS_SLP_X_STRCH_SUS_UP,
+ (void *)(uintptr_t)(gen_pmcon1));
} else {
- write32(gen_pmcon1,
- read32(gen_pmcon1) & ~DIS_SLP_X_STRCH_SUS_UP);
+ write32(read32((void *)(uintptr_t)(gen_pmcon1)) & ~DIS_SLP_X_STRCH_SUS_UP,
+ (void *)(uintptr_t)(gen_pmcon1));
}
if (acpi_slp_type == 3)
@@ -321,15 +324,17 @@ static void sc_disable_devfn(device_t dev)
}
if (mask != 0) {
- write32(func_dis, read32(func_dis) | mask);
+ write32(read32((void *)(uintptr_t)(func_dis)) | mask,
+ (void *)(uintptr_t)(func_dis));
/* Ensure posted write hits. */
- read32(func_dis);
+ read32((void *)(uintptr_t)(func_dis));
}
if (mask2 != 0) {
- write32(func_dis2, read32(func_dis2) | mask2);
+ write32(read32((void *)(uintptr_t)(func_dis2)) | mask2,
+ (void *)(uintptr_t)(func_dis2));
/* Ensure posted write hits. */
- read32(func_dis2);
+ read32((void *)(uintptr_t)(func_dis2));
}
}
@@ -357,7 +362,8 @@ static void hda_work_around(device_t dev)
pci_write_config32(dev, PCI_BASE_ADDRESS_0, TEMP_BASE_ADDRESS);
pci_write_config32(dev, PCI_BASE_ADDRESS_1, 0);
pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY);
- write32(gctl, read32(gctl) | 0x1);
+ write32(read32((void *)(uintptr_t)(gctl)) | 0x1,
+ (void *)(uintptr_t)(gctl));
pci_write_config8(dev, PCI_COMMAND, 0);
pci_write_config32(dev, PCI_BASE_ADDRESS_0, 0);
}
@@ -542,27 +548,32 @@ static void finalize_chipset(void *unused)
struct spi_config cfg;
/* Set the lock enable on the BIOS control register. */
- write32(bcr, read32(bcr) | BCR_LE);
+ write32(read32((void *)(uintptr_t)(bcr)) | BCR_LE,
+ (void *)(uintptr_t)(bcr));
/* Set BIOS lock down bit controlling boot block size and swapping. */
- write32(gcs, read32(gcs) | BILD);
+ write32(read32((void *)(uintptr_t)(gcs)) | BILD,
+ (void *)(uintptr_t)(gcs));
/* Lock sleep stretching policy and set SMI lock. */
- write32(gen_pmcon2, read32(gen_pmcon2) | SLPSX_STR_POL_LOCK | SMI_LOCK);
+ write32(read32((void *)(uintptr_t)(gen_pmcon2)) | SLPSX_STR_POL_LOCK | SMI_LOCK,
+ (void *)(uintptr_t)(gen_pmcon2));
/* Set the CF9 lock. */
- write32(etr, read32(etr) | CF9LOCK);
+ write32(read32((void *)(uintptr_t)(etr)) | CF9LOCK,
+ (void *)(uintptr_t)(etr));
if (mainboard_get_spi_config(&cfg) < 0) {
printk(BIOS_DEBUG, "No SPI lockdown configuration.\n");
} else {
- write16(spi + PREOP, cfg.preop);
- write16(spi + OPTYPE, cfg.optype);
- write32(spi + OPMENU0, cfg.opmenu[0]);
- write32(spi + OPMENU1, cfg.opmenu[1]);
- write16(spi + HSFSTS, read16(spi + HSFSTS) | FLOCKDN);
- write32(spi + UVSCC, cfg.uvscc);
- write32(spi + LVSCC, cfg.lvscc | VCL);
+ write16(cfg.preop, (void *)(uintptr_t)(spi + PREOP));
+ write16(cfg.optype, (void *)(uintptr_t)(spi + OPTYPE));
+ write32(cfg.opmenu[0], (void *)(uintptr_t)(spi + OPMENU0));
+ write32(cfg.opmenu[1], (void *)(uintptr_t)(spi + OPMENU1));
+ write16(read16((void *)(uintptr_t)(spi + HSFSTS)) | FLOCKDN,
+ (void *)(uintptr_t)(spi + HSFSTS));
+ write32(cfg.uvscc, (void *)(uintptr_t)(spi + UVSCC));
+ write32(cfg.lvscc | VCL, (void *)(uintptr_t)(spi + LVSCC));
}
printk(BIOS_DEBUG, "Finalizing SMM.\n");
diff --git a/src/soc/intel/baytrail/spi.c b/src/soc/intel/baytrail/spi.c
index 64aeb9b..e9b369d 100644
--- a/src/soc/intel/baytrail/spi.c
+++ b/src/soc/intel/baytrail/spi.c
@@ -171,7 +171,7 @@ enum {
static u8 readb_(const void *addr)
{
- u8 v = read8((unsigned long)addr);
+ u8 v = read8((void *)(uintptr_t)((unsigned long)addr));
printk(BIOS_DEBUG, "read %2.2x from %4.4x\n",
v, ((unsigned) addr & 0xffff) - 0xf020);
return v;
@@ -179,7 +179,7 @@ static u8 readb_(const void *addr)
static u16 readw_(const void *addr)
{
- u16 v = read16((unsigned long)addr);
+ u16 v = read16((void *)(uintptr_t)((unsigned long)addr));
printk(BIOS_DEBUG, "read %4.4x from %4.4x\n",
v, ((unsigned) addr & 0xffff) - 0xf020);
return v;
@@ -187,7 +187,7 @@ static u16 readw_(const void *addr)
static u32 readl_(const void *addr)
{
- u32 v = read32((unsigned long)addr);
+ u32 v = read32((void *)(uintptr_t)((unsigned long)addr));
printk(BIOS_DEBUG, "read %8.8x from %4.4x\n",
v, ((unsigned) addr & 0xffff) - 0xf020);
return v;
@@ -195,33 +195,33 @@ static u32 readl_(const void *addr)
static void writeb_(u8 b, const void *addr)
{
- write8((unsigned long)addr, b);
+ write8(b, (void *)(uintptr_t)((unsigned long)addr));
printk(BIOS_DEBUG, "wrote %2.2x to %4.4x\n",
b, ((unsigned) addr & 0xffff) - 0xf020);
}
static void writew_(u16 b, const void *addr)
{
- write16((unsigned long)addr, b);
+ write16(b, (void *)(uintptr_t)((unsigned long)addr));
printk(BIOS_DEBUG, "wrote %4.4x to %4.4x\n",
b, ((unsigned) addr & 0xffff) - 0xf020);
}
static void writel_(u32 b, const void *addr)
{
- write32((unsigned long)addr, b);
+ write32(b, (void *)(uintptr_t)((unsigned long)addr));
printk(BIOS_DEBUG, "wrote %8.8x to %4.4x\n",
b, ((unsigned) addr & 0xffff) - 0xf020);
}
#else /* CONFIG_DEBUG_SPI_FLASH ^^^ enabled vvv NOT enabled */
-#define readb_(a) read8((uint32_t)a)
-#define readw_(a) read16((uint32_t)a)
-#define readl_(a) read32((uint32_t)a)
-#define writeb_(val, addr) write8((uint32_t)addr, val)
-#define writew_(val, addr) write16((uint32_t)addr, val)
-#define writel_(val, addr) write32((uint32_t)addr, val)
+#define readb_(a) read8((void *)(uintptr_t)((uint32_t)a))
+#define readw_(a) read16((void *)(uintptr_t)((uint32_t)a))
+#define readl_(a) read32((void *)(uintptr_t)((uint32_t)a))
+#define writeb_(val, addr) write8(val, (void *)(uintptr_t)((uint32_t)addr))
+#define writew_(val, addr) write16(val, (void *)(uintptr_t)((uint32_t)addr))
+#define writel_(val, addr) write32(val, (void *)(uintptr_t)((uint32_t)addr))
#endif /* CONFIG_DEBUG_SPI_FLASH ^^^ NOT enabled */
diff --git a/src/soc/intel/broadwell/adsp.c b/src/soc/intel/broadwell/adsp.c
index 2a6dc17..c635a5b 100644
--- a/src/soc/intel/broadwell/adsp.c
+++ b/src/soc/intel/broadwell/adsp.c
@@ -58,7 +58,8 @@ static void adsp_init(struct device *dev)
* SNOOP_REQ[13]=1b SNOOP_SCALE[12:10]=100b (1ms) SNOOP_VAL[9:0]=3h
*/
tmp32 = pch_is_wpt() ? ADSP_SHIM_BASE_WPT : ADSP_SHIM_BASE_LPT;
- write32(bar0->base + tmp32 + ADSP_SHIM_LTRC, ADSP_SHIM_LTRC_VALUE);
+ write32(ADSP_SHIM_LTRC_VALUE,
+ (void *)(uintptr_t)(bar0->base + tmp32 + ADSP_SHIM_LTRC));
/* Program VDRTCTL2 D19:F0:A8[31:0] = 0x00000fff */
pci_write_config32(dev, ADSP_PCI_VDRTCTL2, ADSP_VDRTCTL2_VALUE);
@@ -115,9 +116,9 @@ static void adsp_init(struct device *dev)
ADSP_PCICFGCTL_ACPIIE);
/* Put ADSP in D3hot */
- tmp32 = read32(bar1->base + PCH_PCS);
+ tmp32 = read32((void *)(uintptr_t)(bar1->base + PCH_PCS));
tmp32 |= PCH_PCS_PS_D3HOT;
- write32(bar1->base + PCH_PCS, tmp32);
+ write32(tmp32, (void *)(uintptr_t)(bar1->base + PCH_PCS));
} else {
printk(BIOS_INFO, "ADSP: Enable PCI Mode IRQ23\n");
diff --git a/src/soc/intel/broadwell/hda.c b/src/soc/intel/broadwell/hda.c
index 80caa2c..ba0291e 100644
--- a/src/soc/intel/broadwell/hda.c
+++ b/src/soc/intel/broadwell/hda.c
@@ -96,9 +96,9 @@ static void hda_pch_init(struct device *dev, u32 base)
reg8 &= ~(1 << 7); // Docking not supported
pci_write_config8(dev, 0x4d, reg8);
- reg16 = read32(base + 0x0012);
+ reg16 = read32((void *)(uintptr_t)(base + 0x0012));
reg16 |= (1 << 0);
- write32(base + 0x0012, reg16);
+ write32(reg16, (void *)(uintptr_t)(base + 0x0012));
/* disable Auto Voltage Detector */
reg8 = pci_read_config8(dev, 0x42);
diff --git a/src/soc/intel/broadwell/igd.c b/src/soc/intel/broadwell/igd.c
index b429758..535bc5a 100644
--- a/src/soc/intel/broadwell/igd.c
+++ b/src/soc/intel/broadwell/igd.c
@@ -245,14 +245,14 @@ static struct resource *gtt_res = NULL;
static unsigned long gtt_read(unsigned long reg)
{
u32 val;
- val = read32(gtt_res->base + reg);
+ val = read32((void *)(uintptr_t)(gtt_res->base + reg));
return val;
}
static void gtt_write(unsigned long reg, unsigned long data)
{
- write32(gtt_res->base + reg, data);
+ write32(data, (void *)(uintptr_t)(gtt_res->base + reg));
}
static inline void gtt_rmw(u32 reg, u32 andmask, u32 ormask)
diff --git a/src/soc/intel/broadwell/me.c b/src/soc/intel/broadwell/me.c
index 2bdb1ed..0243acb 100644
--- a/src/soc/intel/broadwell/me.c
+++ b/src/soc/intel/broadwell/me.c
@@ -103,7 +103,7 @@ static void mei_dump(void *ptr, int dword, int offset, const char *type)
static inline void mei_read_dword_ptr(void *ptr, int offset)
{
- u32 dword = read32(mei_base_address + offset);
+ u32 dword = read32((void *)(uintptr_t)(mei_base_address + offset));
memcpy(ptr, &dword, sizeof(dword));
mei_dump(ptr, dword, offset, "READ");
}
@@ -112,7 +112,7 @@ static inline void mei_write_dword_ptr(void *ptr, int offset)
{
u32 dword = 0;
memcpy(&dword, ptr, sizeof(dword));
- write32(mei_base_address + offset, dword);
+ write32(dword, (void *)(uintptr_t)(mei_base_address + offset));
mei_dump(ptr, dword, offset, "WRITE");
}
@@ -140,13 +140,13 @@ static inline void read_me_csr(struct mei_csr *csr)
static inline void write_cb(u32 dword)
{
- write32(mei_base_address + MEI_H_CB_WW, dword);
+ write32(dword, (void *)(uintptr_t)(mei_base_address + MEI_H_CB_WW));
mei_dump(NULL, dword, MEI_H_CB_WW, "WRITE");
}
static inline u32 read_cb(void)
{
- u32 dword = read32(mei_base_address + MEI_ME_CB_RW);
+ u32 dword = read32((void *)(uintptr_t)(mei_base_address + MEI_ME_CB_RW));
mei_dump(NULL, dword, MEI_ME_CB_RW, "READ");
return dword;
}
diff --git a/src/soc/intel/broadwell/minihd.c b/src/soc/intel/broadwell/minihd.c
index 43aeec2..5df125e 100644
--- a/src/soc/intel/broadwell/minihd.c
+++ b/src/soc/intel/broadwell/minihd.c
@@ -84,15 +84,15 @@ static void minihd_init(struct device *dev)
pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER);
/* Mini-HD configuration */
- reg32 = read32(base + 0x100c);
+ reg32 = read32((void *)(uintptr_t)(base + 0x100c));
reg32 &= 0xfffc0000;
reg32 |= 0x4;
- write32(base + 0x100c, reg32);
+ write32(reg32, (void *)(uintptr_t)(base + 0x100c));
- reg32 = read32(base + 0x1010);
+ reg32 = read32((void *)(uintptr_t)(base + 0x1010));
reg32 &= 0xfffc0000;
reg32 |= 0x4b;
- write32(base + 0x1010, reg32);
+ write32(reg32, (void *)(uintptr_t)(base + 0x1010));
/* Init the codec and write the verb table */
codec_mask = hda_codec_detect(base);
diff --git a/src/soc/intel/broadwell/sata.c b/src/soc/intel/broadwell/sata.c
index e8d1fbe..b5fa559 100644
--- a/src/soc/intel/broadwell/sata.c
+++ b/src/soc/intel/broadwell/sata.c
@@ -111,19 +111,19 @@ static void sata_init(struct device *dev)
printk(BIOS_DEBUG, "ABAR: %08X\n", abar);
/* CAP (HBA Capabilities) : enable power management */
- reg32 = read32(abar + 0x00);
+ reg32 = read32((void *)(uintptr_t)(abar + 0x00));
reg32 |= 0x0c006000; // set PSC+SSC+SALP+SSS
reg32 &= ~0x00020060; // clear SXS+EMS+PMS
reg32 |= (1 << 18); // SAM: SATA AHCI MODE ONLY
- write32(abar + 0x00, reg32);
+ write32(reg32, (void *)(uintptr_t)(abar + 0x00));
/* PI (Ports implemented) */
- write32(abar + 0x0c, config->sata_port_map);
- (void) read32(abar + 0x0c); /* Read back 1 */
- (void) read32(abar + 0x0c); /* Read back 2 */
+ write32(config->sata_port_map, (void *)(uintptr_t)(abar + 0x0c));
+ (void) read32((void *)(uintptr_t)(abar + 0x0c)); /* Read back 1 */
+ (void) read32((void *)(uintptr_t)(abar + 0x0c)); /* Read back 2 */
/* CAP2 (HBA Capabilities Extended)*/
- reg32 = read32(abar + 0x24);
+ reg32 = read32((void *)(uintptr_t)(abar + 0x24));
/*
* Static Power Gating for unused ports
@@ -142,7 +142,7 @@ static void sata_init(struct device *dev)
reg32 &= ~(1 << 3);
else
reg32 |= (1 << 5)|(1 << 4)|(1 << 3)|(1 << 2);
- write32(abar + 0x24, reg32);
+ write32(reg32, (void *)(uintptr_t)(abar + 0x24));
/* Set Gen3 Transmitter settings if needed */
if (config->sata_port0_gen3_tx)
diff --git a/src/soc/intel/broadwell/serialio.c b/src/soc/intel/broadwell/serialio.c
index e2b17af..8d90428 100644
--- a/src/soc/intel/broadwell/serialio.c
+++ b/src/soc/intel/broadwell/serialio.c
@@ -37,9 +37,9 @@
/* Set D3Hot Power State in ACPI mode */
static void serialio_enable_d3hot(struct resource *res)
{
- u32 reg32 = read32(res->base + PCH_PCS);
+ u32 reg32 = read32((void *)(uintptr_t)(res->base + PCH_PCS));
reg32 |= PCH_PCS_PS_D3HOT;
- write32(res->base + PCH_PCS, reg32);
+ write32(reg32, (void *)(uintptr_t)(res->base + PCH_PCS));
}
static int serialio_uart_is_debug(struct device *dev)
@@ -58,9 +58,9 @@ static int serialio_uart_is_debug(struct device *dev)
/* Enable clock in PCI mode */
static void serialio_enable_clock(struct resource *bar0)
{
- u32 reg32 = read32(bar0->base + SIO_REG_PPR_CLOCK);
+ u32 reg32 = read32((void *)(uintptr_t)(bar0->base + SIO_REG_PPR_CLOCK));
reg32 |= SIO_REG_PPR_CLOCK_EN;
- write32(bar0->base + SIO_REG_PPR_CLOCK, reg32);
+ write32(reg32, (void *)(uintptr_t)(bar0->base + SIO_REG_PPR_CLOCK));
}
/* Put Serial IO D21:F0-F6 device into desired mode. */
@@ -111,22 +111,22 @@ static void serialio_d21_ltr(struct resource *bar0)
u32 reg;
/* 1. Program BAR0 + 808h[2] = 0b */
- reg = read32(bar0->base + SIO_REG_PPR_GEN);
+ reg = read32((void *)(uintptr_t)(bar0->base + SIO_REG_PPR_GEN));
reg &= ~SIO_REG_PPR_GEN_LTR_MODE_MASK;
- write32(bar0->base + SIO_REG_PPR_GEN, reg);
+ write32(reg, (void *)(uintptr_t)(bar0->base + SIO_REG_PPR_GEN));
/* 2. Program BAR0 + 804h[1:0] = 00b */
- reg = read32(bar0->base + SIO_REG_PPR_RST);
+ reg = read32((void *)(uintptr_t)(bar0->base + SIO_REG_PPR_RST));
reg &= ~SIO_REG_PPR_RST_ASSERT;
- write32(bar0->base + SIO_REG_PPR_RST, reg);
+ write32(reg, (void *)(uintptr_t)(bar0->base + SIO_REG_PPR_RST));
/* 3. Program BAR0 + 804h[1:0] = 11b */
- reg = read32(bar0->base + SIO_REG_PPR_RST);
+ reg = read32((void *)(uintptr_t)(bar0->base + SIO_REG_PPR_RST));
reg |= SIO_REG_PPR_RST_ASSERT;
- write32(bar0->base + SIO_REG_PPR_RST, reg);
+ write32(reg, (void *)(uintptr_t)(bar0->base + SIO_REG_PPR_RST));
/* 4. Program BAR0 + 814h[31:0] = 00000000h */
- write32(bar0->base + SIO_REG_AUTO_LTR, 0);
+ write32(0, (void *)(uintptr_t)(bar0->base + SIO_REG_AUTO_LTR));
}
/* Enable LTR Auto Mode for D23:F0. */
@@ -135,26 +135,26 @@ static void serialio_d23_ltr(struct resource *bar0)
u32 reg;
/* Program BAR0 + 1008h[2] = 1b */
- reg = read32(bar0->base + SIO_REG_SDIO_PPR_GEN);
+ reg = read32((void *)(uintptr_t)(bar0->base + SIO_REG_SDIO_PPR_GEN));
reg |= SIO_REG_PPR_GEN_LTR_MODE_MASK;
- write32(bar0->base + SIO_REG_SDIO_PPR_GEN, reg);
+ write32(reg, (void *)(uintptr_t)(bar0->base + SIO_REG_SDIO_PPR_GEN));
/* Program BAR0 + 1010h = 0x00000000 */
- write32(bar0->base + SIO_REG_SDIO_PPR_SW_LTR, 0);
+ write32(0, (void *)(uintptr_t)(bar0->base + SIO_REG_SDIO_PPR_SW_LTR));
/* Program BAR0 + 3Ch[30] = 1b */
- reg = read32(bar0->base + SIO_REG_SDIO_PPR_CMD12);
+ reg = read32((void *)(uintptr_t)(bar0->base + SIO_REG_SDIO_PPR_CMD12));
reg |= SIO_REG_SDIO_PPR_CMD12_B30;
- write32(bar0->base + SIO_REG_SDIO_PPR_CMD12, reg);
+ write32(reg, (void *)(uintptr_t)(bar0->base + SIO_REG_SDIO_PPR_CMD12));
}
/* Select I2C voltage of 1.8V or 3.3V. */
static void serialio_i2c_voltage_sel(struct resource *bar0, u8 voltage)
{
- u32 reg32 = read32(bar0->base + SIO_REG_PPR_GEN);
+ u32 reg32 = read32((void *)(uintptr_t)(bar0->base + SIO_REG_PPR_GEN));
reg32 &= ~SIO_REG_PPR_GEN_VOLTAGE_MASK;
reg32 |= SIO_REG_PPR_GEN_VOLTAGE(voltage);
- write32(bar0->base + SIO_REG_PPR_GEN, reg32);
+ write32(reg32, (void *)(uintptr_t)(bar0->base + SIO_REG_PPR_GEN));
}
/* Init sequence to be run once, done as part of D21:F0 (SDMA) init. */
diff --git a/src/soc/intel/broadwell/spi.c b/src/soc/intel/broadwell/spi.c
index 935c532..03def0c 100644
--- a/src/soc/intel/broadwell/spi.c
+++ b/src/soc/intel/broadwell/spi.c
@@ -170,7 +170,7 @@ enum {
static u8 readb_(const void *addr)
{
- u8 v = read8((unsigned long)addr);
+ u8 v = read8((void *)(uintptr_t)((unsigned long)addr));
printk(BIOS_DEBUG, "read %2.2x from %4.4x\n",
v, ((unsigned) addr & 0xffff) - 0xf020);
return v;
@@ -178,7 +178,7 @@ static u8 readb_(const void *addr)
static u16 readw_(const void *addr)
{
- u16 v = read16((unsigned long)addr);
+ u16 v = read16((void *)(uintptr_t)((unsigned long)addr));
printk(BIOS_DEBUG, "read %4.4x from %4.4x\n",
v, ((unsigned) addr & 0xffff) - 0xf020);
return v;
@@ -186,7 +186,7 @@ static u16 readw_(const void *addr)
static u32 readl_(const void *addr)
{
- u32 v = read32((unsigned long)addr);
+ u32 v = read32((void *)(uintptr_t)((unsigned long)addr));
printk(BIOS_DEBUG, "read %8.8x from %4.4x\n",
v, ((unsigned) addr & 0xffff) - 0xf020);
return v;
@@ -194,33 +194,33 @@ static u32 readl_(const void *addr)
static void writeb_(u8 b, const void *addr)
{
- write8((unsigned long)addr, b);
+ write8(b, (void *)(uintptr_t)((unsigned long)addr));
printk(BIOS_DEBUG, "wrote %2.2x to %4.4x\n",
b, ((unsigned) addr & 0xffff) - 0xf020);
}
static void writew_(u16 b, const void *addr)
{
- write16((unsigned long)addr, b);
+ write16(b, (void *)(uintptr_t)((unsigned long)addr));
printk(BIOS_DEBUG, "wrote %4.4x to %4.4x\n",
b, ((unsigned) addr & 0xffff) - 0xf020);
}
static void writel_(u32 b, const void *addr)
{
- write32((unsigned long)addr, b);
+ write32(b, (void *)(uintptr_t)((unsigned long)addr));
printk(BIOS_DEBUG, "wrote %8.8x to %4.4x\n",
b, ((unsigned) addr & 0xffff) - 0xf020);
}
#else /* CONFIG_DEBUG_SPI_FLASH ^^^ enabled vvv NOT enabled */
-#define readb_(a) read8((uint32_t)a)
-#define readw_(a) read16((uint32_t)a)
-#define readl_(a) read32((uint32_t)a)
-#define writeb_(val, addr) write8((uint32_t)addr, val)
-#define writew_(val, addr) write16((uint32_t)addr, val)
-#define writel_(val, addr) write32((uint32_t)addr, val)
+#define readb_(a) read8((void *)(uintptr_t)((uint32_t)a))
+#define readw_(a) read16((void *)(uintptr_t)((uint32_t)a))
+#define readl_(a) read32((void *)(uintptr_t)((uint32_t)a))
+#define writeb_(val, addr) write8(val, (void *)(uintptr_t)((uint32_t)addr))
+#define writew_(val, addr) write16(val, (void *)(uintptr_t)((uint32_t)addr))
+#define writel_(val, addr) write32(val, (void *)(uintptr_t)((uint32_t)addr))
#endif /* CONFIG_DEBUG_SPI_FLASH ^^^ NOT enabled */
diff --git a/src/soc/intel/broadwell/usbdebug.c b/src/soc/intel/broadwell/usbdebug.c
index d462e89..51cf50f 100644
--- a/src/soc/intel/broadwell/usbdebug.c
+++ b/src/soc/intel/broadwell/usbdebug.c
@@ -45,7 +45,8 @@ void enable_usbdebug(unsigned int port)
pci_write_config8(PCH_DEV_EHCI, PCI_COMMAND, PCI_COMMAND_MEMORY);
/* Force ownership of the Debug Port to the EHCI controller. */
- tmp32 = read32(CONFIG_EHCI_BAR + CONFIG_EHCI_DEBUG_OFFSET);
+ tmp32 = read32((void *)(uintptr_t)(CONFIG_EHCI_BAR + CONFIG_EHCI_DEBUG_OFFSET));
tmp32 |= (1 << 30);
- write32(CONFIG_EHCI_BAR + CONFIG_EHCI_DEBUG_OFFSET, tmp32);
+ write32(tmp32,
+ (void *)(uintptr_t)(CONFIG_EHCI_BAR + CONFIG_EHCI_DEBUG_OFFSET));
}
diff --git a/src/soc/intel/broadwell/xhci.c b/src/soc/intel/broadwell/xhci.c
index 89e1139..96061b9 100644
--- a/src/soc/intel/broadwell/xhci.c
+++ b/src/soc/intel/broadwell/xhci.c
@@ -47,18 +47,19 @@ static int usb_xhci_port_count_usb3(device_t dev)
static void usb_xhci_reset_status_usb3(u32 mem_base, int port)
{
u32 portsc = mem_base + XHCI_USB3_PORTSC(port);
- u32 status = read32(portsc);
+ u32 status = read32((void *)(uintptr_t)(portsc));
/* Do not set Port Enabled/Disabled field */
status &= ~XHCI_USB3_PORTSC_PED;
/* Clear all change status bits */
status |= XHCI_USB3_PORTSC_CHST;
- write32(portsc, status);
+ write32(status, (void *)(uintptr_t)(portsc));
}
static void usb_xhci_reset_port_usb3(u32 mem_base, int port)
{
u32 portsc = mem_base + XHCI_USB3_PORTSC(port);
- write32(portsc, read32(portsc) | XHCI_USB3_PORTSC_WPR);
+ write32(read32((void *)(uintptr_t)(portsc)) | XHCI_USB3_PORTSC_WPR,
+ (void *)(uintptr_t)(portsc));
}
#define XHCI_RESET_DELAY_US 1000 /* 1ms */
@@ -92,7 +93,7 @@ static void usb_xhci_reset_usb3(device_t dev, int all)
if (port_disabled & (1 << port))
continue;
/* Read port link status field */
- status = read32(mem_base + XHCI_USB3_PORTSC(port));
+ status = read32((void *)(uintptr_t)(mem_base + XHCI_USB3_PORTSC(port)));
status &= XHCI_USB3_PORTSC_PLS;
if (status == XHCI_PLSR_POLLING)
complete = 0;
@@ -109,7 +110,7 @@ static void usb_xhci_reset_usb3(device_t dev, int all)
/* Skip disabled ports */
if (port_disabled & (1 << port))
continue;
- status = read32(portsc) & XHCI_USB3_PORTSC_PLS;
+ status = read32((void *)(uintptr_t)(portsc)) & XHCI_USB3_PORTSC_PLS;
/* Reset all or only disconnected ports */
if (all || (status == XHCI_PLSR_RXDETECT ||
status == XHCI_PLSR_POLLING))
@@ -126,7 +127,7 @@ static void usb_xhci_reset_usb3(device_t dev, int all)
if (port_disabled & (1 << port))
continue;
/* Check if warm reset is complete */
- status = read32(mem_base + XHCI_USB3_PORTSC(port));
+ status = read32((void *)(uintptr_t)(mem_base + XHCI_USB3_PORTSC(port)));
if (!(status & XHCI_USB3_PORTSC_WRC))
complete = 0;
}
@@ -163,17 +164,17 @@ void usb_xhci_sleep_prepare(device_t dev, u8 slp_typ)
pci_write_config32(dev, 0xb0, reg32);
/* Clear MMIO 0x816c[14,2] */
- reg32 = read32(mem_base + 0x816c);
+ reg32 = read32((void *)(uintptr_t)(mem_base + 0x816c));
reg32 &= ~((1 << 14) | (1 << 2));
- write32(mem_base + 0x816c, reg32);
+ write32(reg32, (void *)(uintptr_t)(mem_base + 0x816c));
/* Reset disconnected USB3 ports */
usb_xhci_reset_usb3(dev, 0);
/* Set MMIO 0x80e0[15] */
- reg32 = read32(mem_base + 0x80e0);
+ reg32 = read32((void *)(uintptr_t)(mem_base + 0x80e0));
reg32 |= (1 << 15);
- write32(mem_base + 0x80e0, reg32);
+ write32(reg32, (void *)(uintptr_t)(mem_base + 0x80e0));
/* Set D3Hot state and enable PME */
pci_or_config16(dev, XHCI_PWR_CTL_STS, XHCI_PWR_CTL_SET_D3);
diff --git a/src/soc/intel/common/hda_verb.c b/src/soc/intel/common/hda_verb.c
index 6404ee2..ee54f40 100644
--- a/src/soc/intel/common/hda_verb.c
+++ b/src/soc/intel/common/hda_verb.c
@@ -34,10 +34,10 @@ static int set_bits(u32 port, u32 mask, u32 val)
/* Write (val & mask) to port */
val &= mask;
- reg32 = read32(port);
+ reg32 = read32((void *)(uintptr_t)(port));
reg32 &= ~mask;
reg32 |= val;
- write32(port, reg32);
+ write32(reg32, (void *)(uintptr_t)(port));
/* Wait for readback of register to
* match what was just written to it
@@ -46,7 +46,7 @@ static int set_bits(u32 port, u32 mask, u32 val)
do {
/* Wait 1ms based on BKDG wait time */
mdelay(1);
- reg32 = read32(port);
+ reg32 = read32((void *)(uintptr_t)(port));
reg32 &= mask;
} while ((reg32 != val) && --count);
@@ -68,10 +68,11 @@ int hda_codec_detect(u32 base)
goto no_codec;
/* Write back the value once reset bit is set. */
- write16(base + HDA_GCAP_REG, read16(base + HDA_GCAP_REG));
+ write16(read16((void *)(uintptr_t)(base + HDA_GCAP_REG)),
+ (void *)(uintptr_t)(base + HDA_GCAP_REG));
/* Read in Codec location (BAR + 0xe)[2..0]*/
- reg8 = read8(base + HDA_STATESTS_REG);
+ reg8 = read8((void *)(uintptr_t)(base + HDA_STATESTS_REG));
reg8 &= 0x0f;
if (!reg8)
goto no_codec;
@@ -98,7 +99,7 @@ static int hda_wait_for_ready(u32 base)
int timeout = 50;
while(timeout--) {
- u32 reg32 = read32(base + HDA_ICII_REG);
+ u32 reg32 = read32((void *)(uintptr_t)(base + HDA_ICII_REG));
if (!(reg32 & HDA_ICII_BUSY))
return 0;
udelay(1);
@@ -117,16 +118,16 @@ static int hda_wait_for_valid(u32 base)
u32 reg32;
/* Send the verb to the codec */
- reg32 = read32(base + HDA_ICII_REG);
+ reg32 = read32((void *)(uintptr_t)(base + HDA_ICII_REG));
reg32 |= HDA_ICII_BUSY | HDA_ICII_VALID;
- write32(base + HDA_ICII_REG, reg32);
+ write32(reg32, (void *)(uintptr_t)(base + HDA_ICII_REG));
/* Use a 50 usec timeout - the Linux kernel uses the
* same duration */
int timeout = 50;
while(timeout--) {
- reg32 = read32(base + HDA_ICII_REG);
+ reg32 = read32((void *)(uintptr_t)(base + HDA_ICII_REG));
if ((reg32 & (HDA_ICII_VALID | HDA_ICII_BUSY)) ==
HDA_ICII_VALID)
return 0;
@@ -192,7 +193,7 @@ int hda_codec_write(u32 base, u32 size, const u32 *data)
if (hda_wait_for_ready(base) < 0)
return -1;
- write32(base + HDA_IC_REG, data[i]);
+ write32(data[i], (void *)(uintptr_t)(base + HDA_IC_REG));
if (hda_wait_for_valid(base) < 0)
return -1;
@@ -224,7 +225,7 @@ int hda_codec_init(u32 base, int addr, int verb_size, const u32 *verb_data)
}
reg32 = (addr << 28) | 0x000f0000;
- write32(base + HDA_IC_REG, reg32);
+ write32(reg32, (void *)(uintptr_t)(base + HDA_IC_REG));
if (hda_wait_for_valid(base) < 0) {
printk(BIOS_DEBUG, " codec not valid.\n");
@@ -232,7 +233,7 @@ int hda_codec_init(u32 base, int addr, int verb_size, const u32 *verb_data)
}
/* 2 */
- reg32 = read32(base + HDA_IR_REG);
+ reg32 = read32((void *)(uintptr_t)(base + HDA_IR_REG));
printk(BIOS_DEBUG, "HDA: codec viddid: %08x\n", reg32);
size = hda_find_verb(verb_size, verb_data, reg32, &verb);
diff --git a/src/soc/intel/fsp_baytrail/acpi.c b/src/soc/intel/fsp_baytrail/acpi.c
index fb0dc87..870486d 100644
--- a/src/soc/intel/fsp_baytrail/acpi.c
+++ b/src/soc/intel/fsp_baytrail/acpi.c
@@ -113,7 +113,7 @@ static int acpi_sci_irq(void)
return sci_irq;
/* Determine how SCI is routed. */
- scis = read32(actl) & SCIS_MASK;
+ scis = read32((void *)(uintptr_t)(actl)) & SCIS_MASK;
switch (scis) {
case SCIS_IRQ9:
case SCIS_IRQ10:
diff --git a/src/soc/intel/fsp_baytrail/baytrail/gpio.h b/src/soc/intel/fsp_baytrail/baytrail/gpio.h
index 957b0de..70371c7 100644
--- a/src/soc/intel/fsp_baytrail/baytrail/gpio.h
+++ b/src/soc/intel/fsp_baytrail/baytrail/gpio.h
@@ -347,10 +347,10 @@ static inline void score_select_func(int pad, int func)
uint32_t reg;
uint32_t pconf0_addr = score_pconf0(pad);
- reg = read32(pconf0_addr);
+ reg = read32((void *)(uintptr_t)(pconf0_addr));
reg &= ~0x7;
reg |= func & 0x7;
- write32(pconf0_addr, reg);
+ write32(reg, (void *)(uintptr_t)(pconf0_addr));
}
static inline void ssus_select_func(int pad, int func)
@@ -358,10 +358,10 @@ static inline void ssus_select_func(int pad, int func)
uint32_t reg;
uint32_t pconf0_addr = ssus_pconf0(pad);
- reg = read32(pconf0_addr);
+ reg = read32((void *)(uintptr_t)(pconf0_addr));
reg &= ~0x7;
reg |= func & 0x7;
- write32(pconf0_addr, reg);
+ write32(reg, (void *)(uintptr_t)(pconf0_addr));
}
/* These functions require that the input pad be configured as an input GPIO */
@@ -369,20 +369,21 @@ static inline int score_get_gpio(int pad)
{
uint32_t val_addr = score_pconf0(pad) + PAD_VAL_REG;
- return read32(val_addr) & PAD_VAL_HIGH;
+ return read32((void *)(uintptr_t)(val_addr)) & PAD_VAL_HIGH;
}
static inline int ssus_get_gpio(int pad)
{
uint32_t val_addr = ssus_pconf0(pad) + PAD_VAL_REG;
- return read32(val_addr) & PAD_VAL_HIGH;
+ return read32((void *)(uintptr_t)(val_addr)) & PAD_VAL_HIGH;
}
static inline void ssus_disable_internal_pull(int pad)
{
const uint32_t pull_mask = ~(0xf << 7);
- write32(ssus_pconf0(pad), read32(ssus_pconf0(pad)) & pull_mask);
+ write32(read32((void *)(uintptr_t)(ssus_pconf0(pad))) & pull_mask,
+ (void *)(uintptr_t)(ssus_pconf0(pad)));
}
#endif /* _BAYTRAIL_GPIO_H_ */
diff --git a/src/soc/intel/fsp_baytrail/bootblock/bootblock.c b/src/soc/intel/fsp_baytrail/bootblock/bootblock.c
index 1623f04..b55a50e 100644
--- a/src/soc/intel/fsp_baytrail/bootblock/bootblock.c
+++ b/src/soc/intel/fsp_baytrail/bootblock/bootblock.c
@@ -64,7 +64,8 @@ static void enable_spi_prefetch(void)
{
uint32_t bcr = SPI_BASE_ADDRESS + BCR;
/* Enable caching and prefetching in the SPI controller. */
- write32(bcr, (read32(bcr) & ~SRC_MASK) | SRC_CACHE_PREFETCH);
+ write32((read32((void *)(uintptr_t)(bcr)) & ~SRC_MASK) | SRC_CACHE_PREFETCH,
+ (void *)(uintptr_t)(bcr));
}
static void enable_rom_caching(void)
diff --git a/src/soc/intel/fsp_baytrail/gpio.c b/src/soc/intel/fsp_baytrail/gpio.c
index c12c937..4fb0389 100644
--- a/src/soc/intel/fsp_baytrail/gpio.c
+++ b/src/soc/intel/fsp_baytrail/gpio.c
@@ -142,9 +142,11 @@ static void setup_gpios(const struct soc_gpio_map *gpios,
reg, pad_conf0, config->pad_conf1, config->pad_val);
#endif
- write32(reg + PAD_CONF0_REG, pad_conf0);
- write32(reg + PAD_CONF1_REG, config->pad_conf1);
- write32(reg + PAD_VAL_REG, config->pad_val);
+ write32(pad_conf0, (void *)(uintptr_t)(reg + PAD_CONF0_REG));
+ write32(config->pad_conf1,
+ (void *)(uintptr_t)(reg + PAD_CONF1_REG));
+ write32(config->pad_val,
+ (void *)(uintptr_t)(reg + PAD_VAL_REG));
}
if (bank->legacy_base != GP_LEGACY_BASE_NONE)
@@ -209,7 +211,7 @@ static void setup_dirqs(const u8 dirq[GPIO_MAX_DIRQS],
for (i=0; i<4; ++i) {
val = dirq[i * 4 + 3] << 24 | dirq[i * 4 + 2] << 16 |
dirq[i * 4 + 1] << 8 | dirq[i * 4];
- write32(reg + i * 4, val);
+ write32(val, (void *)(uintptr_t)(reg + i * 4));
#ifdef GPIO_DEBUG
printk(BIOS_DEBUG, "Write DIRQ reg(%x) - %x\n",
reg + i * 4, val);
diff --git a/src/soc/intel/fsp_baytrail/iosf.c b/src/soc/intel/fsp_baytrail/iosf.c
index f892b20..4ff33a0 100644
--- a/src/soc/intel/fsp_baytrail/iosf.c
+++ b/src/soc/intel/fsp_baytrail/iosf.c
@@ -29,11 +29,11 @@
static inline void write_iosf_reg(int reg, uint32_t value)
{
- write32(IOSF_PCI_BASE + reg, value);
+ write32(value, (void *)(uintptr_t)(IOSF_PCI_BASE + reg));
}
static inline uint32_t read_iosf_reg(int reg)
{
- return read32(IOSF_PCI_BASE + reg);
+ return read32((void *)(uintptr_t)(IOSF_PCI_BASE + reg));
}
#else
static inline void write_iosf_reg(int reg, uint32_t value)
diff --git a/src/soc/intel/fsp_baytrail/pmutil.c b/src/soc/intel/fsp_baytrail/pmutil.c
index aee3726..ceb5756 100644
--- a/src/soc/intel/fsp_baytrail/pmutil.c
+++ b/src/soc/intel/fsp_baytrail/pmutil.c
@@ -355,10 +355,11 @@ void clear_pmc_status(void)
uint32_t prsts;
uint32_t gen_pmcon1;
- prsts = read32(PMC_BASE_ADDRESS + PRSTS);
- gen_pmcon1 = read32(PMC_BASE_ADDRESS + GEN_PMCON1);
+ prsts = read32((void *)(uintptr_t)(PMC_BASE_ADDRESS + PRSTS));
+ gen_pmcon1 = read32((void *)(uintptr_t)(PMC_BASE_ADDRESS + GEN_PMCON1));
/* Clear the status bits. The RPS field is cleared on a 0 write. */
- write32(PMC_BASE_ADDRESS + GEN_PMCON1, gen_pmcon1 & ~RPS);
- write32(PMC_BASE_ADDRESS + PRSTS, prsts);
+ write32(gen_pmcon1 & ~RPS,
+ (void *)(uintptr_t)(PMC_BASE_ADDRESS + GEN_PMCON1));
+ write32(prsts, (void *)(uintptr_t)(PMC_BASE_ADDRESS + PRSTS));
}
diff --git a/src/soc/intel/fsp_baytrail/romstage/romstage.c b/src/soc/intel/fsp_baytrail/romstage/romstage.c
index 259ecdc..5cb3811 100644
--- a/src/soc/intel/fsp_baytrail/romstage/romstage.c
+++ b/src/soc/intel/fsp_baytrail/romstage/romstage.c
@@ -57,7 +57,7 @@ uint32_t chipset_prev_sleep_state(uint32_t clear)
/* Read Power State */
pm1_sts = inw(ACPI_BASE_ADDRESS + PM1_STS);
pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT);
- gen_pmcon1 = read32(PMC_BASE_ADDRESS + GEN_PMCON1);
+ gen_pmcon1 = read32((void *)(uintptr_t)(PMC_BASE_ADDRESS + GEN_PMCON1));
printk(BIOS_DEBUG, "PM1_STS = 0x%x PM1_CNT = 0x%x GEN_PMCON1 = 0x%x\n",
pm1_sts, pm1_cnt, gen_pmcon1);
@@ -124,20 +124,21 @@ static void spi_init(void)
uint32_t reg;
/* Disable generating SMI when setting WPD bit. */
- write32(scs, read32(scs) & ~SMIWPEN);
+ write32(read32((void *)(uintptr_t)(scs)) & ~SMIWPEN,
+ (void *)(uintptr_t)(scs));
/*
* Enable caching and prefetching in the SPI controller. Disable
* the SMM-only BIOS write and set WPD bit.
*/
- reg = (read32(bcr) & ~SRC_MASK) | SRC_CACHE_PREFETCH | BCR_WPD;
+ reg = (read32((void *)(uintptr_t)(bcr)) & ~SRC_MASK) | SRC_CACHE_PREFETCH | BCR_WPD;
reg &= ~EISS;
- write32(bcr, reg);
+ write32(reg, (void *)(uintptr_t)(bcr));
}
static void baytrail_rtc_init(void)
{
uint32_t pbase = pci_read_config32(LPC_BDF, PBASE) & 0xfffffff0;
- uint32_t gen_pmcon1 = read32(pbase + GEN_PMCON1);
+ uint32_t gen_pmcon1 = read32((void *)(uintptr_t)(pbase + GEN_PMCON1));
int rtc_failed = !!(gen_pmcon1 & RPS);
if (rtc_failed) {
@@ -145,7 +146,8 @@ static void baytrail_rtc_init(void)
"RTC Failure detected. Resetting Date to %s\n",
coreboot_dmi_date);
- write32(DEFAULT_PBASE + GEN_PMCON1, gen_pmcon1 & ~RPS);
+ write32(gen_pmcon1 & ~RPS,
+ (void *)(uintptr_t)(DEFAULT_PBASE + GEN_PMCON1));
}
cmos_init(rtc_failed);
@@ -186,15 +188,17 @@ void main(FSP_INFO_HEADER *fsp_info_header)
get_func_disables(&fd_mask, &fd2_mask);
if (fd_mask != 0) {
- write32(func_dis, read32(func_dis) | fd_mask);
+ write32(read32((void *)(uintptr_t)(func_dis)) | fd_mask,
+ (void *)(uintptr_t)(func_dis));
/* Ensure posted write hits. */
- read32(func_dis);
+ read32((void *)(uintptr_t)(func_dis));
}
if (fd2_mask != 0) {
- write32(func_dis2, read32(func_dis2) | fd2_mask);
+ write32(read32((void *)(uintptr_t)(func_dis2)) | fd2_mask,
+ (void *)(uintptr_t)(func_dis2));
/* Ensure posted write hits. */
- read32(func_dis2);
+ read32((void *)(uintptr_t)(func_dis2));
}
post_code(0x47);
diff --git a/src/soc/intel/fsp_baytrail/smm.c b/src/soc/intel/fsp_baytrail/smm.c
index d4b3d58..6488553 100644
--- a/src/soc/intel/fsp_baytrail/smm.c
+++ b/src/soc/intel/fsp_baytrail/smm.c
@@ -76,7 +76,7 @@ static void southcluster_smm_route_gpios(void)
printk(BIOS_DEBUG, "GPIO_ROUT = %08x\n", route_reg);
/* Start the routing for the specific gpios. */
- write32(gpio_rout, route_reg);
+ write32(route_reg, (void *)(uintptr_t)(gpio_rout));
/* Enable SMIs for the gpios that are set to trigger the SMI. */
for (i = 0; i < 16; i++) {
diff --git a/src/soc/intel/fsp_baytrail/southcluster.c b/src/soc/intel/fsp_baytrail/southcluster.c
index d87935b..55ecab3 100644
--- a/src/soc/intel/fsp_baytrail/southcluster.c
+++ b/src/soc/intel/fsp_baytrail/southcluster.c
@@ -90,9 +90,9 @@ static void sc_enable_ioapic(struct device *dev)
* Enable ACPI I/O and power management.
* Set SCI IRQ to IRQ9
*/
- write32(ilb_base + ILB_OIC, 0x100); /* AEN */
- reg32 = read32(ilb_base + ILB_OIC); /* Read back per BWG */
- write32(ilb_base + ILB_ACTL, 0); /* ACTL bit 2:0 SCIS IRQ9 */
+ write32(0x100, (void *)(uintptr_t)(ilb_base + ILB_OIC)); /* AEN */
+ reg32 = read32((void *)(uintptr_t)(ilb_base + ILB_OIC)); /* Read back per BWG */
+ write32(0, (void *)(uintptr_t)(ilb_base + ILB_ACTL)); /* ACTL bit 2:0 SCIS IRQ9 */
*ioapic_index = 0;
*ioapic_data = (1 << 25);
@@ -141,8 +141,10 @@ static void sc_enable_serial_irqs(struct device *dev)
reg8 |= (1 << 3); /* IOCHK# NMI Disable for now */
outb(reg8, 0x61);
- write32(ibase + ILB_OIC, read32(ibase + ILB_OIC) | SIRQEN);
- write8(ibase + ILB_SERIRQ_CNTL, SCNT_CONTINUOUS_MODE);
+ write32(read32((void *)(uintptr_t)(ibase + ILB_OIC)) | SIRQEN,
+ (void *)(uintptr_t)(ibase + ILB_OIC));
+ write8(SCNT_CONTINUOUS_MODE,
+ (void *)(uintptr_t)(ibase + ILB_SERIRQ_CNTL));
#if !IS_ENABLED(CONFIG_SERIRQ_CONTINUOUS_MODE)
/*
@@ -151,7 +153,7 @@ static void sc_enable_serial_irqs(struct device *dev)
* it into quiet mode operation.
*/
outb(0x00, 0xED); /* I/O Delay to get the 1 frame */
- write8(ibase + ILB_SERIRQ_CNTL, SCNT_QUIET_MODE);
+ write8(SCNT_QUIET_MODE, (void *)(uintptr_t)(ibase + ILB_SERIRQ_CNTL));
#endif
#endif /* DON'T SET UP IRQS */
}
@@ -269,7 +271,8 @@ static void sc_pirq_init(device_t dev)
"PIRQ\tA \tB \tC \tD \tE \tF \tG \tH\n"
"IRQ ");
for (i = 0; i < NUM_PIRQS; i++) {
- write8(pr_base + i*sizeof(ir->pic[i]), ir->pic[i]);
+ write8(ir->pic[i],
+ (void *)(uintptr_t)(pr_base + i * sizeof(ir->pic[i])));
printk(BIOS_SPEW, "\t%d", ir->pic[i]);
}
printk(BIOS_SPEW, "\n\n");
@@ -278,7 +281,8 @@ static void sc_pirq_init(device_t dev)
printk(BIOS_SPEW, "\t\t\tPIRQ[A-H] routed to each INT_PIN[A-D]\n"
"Dev\tINTA (IRQ)\tINTB (IRQ)\tINTC (IRQ)\tINTD (IRQ)\n");
for (i = 0; i < NUM_OF_PCI_DEVS; i++) {
- write16(ir_base + i*sizeof(ir->pcidev[i]), ir->pcidev[i]);
+ write16(ir->pcidev[i],
+ (void *)(uintptr_t)(ir_base + i * sizeof(ir->pcidev[i])));
/* If the entry is more than just 0, print it out */
if(ir->pcidev[i]) {
@@ -292,7 +296,8 @@ static void sc_pirq_init(device_t dev)
}
/* Route SCI to IRQ9 */
- write32(actl, (read32(actl) & ~SCIS_MASK) | SCIS_IRQ9);
+ write32((read32((void *)(uintptr_t)(actl)) & ~SCIS_MASK) | SCIS_IRQ9,
+ (void *)(uintptr_t)(actl));
printk(BIOS_SPEW, "Finished writing IRQ assignments\n");
/* Write IRQ assignments to PCI config space */
@@ -378,7 +383,7 @@ static void sc_init(struct device *dev)
ibase = pci_read_config32(dev, IBASE) & ~0xF;
- write8(ibase + ILB_MC, 0);
+ write8(0, (void *)(uintptr_t)(ibase + ILB_MC));
/* Set the value for PCI command register. */
pci_write_config16(dev, PCI_COMMAND,
@@ -445,15 +450,17 @@ static void sc_disable_devfn(device_t dev)
}
if (fd_mask != 0) {
- write32(func_dis, read32(func_dis) | fd_mask);
+ write32(read32((void *)(uintptr_t)(func_dis)) | fd_mask,
+ (void *)(uintptr_t)(func_dis));
/* Ensure posted write hits. */
- read32(func_dis);
+ read32((void *)(uintptr_t)(func_dis));
}
if (fd2_mask != 0) {
- write32(func_dis2, read32(func_dis2) | fd2_mask);
+ write32(read32((void *)(uintptr_t)(func_dis2)) | fd2_mask,
+ (void *)(uintptr_t)(func_dis2));
/* Ensure posted write hits. */
- read32(func_dis2);
+ read32((void *)(uintptr_t)(func_dis2));
}
}
@@ -481,7 +488,8 @@ static void hda_work_around(device_t dev)
pci_write_config32(dev, PCI_BASE_ADDRESS_0, TEMP_BASE_ADDRESS);
pci_write_config32(dev, PCI_BASE_ADDRESS_1, 0);
pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY);
- write32(gctl, read32(gctl) | 0x1);
+ write32(read32((void *)(uintptr_t)(gctl)) | 0x1,
+ (void *)(uintptr_t)(gctl));
pci_write_config8(dev, PCI_COMMAND, 0);
pci_write_config32(dev, PCI_BASE_ADDRESS_0, 0);
}
diff --git a/src/soc/intel/fsp_baytrail/spi.c b/src/soc/intel/fsp_baytrail/spi.c
index 0c3c63d..b0921e3 100644
--- a/src/soc/intel/fsp_baytrail/spi.c
+++ b/src/soc/intel/fsp_baytrail/spi.c
@@ -169,7 +169,7 @@ enum {
static u8 readb_(const void *addr)
{
- u8 v = read8((unsigned long)addr);
+ u8 v = read8((void *)(uintptr_t)((unsigned long)addr));
printk(BIOS_DEBUG, "read %2.2x from %4.4x\n",
v, ((unsigned) addr & 0xffff) - 0xf020);
return v;
@@ -177,7 +177,7 @@ static u8 readb_(const void *addr)
static u16 readw_(const void *addr)
{
- u16 v = read16((unsigned long)addr);
+ u16 v = read16((void *)(uintptr_t)((unsigned long)addr));
printk(BIOS_DEBUG, "read %4.4x from %4.4x\n",
v, ((unsigned) addr & 0xffff) - 0xf020);
return v;
@@ -185,7 +185,7 @@ static u16 readw_(const void *addr)
static u32 readl_(const void *addr)
{
- u32 v = read32((unsigned long)addr);
+ u32 v = read32((void *)(uintptr_t)((unsigned long)addr));
printk(BIOS_DEBUG, "read %8.8x from %4.4x\n",
v, ((unsigned) addr & 0xffff) - 0xf020);
return v;
@@ -193,33 +193,33 @@ static u32 readl_(const void *addr)
static void writeb_(u8 b, const void *addr)
{
- write8((unsigned long)addr, b);
+ write8(b, (void *)(uintptr_t)((unsigned long)addr));
printk(BIOS_DEBUG, "wrote %2.2x to %4.4x\n",
b, ((unsigned) addr & 0xffff) - 0xf020);
}
static void writew_(u16 b, const void *addr)
{
- write16((unsigned long)addr, b);
+ write16(b, (void *)(uintptr_t)((unsigned long)addr));
printk(BIOS_DEBUG, "wrote %4.4x to %4.4x\n",
b, ((unsigned) addr & 0xffff) - 0xf020);
}
static void writel_(u32 b, const void *addr)
{
- write32((unsigned long)addr, b);
+ write32(b, (void *)(uintptr_t)((unsigned long)addr));
printk(BIOS_DEBUG, "wrote %8.8x to %4.4x\n",
b, ((unsigned) addr & 0xffff) - 0xf020);
}
#else /* CONFIG_DEBUG_SPI_FLASH ^^^ enabled vvv NOT enabled */
-#define readb_(a) read8((uint32_t)a)
-#define readw_(a) read16((uint32_t)a)
-#define readl_(a) read32((uint32_t)a)
-#define writeb_(val, addr) write8((uint32_t)addr, val)
-#define writew_(val, addr) write16((uint32_t)addr, val)
-#define writel_(val, addr) write32((uint32_t)addr, val)
+#define readb_(a) read8((void *)(uintptr_t)((uint32_t)a))
+#define readw_(a) read16((void *)(uintptr_t)((uint32_t)a))
+#define readl_(a) read32((void *)(uintptr_t)((uint32_t)a))
+#define writeb_(val, addr) write8(val, (void *)(uintptr_t)((uint32_t)addr))
+#define writew_(val, addr) write16(val, (void *)(uintptr_t)((uint32_t)addr))
+#define writel_(val, addr) write32(val, (void *)(uintptr_t)((uint32_t)addr))
#endif /* CONFIG_DEBUG_SPI_FLASH ^^^ NOT enabled */
diff --git a/src/southbridge/amd/agesa/hudson/enable_usbdebug.c b/src/southbridge/amd/agesa/hudson/enable_usbdebug.c
index 258267e..e9ba23d 100644
--- a/src/southbridge/amd/agesa/hudson/enable_usbdebug.c
+++ b/src/southbridge/amd/agesa/hudson/enable_usbdebug.c
@@ -44,11 +44,12 @@ void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port)
u32 reg32;
/* Write the port number to DEBUGPORT_MISC_CONTROL[31:28]. */
- reg32 = read32(base_regs + DEBUGPORT_MISC_CONTROL);
+ reg32 = read32((void *)(uintptr_t)(base_regs + DEBUGPORT_MISC_CONTROL));
reg32 &= ~(0xf << 28);
reg32 |= (port << 28);
reg32 |= (1 << 27); /* Enable Debug Port port number remapping. */
- write32(base_regs + DEBUGPORT_MISC_CONTROL, reg32);
+ write32(reg32,
+ (void *)(uintptr_t)(base_regs + DEBUGPORT_MISC_CONTROL));
}
diff --git a/src/southbridge/amd/agesa/hudson/hudson.c b/src/southbridge/amd/agesa/hudson/hudson.c
index d5f11dc..d9dc987 100644
--- a/src/southbridge/amd/agesa/hudson/hudson.c
+++ b/src/southbridge/amd/agesa/hudson/hudson.c
@@ -64,22 +64,22 @@ void backup_top_of_ram(uint64_t ramtop)
void pm_write8(u8 reg, u8 value)
{
- write8(PM_MMIO_BASE + reg, value);
+ write8(value, (void *)(uintptr_t)(PM_MMIO_BASE + reg));
}
u8 pm_read8(u8 reg)
{
- return read8(PM_MMIO_BASE + reg);
+ return read8((void *)(uintptr_t)(PM_MMIO_BASE + reg));
}
void pm_write16(u8 reg, u16 value)
{
- write16(PM_MMIO_BASE + reg, value);
+ write16(value, (void *)(uintptr_t)(PM_MMIO_BASE + reg));
}
u16 pm_read16(u16 reg)
{
- return read16(PM_MMIO_BASE + reg);
+ return read16((void *)(uintptr_t)(PM_MMIO_BASE + reg));
}
#define PM_REG_USB_ENABLE 0xef
diff --git a/src/southbridge/amd/agesa/hudson/imc.c b/src/southbridge/amd/agesa/hudson/imc.c
index d706292..cf3cc3b 100644
--- a/src/southbridge/amd/agesa/hudson/imc.c
+++ b/src/southbridge/amd/agesa/hudson/imc.c
@@ -31,18 +31,18 @@ void imc_reg_init(void)
{
/* Init Power Management Block 2 (PM2) Registers.
* Check BKDG for AMD Family 16h for details. */
- write8(ACPI_MMIO_BASE + PMIO2_BASE + 0x00, 0x06);
- write8(ACPI_MMIO_BASE + PMIO2_BASE + 0x01, 0x06);
- write8(ACPI_MMIO_BASE + PMIO2_BASE + 0x02, 0xf7);
- write8(ACPI_MMIO_BASE + PMIO2_BASE + 0x03, 0xff);
- write8(ACPI_MMIO_BASE + PMIO2_BASE + 0x04, 0xff);
+ write8(0x06, (void *)(uintptr_t)(ACPI_MMIO_BASE + PMIO2_BASE + 0x00));
+ write8(0x06, (void *)(uintptr_t)(ACPI_MMIO_BASE + PMIO2_BASE + 0x01));
+ write8(0xf7, (void *)(uintptr_t)(ACPI_MMIO_BASE + PMIO2_BASE + 0x02));
+ write8(0xff, (void *)(uintptr_t)(ACPI_MMIO_BASE + PMIO2_BASE + 0x03));
+ write8(0xff, (void *)(uintptr_t)(ACPI_MMIO_BASE + PMIO2_BASE + 0x04));
#if !CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE
- write8(ACPI_MMIO_BASE + PMIO2_BASE + 0x10, 0x06);
- write8(ACPI_MMIO_BASE + PMIO2_BASE + 0x11, 0x06);
- write8(ACPI_MMIO_BASE + PMIO2_BASE + 0x12, 0xf7);
- write8(ACPI_MMIO_BASE + PMIO2_BASE + 0x13, 0xff);
- write8(ACPI_MMIO_BASE + PMIO2_BASE + 0x14, 0xff);
+ write8(0x06, (void *)(uintptr_t)(ACPI_MMIO_BASE + PMIO2_BASE + 0x10));
+ write8(0x06, (void *)(uintptr_t)(ACPI_MMIO_BASE + PMIO2_BASE + 0x11));
+ write8(0xf7, (void *)(uintptr_t)(ACPI_MMIO_BASE + PMIO2_BASE + 0x12));
+ write8(0xff, (void *)(uintptr_t)(ACPI_MMIO_BASE + PMIO2_BASE + 0x13));
+ write8(0xff, (void *)(uintptr_t)(ACPI_MMIO_BASE + PMIO2_BASE + 0x14));
#endif
#if CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE
diff --git a/src/southbridge/amd/agesa/hudson/smi.h b/src/southbridge/amd/agesa/hudson/smi.h
index 53da00a..96f03dc 100644
--- a/src/southbridge/amd/agesa/hudson/smi.h
+++ b/src/southbridge/amd/agesa/hudson/smi.h
@@ -36,22 +36,22 @@ enum smi_lvl {
static inline uint32_t smi_read32(uint8_t offset)
{
- return read32(SMI_BASE + offset);
+ return read32((void *)(uintptr_t)(SMI_BASE + offset));
}
static inline void smi_write32(uint8_t offset, uint32_t value)
{
- write32(SMI_BASE + offset, value);
+ write32(value, (void *)(uintptr_t)(SMI_BASE + offset));
}
static inline uint16_t smi_read16(uint8_t offset)
{
- return read16(SMI_BASE + offset);
+ return read16((void *)(uintptr_t)(SMI_BASE + offset));
}
static inline void smi_write16(uint8_t offset, uint16_t value)
{
- write16(SMI_BASE + offset, value);
+ write16(value, (void *)(uintptr_t)(SMI_BASE + offset));
}
void hudson_configure_gevent_smi(uint8_t gevent, uint8_t mode, uint8_t level);
diff --git a/src/southbridge/amd/agesa/hudson/spi.c b/src/southbridge/amd/agesa/hudson/spi.c
index 735ab7e..290ed4b 100644
--- a/src/southbridge/amd/agesa/hudson/spi.c
+++ b/src/southbridge/amd/agesa/hudson/spi.c
@@ -53,12 +53,12 @@ static u32 spibar;
static inline uint8_t spi_read(uint8_t reg)
{
- return read8(spibar + reg);
+ return read8((void *)(uintptr_t)(spibar + reg));
}
static inline void spi_write(uint8_t reg, uint8_t val)
{
- write8(spibar + reg, val);
+ write8(val, (void *)(uintptr_t)(spibar + reg));
}
static void reset_internal_fifo_pointer(void)
diff --git a/src/southbridge/amd/amd8111/nic.c b/src/southbridge/amd/amd8111/nic.c
index 5352705..ad1aee2 100644
--- a/src/southbridge/amd/amd8111/nic.c
+++ b/src/southbridge/amd/amd8111/nic.c
@@ -54,12 +54,13 @@ static void nic_init(struct device *dev)
/* Hard Reset PHY */
printk(BIOS_DEBUG, "Resetting PHY... ");
if (conf->phy_lowreset) {
- write32((mmio + CMD3), VAL0 | PHY_RST_POL | RESET_PHY);
+ write32(VAL0 | PHY_RST_POL | RESET_PHY,
+ (void *)(uintptr_t)((mmio + CMD3)));
} else {
- write32((mmio + CMD3), VAL0 | RESET_PHY);
+ write32(VAL0 | RESET_PHY, (void *)(uintptr_t)((mmio + CMD3)));
}
mdelay(15);
- write32((mmio + CMD3), RESET_PHY);
+ write32(RESET_PHY, (void *)(uintptr_t)((mmio + CMD3)));
printk(BIOS_DEBUG, "Done\n");
}
diff --git a/src/southbridge/amd/cimx/sb800/spi.c b/src/southbridge/amd/cimx/sb800/spi.c
index c84eee2..47a2187 100644
--- a/src/southbridge/amd/cimx/sb800/spi.c
+++ b/src/southbridge/amd/cimx/sb800/spi.c
@@ -40,15 +40,17 @@ static u32 spibar;
static void reset_internal_fifo_pointer(void)
{
do {
- write8(spibar + 2, read8(spibar + 2) | 0x10);
- } while (read8(spibar + 0xD) & 0x7);
+ write8(read8((void *)(uintptr_t)(spibar + 2)) | 0x10,
+ (void *)(uintptr_t)(spibar + 2));
+ } while (read8((void *)(uintptr_t)(spibar + 0xD)) & 0x7);
}
static void execute_command(void)
{
- write8(spibar + 2, read8(spibar + 2) | 1);
+ write8(read8((void *)(uintptr_t)(spibar + 2)) | 1,
+ (void *)(uintptr_t)(spibar + 2));
- while ((read8(spibar + 2) & 1) && (read8(spibar+3) & 0x80));
+ while ((read8((void *)(uintptr_t)(spibar + 2)) & 1) && (read8((void *)(uintptr_t)(spibar + 3)) & 0x80));
}
void spi_init()
@@ -91,12 +93,12 @@ int spi_xfer(struct spi_slave *slave, const void *dout,
readoffby1 = bytesout ? 0 : 1;
readwrite = (bytesin + readoffby1) << 4 | bytesout;
- write8(spibar + 1, readwrite);
- write8(spibar + 0, cmd);
+ write8(readwrite, (void *)(uintptr_t)(spibar + 1));
+ write8(cmd, (void *)(uintptr_t)(spibar + 0));
reset_internal_fifo_pointer();
for (count = 0; count < bytesout; count++, dout++) {
- write8(spibar + 0x0C, *(u8 *)dout);
+ write8(*(u8 *)dout, (void *)(uintptr_t)(spibar + 0x0C));
}
reset_internal_fifo_pointer();
@@ -105,12 +107,12 @@ int spi_xfer(struct spi_slave *slave, const void *dout,
reset_internal_fifo_pointer();
/* Skip the bytes we sent. */
for (count = 0; count < bytesout; count++) {
- cmd = read8(spibar + 0x0C);
+ cmd = read8((void *)(uintptr_t)(spibar + 0x0C));
}
reset_internal_fifo_pointer();
for (count = 0; count < bytesin; count++, din++) {
- *(u8 *)din = read8(spibar + 0x0C);
+ *(u8 *)din = read8((void *)(uintptr_t)(spibar + 0x0C));
}
return 0;
diff --git a/src/southbridge/amd/cs5530/vga.c b/src/southbridge/amd/cs5530/vga.c
index 66ab239..7ef8ed4 100644
--- a/src/southbridge/amd/cs5530/vga.c
+++ b/src/southbridge/amd/cs5530/vga.c
@@ -244,27 +244,27 @@ static void cs5530_set_clock_frequency(u32 io_base, unsigned long pll_val)
unsigned long reg;
/* disable the PLL first, reset and power it down */
- reg = read32(io_base+CS5530_DOT_CLK_CONFIG) & ~0x20;
+ reg = read32((void *)(uintptr_t)(io_base + CS5530_DOT_CLK_CONFIG)) & ~0x20;
reg |= 0x80000100;
- write32(io_base+CS5530_DOT_CLK_CONFIG, reg);
+ write32(reg, (void *)(uintptr_t)(io_base + CS5530_DOT_CLK_CONFIG));
/* write the new PLL setting */
reg |= (pll_val & ~0x80000920);
- write32(io_base+CS5530_DOT_CLK_CONFIG, reg);
+ write32(reg, (void *)(uintptr_t)(io_base + CS5530_DOT_CLK_CONFIG));
mdelay(1); /* wait for control voltage to be 0V */
/* enable the PLL */
reg |= 0x00000800;
- write32(io_base+CS5530_DOT_CLK_CONFIG, reg);
+ write32(reg, (void *)(uintptr_t)(io_base + CS5530_DOT_CLK_CONFIG));
/* clear reset */
reg &= ~0x80000000;
- write32(io_base+CS5530_DOT_CLK_CONFIG, reg);
+ write32(reg, (void *)(uintptr_t)(io_base + CS5530_DOT_CLK_CONFIG));
/* clear bypass */
reg &= ~0x00000100;
- write32(io_base+CS5530_DOT_CLK_CONFIG, reg);
+ write32(reg, (void *)(uintptr_t)(io_base + CS5530_DOT_CLK_CONFIG));
}
/**
@@ -288,15 +288,17 @@ static void dc_setup_layout(u32 gx_base, const struct video_mode *mode)
{
u32 base = 0x00000000;
- write32(gx_base + DC_FB_ST_OFFSET, base);
+ write32(base, (void *)(uintptr_t)(gx_base + DC_FB_ST_OFFSET));
base += (COLOUR_DEPTH>>3) * mode->visible_pixel * mode->visible_lines;
- write32(gx_base + DC_CB_ST_OFFSET, base);
- write32(gx_base + DC_CURS_ST_OFFSET, base);
- write32(gx_base + DC_VID_ST_OFFSET, base);
- write32(gx_base + DC_LINE_DELTA, ((COLOUR_DEPTH>>3) * mode->visible_pixel) >> 2);
- write32(gx_base + DC_BUF_SIZE, ((COLOUR_DEPTH>>3) * mode->visible_pixel) >> 3);
+ write32(base, (void *)(uintptr_t)(gx_base + DC_CB_ST_OFFSET));
+ write32(base, (void *)(uintptr_t)(gx_base + DC_CURS_ST_OFFSET));
+ write32(base, (void *)(uintptr_t)(gx_base + DC_VID_ST_OFFSET));
+ write32(((COLOUR_DEPTH >> 3) * mode->visible_pixel) >> 2,
+ (void *)(uintptr_t)(gx_base + DC_LINE_DELTA));
+ write32(((COLOUR_DEPTH >> 3) * mode->visible_pixel) >> 3,
+ (void *)(uintptr_t)(gx_base + DC_BUF_SIZE));
}
/**
@@ -345,20 +347,28 @@ static void dc_setup_timing(u32 gx_base, const struct video_mode *mode)
vtotal = vblankend;
/* row description */
- write32(gx_base + DC_H_TIMING_1, (hactive - 1) | ((htotal - 1) << 16));
+ write32((hactive - 1) | ((htotal - 1) << 16),
+ (void *)(uintptr_t)(gx_base + DC_H_TIMING_1));
/* horizontal blank description */
- write32(gx_base + DC_H_TIMING_2, (hblankstart - 1) | ((hblankend - 1) << 16));
+ write32((hblankstart - 1) | ((hblankend - 1) << 16),
+ (void *)(uintptr_t)(gx_base + DC_H_TIMING_2));
/* horizontal sync description */
- write32(gx_base + DC_H_TIMING_3, (hsyncstart - 1) | ((hsyncend - 1) << 16));
- write32(gx_base + DC_FP_H_TIMING, (hsyncstart - 1) | ((hsyncend - 1) << 16));
+ write32((hsyncstart - 1) | ((hsyncend - 1) << 16),
+ (void *)(uintptr_t)(gx_base + DC_H_TIMING_3));
+ write32((hsyncstart - 1) | ((hsyncend - 1) << 16),
+ (void *)(uintptr_t)(gx_base + DC_FP_H_TIMING));
/* line description */
- write32(gx_base + DC_V_TIMING_1, (vactive - 1) | ((vtotal - 1) << 16));
+ write32((vactive - 1) | ((vtotal - 1) << 16),
+ (void *)(uintptr_t)(gx_base + DC_V_TIMING_1));
/* vertical blank description */
- write32(gx_base + DC_V_TIMING_2, (vblankstart - 1) | ((vblankend - 1) << 16));
+ write32((vblankstart - 1) | ((vblankend - 1) << 16),
+ (void *)(uintptr_t)(gx_base + DC_V_TIMING_2));
/* vertical sync description */
- write32(gx_base + DC_V_TIMING_3, (vsyncstart - 1) | ((vsyncend - 1) << 16));
- write32(gx_base + DC_FP_V_TIMING, (vsyncstart - 2) | ((vsyncend - 2) << 16));
+ write32((vsyncstart - 1) | ((vsyncend - 1) << 16),
+ (void *)(uintptr_t)(gx_base + DC_V_TIMING_3));
+ write32((vsyncstart - 2) | ((vsyncend - 2) << 16),
+ (void *)(uintptr_t)(gx_base + DC_FP_V_TIMING));
}
/**
@@ -371,14 +381,14 @@ static void dc_setup_timing(u32 gx_base, const struct video_mode *mode)
*/
static void cs5530_activate_mode(u32 gx_base, const struct video_mode *mode)
{
- write32(gx_base + DC_GENERAL_CFG, 0x00000080);
+ write32(0x00000080, (void *)(uintptr_t)(gx_base + DC_GENERAL_CFG));
mdelay(1);
dc_setup_layout(gx_base,mode);
dc_setup_timing(gx_base,mode);
- write32(gx_base + DC_GENERAL_CFG, 0x2000C581);
- write32(gx_base + DC_TIMING_CFG, 0x0000002F);
- write32(gx_base + DC_OUTPUT_CFG, 0x00003004);
+ write32(0x2000C581, (void *)(uintptr_t)(gx_base + DC_GENERAL_CFG));
+ write32(0x0000002F, (void *)(uintptr_t)(gx_base + DC_TIMING_CFG));
+ write32(0x00003004, (void *)(uintptr_t)(gx_base + DC_OUTPUT_CFG));
}
/**
@@ -394,7 +404,8 @@ static void cs5530_activate_video(u32 io_base, const struct video_mode *mode)
u32 val;
val = (u32)mode->sync_pol << 8;
- write32(io_base + CS5530_DISPLAY_CONFIG, val | 0x0020002F);
+ write32(val | 0x0020002F,
+ (void *)(uintptr_t)(io_base + CS5530_DISPLAY_CONFIG));
}
#if CONFIG_SPLASH_GRAPHIC
@@ -467,7 +478,7 @@ static void cs5530_vga_init(device_t dev)
cs5530_set_clock_frequency(io_base, mode->pll_value);
- write32(gx_base + DC_UNLOCK, DC_UNLOCK_MAGIC);
+ write32(DC_UNLOCK_MAGIC, (void *)(uintptr_t)(gx_base + DC_UNLOCK));
show_boot_splash_16(mode->visible_pixel, mode->visible_lines,
mode->visible_pixel * (COLOUR_DEPTH>>3), (void*)(GX_BASE + 0x800000));
@@ -475,7 +486,7 @@ static void cs5530_vga_init(device_t dev)
cs5530_activate_mode(gx_base, mode);
cs5530_activate_video(io_base, mode);
- write32(gx_base + DC_UNLOCK, 0x00000000);
+ write32(0x00000000, (void *)(uintptr_t)(gx_base + DC_UNLOCK));
}
static struct device_operations vga_ops = {
diff --git a/src/southbridge/amd/cs5536/cs5536.c b/src/southbridge/amd/cs5536/cs5536.c
index 1f7eab8..73d5850 100644
--- a/src/southbridge/amd/cs5536/cs5536.c
+++ b/src/southbridge/amd/cs5536/cs5536.c
@@ -448,10 +448,11 @@ static void enable_USB_port4(struct southbridge_amd_cs5536_config *sb)
bar = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
/* Make HCCPARAMS writeable */
- write32(bar + IPREG04, read32(bar + IPREG04) | USB_HCCPW_SET);
+ write32(read32((void *)(uintptr_t)(bar + IPREG04)) | USB_HCCPW_SET,
+ (void *)(uintptr_t)(bar + IPREG04));
/* ; EECP=50h, IST=01h, ASPC=1 */
- write32(bar + HCCPARAMS, 0x00005012);
+ write32(0x00005012, (void *)(uintptr_t)(bar + HCCPARAMS));
}
dev = dev_find_device(PCI_VENDOR_ID_AMD,
@@ -459,19 +460,22 @@ static void enable_USB_port4(struct southbridge_amd_cs5536_config *sb)
if (dev) {
bar = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
- write32(bar + UOCMUX, read32(bar + UOCMUX) & PUEN_SET);
+ write32(read32((void *)(uintptr_t)(bar + UOCMUX)) & PUEN_SET,
+ (void *)(uintptr_t)(bar + UOCMUX));
/* Host or Device? */
if (sb->enable_USBP4_device) {
- write32(bar + UOCMUX, read32(bar + UOCMUX) | PMUX_DEVICE);
+ write32(read32((void *)(uintptr_t)(bar + UOCMUX)) | PMUX_DEVICE,
+ (void *)(uintptr_t)(bar + UOCMUX));
} else {
- write32(bar + UOCMUX, read32(bar + UOCMUX) | PMUX_HOST);
+ write32(read32((void *)(uintptr_t)(bar + UOCMUX)) | PMUX_HOST,
+ (void *)(uintptr_t)(bar + UOCMUX));
}
/* Overcurrent configuration */
if (sb->enable_USBP4_overcurrent) {
- write32(bar + UOCCAP, read32(bar + UOCCAP)
- | sb->enable_USBP4_overcurrent);
+ write32(read32((void *)(uintptr_t)(bar + UOCCAP)) | sb->enable_USBP4_overcurrent,
+ (void *)(uintptr_t)(bar + UOCCAP));
}
}
@@ -486,8 +490,8 @@ static void enable_USB_port4(struct southbridge_amd_cs5536_config *sb)
PCI_DEVICE_ID_AMD_CS5536_UDC, 0);
if (dev) {
bar = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
- write32(bar + UDCDEVCTL,
- read32(bar + UDCDEVCTL) | UDC_SD_SET);
+ write32(read32((void *)(uintptr_t)(bar + UDCDEVCTL)) | UDC_SD_SET,
+ (void *)(uintptr_t)(bar + UDCDEVCTL));
}
@@ -495,8 +499,10 @@ static void enable_USB_port4(struct southbridge_amd_cs5536_config *sb)
PCI_DEVICE_ID_AMD_CS5536_OTG, 0);
if (dev) {
bar = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
- write32(bar + UOCCTL, read32(bar + UOCCTL) | PADEN_SET);
- write32(bar + UOCCAP, read32(bar + UOCCAP) | APU_SET);
+ write32(read32((void *)(uintptr_t)(bar + UOCCTL)) | PADEN_SET,
+ (void *)(uintptr_t)(bar + UOCCTL));
+ write32(read32((void *)(uintptr_t)(bar + UOCCAP)) | APU_SET,
+ (void *)(uintptr_t)(bar + UOCCAP));
}
}
diff --git a/src/southbridge/amd/pi/avalon/enable_usbdebug.c b/src/southbridge/amd/pi/avalon/enable_usbdebug.c
index 258267e..e9ba23d 100644
--- a/src/southbridge/amd/pi/avalon/enable_usbdebug.c
+++ b/src/southbridge/amd/pi/avalon/enable_usbdebug.c
@@ -44,11 +44,12 @@ void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port)
u32 reg32;
/* Write the port number to DEBUGPORT_MISC_CONTROL[31:28]. */
- reg32 = read32(base_regs + DEBUGPORT_MISC_CONTROL);
+ reg32 = read32((void *)(uintptr_t)(base_regs + DEBUGPORT_MISC_CONTROL));
reg32 &= ~(0xf << 28);
reg32 |= (port << 28);
reg32 |= (1 << 27); /* Enable Debug Port port number remapping. */
- write32(base_regs + DEBUGPORT_MISC_CONTROL, reg32);
+ write32(reg32,
+ (void *)(uintptr_t)(base_regs + DEBUGPORT_MISC_CONTROL));
}
diff --git a/src/southbridge/amd/pi/avalon/hudson.c b/src/southbridge/amd/pi/avalon/hudson.c
index 84eaf30..6424859 100644
--- a/src/southbridge/amd/pi/avalon/hudson.c
+++ b/src/southbridge/amd/pi/avalon/hudson.c
@@ -63,22 +63,22 @@ void backup_top_of_ram(uint64_t ramtop)
void pm_write8(u8 reg, u8 value)
{
- write8(PM_MMIO_BASE + reg, value);
+ write8(value, (void *)(uintptr_t)(PM_MMIO_BASE + reg));
}
u8 pm_read8(u8 reg)
{
- return read8(PM_MMIO_BASE + reg);
+ return read8((void *)(uintptr_t)(PM_MMIO_BASE + reg));
}
void pm_write16(u8 reg, u16 value)
{
- write16(PM_MMIO_BASE + reg, value);
+ write16(value, (void *)(uintptr_t)(PM_MMIO_BASE + reg));
}
u16 pm_read16(u16 reg)
{
- return read16(PM_MMIO_BASE + reg);
+ return read16((void *)(uintptr_t)(PM_MMIO_BASE + reg));
}
void hudson_enable(device_t dev)
diff --git a/src/southbridge/amd/pi/avalon/smi.h b/src/southbridge/amd/pi/avalon/smi.h
index de987a9..e28f0f6 100644
--- a/src/southbridge/amd/pi/avalon/smi.h
+++ b/src/southbridge/amd/pi/avalon/smi.h
@@ -36,22 +36,22 @@ enum smi_lvl {
static inline uint32_t smi_read32(uint8_t offset)
{
- return read32(SMI_BASE + offset);
+ return read32((void *)(uintptr_t)(SMI_BASE + offset));
}
static inline void smi_write32(uint8_t offset, uint32_t value)
{
- write32(SMI_BASE + offset, value);
+ write32(value, (void *)(uintptr_t)(SMI_BASE + offset));
}
static inline uint16_t smi_read16(uint8_t offset)
{
- return read16(SMI_BASE + offset);
+ return read16((void *)(uintptr_t)(SMI_BASE + offset));
}
static inline void smi_write16(uint8_t offset, uint16_t value)
{
- write16(SMI_BASE + offset, value);
+ write16(value, (void *)(uintptr_t)(SMI_BASE + offset));
}
void hudson_configure_gevent_smi(uint8_t gevent, uint8_t mode, uint8_t level);
diff --git a/src/southbridge/amd/sb600/hda.c b/src/southbridge/amd/sb600/hda.c
index c65f324..c675fae 100644
--- a/src/southbridge/amd/sb600/hda.c
+++ b/src/southbridge/amd/sb600/hda.c
@@ -37,10 +37,10 @@ static int set_bits(u32 port, u32 mask, u32 val)
/* Write (val & ~mask) to port */
val &= mask;
- dword = read32(port);
+ dword = read32((void *)(uintptr_t)(port));
dword &= ~mask;
dword |= val;
- write32(port, dword);
+ write32(dword, (void *)(uintptr_t)(port));
/* Wait for readback of register to
* match what was just written to it
@@ -49,7 +49,7 @@ static int set_bits(u32 port, u32 mask, u32 val)
do {
/* Wait 1ms based on BKDG wait time */
mdelay(1);
- dword = read32(port);
+ dword = read32((void *)(uintptr_t)(port));
dword &= mask;
} while ((dword != val) && --count);
@@ -75,7 +75,7 @@ static u32 codec_detect(u32 base)
mdelay(1);
/* Read in Codec location (BAR + 0xe)[3..0]*/
- dword = read32(base + 0xe);
+ dword = read32((void *)(uintptr_t)(base + 0xe));
dword &= 0x0F;
if (!dword)
goto no_codec;
@@ -180,7 +180,7 @@ static int wait_for_ready(u32 base)
int timeout = 50;
while(timeout--) {
- u32 dword=read32(base + HDA_ICII_REG);
+ u32 dword=read32((void *)(uintptr_t)(base + HDA_ICII_REG));
if (!(dword & HDA_ICII_BUSY))
return 0;
udelay(1);
@@ -201,7 +201,7 @@ static int wait_for_valid(u32 base)
int timeout = 50;
while(timeout--) {
- u32 dword = read32(base + HDA_ICII_REG);
+ u32 dword = read32((void *)(uintptr_t)(base + HDA_ICII_REG));
if ((dword & (HDA_ICII_VALID | HDA_ICII_BUSY)) ==
HDA_ICII_VALID)
return 0;
@@ -223,12 +223,12 @@ static void codec_init(u32 base, int addr)
return;
dword = (addr << 28) | 0x000f0000;
- write32(base + 0x60, dword);
+ write32(dword, (void *)(uintptr_t)(base + 0x60));
if (wait_for_valid(base) == -1)
return;
- dword = read32(base + 0x64);
+ dword = read32((void *)(uintptr_t)(base + 0x64));
/* 2 */
printk(BIOS_DEBUG, "codec viddid: %08x\n", dword);
@@ -245,7 +245,7 @@ static void codec_init(u32 base, int addr)
if (wait_for_ready(base) == -1)
return;
- write32(base + 0x60, verb[i]);
+ write32(verb[i], (void *)(uintptr_t)(base + 0x60));
if (wait_for_valid(base) == -1)
return;
diff --git a/src/southbridge/amd/sb600/sata.c b/src/southbridge/amd/sb600/sata.c
index a17aab8..cf4721f 100644
--- a/src/southbridge/amd/sb600/sata.c
+++ b/src/southbridge/amd/sb600/sata.c
@@ -184,7 +184,7 @@ static void sata_init(struct device *dev)
/* Use BAR5+0x2A8,BAR2 for Secondary Slave */
for (i = 0; i < 4; i++) {
- byte = read8(sata_bar5 + 0x128 + 0x80 * i);
+ byte = read8((void *)(uintptr_t)(sata_bar5 + 0x128 + 0x80 * i));
printk(BIOS_SPEW, "SATA port %i status = %x\n", i, byte);
byte &= 0xF;
@@ -194,24 +194,26 @@ static void sata_init(struct device *dev)
printk(BIOS_SPEW, "SATA device detected but not talking. Trying lower speed.\n");
/* Read in Port-N Serial ATA Control Register */
- byte = read8(sata_bar5 + 0x12C + 0x80 * i);
+ byte = read8((void *)(uintptr_t)(sata_bar5 + 0x12C + 0x80 * i));
/* Set Reset Bit and 1.5g bit */
byte |= 0x11;
- write8((sata_bar5 + 0x12C + 0x80 * i), byte);
+ write8(byte,
+ (void *)(uintptr_t)((sata_bar5 + 0x12C + 0x80 * i)));
/* Wait 1ms */
mdelay(1);
/* Clear Reset Bit */
byte &= ~0x01;
- write8((sata_bar5 + 0x12C + 0x80 * i), byte);
+ write8(byte,
+ (void *)(uintptr_t)((sata_bar5 + 0x12C + 0x80 * i)));
/* Wait 1ms */
mdelay(1);
/* Reread status */
- byte = read8(sata_bar5 + 0x128 + 0x80 * i);
+ byte = read8((void *)(uintptr_t)(sata_bar5 + 0x128 + 0x80 * i));
printk(BIOS_SPEW, "SATA port %i status = %x\n", i, byte);
byte &= 0xF;
}
@@ -235,15 +237,15 @@ static void sata_init(struct device *dev)
/* Below is CIM InitSataLateFar */
/* Enable interrupts from the HBA */
- byte = read8(sata_bar5 + 0x4);
+ byte = read8((void *)(uintptr_t)(sata_bar5 + 0x4));
byte |= 1 << 1;
- write8((sata_bar5 + 0x4), byte);
+ write8(byte, (void *)(uintptr_t)((sata_bar5 + 0x4)));
/* Clear error status */
- write32((sata_bar5 + 0x130), 0xFFFFFFFF);
- write32((sata_bar5 + 0x1b0), 0xFFFFFFFF);
- write32((sata_bar5 + 0x230), 0xFFFFFFFF);
- write32((sata_bar5 + 0x2b0), 0xFFFFFFFF);
+ write32(0xFFFFFFFF, (void *)(uintptr_t)((sata_bar5 + 0x130)));
+ write32(0xFFFFFFFF, (void *)(uintptr_t)((sata_bar5 + 0x1b0)));
+ write32(0xFFFFFFFF, (void *)(uintptr_t)((sata_bar5 + 0x230)));
+ write32(0xFFFFFFFF, (void *)(uintptr_t)((sata_bar5 + 0x2b0)));
/* Clear SATA status,Firstly we get the AcpiGpe0BlkAddr */
/* ????? why CIM does not set the AcpiGpe0BlkAddr , but use it??? */
diff --git a/src/southbridge/amd/sb600/usb.c b/src/southbridge/amd/sb600/usb.c
index 137a8da..b617263 100644
--- a/src/southbridge/amd/sb600/usb.c
+++ b/src/southbridge/amd/sb600/usb.c
@@ -98,16 +98,16 @@ static void usb_init2(struct device *dev)
/* RPR5.4 Enables the USB PHY auto calibration resister to match 45ohm resistance */
dword = 0x00020F00;
- write32(usb2_bar0 + 0xC0, dword);
+ write32(dword, (void *)(uintptr_t)(usb2_bar0 + 0xC0));
/* RPR5.5 Sets In/OUT FIFO threshold for best performance */
dword = 0x00200040;
- write32(usb2_bar0 + 0xA4, dword);
+ write32(dword, (void *)(uintptr_t)(usb2_bar0 + 0xA4));
/* RPR5.9 Disable the EHCI Dynamic Power Saving feature */
- word = read16(usb2_bar0 + 0xBC);
+ word = read16((void *)(uintptr_t)(usb2_bar0 + 0xBC));
word &= ~(1 << 12);
- write16(usb2_bar0 + 0xBC, word);
+ write16(word, (void *)(uintptr_t)(usb2_bar0 + 0xBC));
/* RPR5.10 Disable EHCI MSI support */
byte = pci_read_config8(dev, 0x50);
diff --git a/src/southbridge/amd/sb700/enable_usbdebug.c b/src/southbridge/amd/sb700/enable_usbdebug.c
index 3d23da0..f944f4b 100644
--- a/src/southbridge/amd/sb700/enable_usbdebug.c
+++ b/src/southbridge/amd/sb700/enable_usbdebug.c
@@ -43,11 +43,12 @@ void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port)
u32 reg32;
/* Write the port number to DEBUGPORT_MISC_CONTROL[31:28]. */
- reg32 = read32(base_regs + DEBUGPORT_MISC_CONTROL);
+ reg32 = read32((void *)(uintptr_t)(base_regs + DEBUGPORT_MISC_CONTROL));
reg32 &= ~(0xf << 28);
reg32 |= (port << 28);
reg32 |= (1 << 27); /* Enable Debug Port port number remapping. */
- write32(base_regs + DEBUGPORT_MISC_CONTROL, reg32);
+ write32(reg32,
+ (void *)(uintptr_t)(base_regs + DEBUGPORT_MISC_CONTROL));
}
void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base)
diff --git a/src/southbridge/amd/sb700/hda.c b/src/southbridge/amd/sb700/hda.c
index 61cc585..eab9bb4 100644
--- a/src/southbridge/amd/sb700/hda.c
+++ b/src/southbridge/amd/sb700/hda.c
@@ -37,10 +37,10 @@ static int set_bits(u32 port, u32 mask, u32 val)
/* Write (val & ~mask) to port */
val &= mask;
- dword = read32(port);
+ dword = read32((void *)(uintptr_t)(port));
dword &= ~mask;
dword |= val;
- write32(port, dword);
+ write32(dword, (void *)(uintptr_t)(port));
/* Wait for readback of register to
* match what was just written to it
@@ -49,7 +49,7 @@ static int set_bits(u32 port, u32 mask, u32 val)
do {
/* Wait 1ms based on BKDG wait time */
mdelay(1);
- dword = read32(port);
+ dword = read32((void *)(uintptr_t)(port));
dword &= mask;
} while ((dword != val) && --count);
@@ -75,7 +75,7 @@ static u32 codec_detect(u32 base)
mdelay(1);
/* Read in Codec location (BAR + 0xe)[3..0]*/
- dword = read32(base + 0xe);
+ dword = read32((void *)(uintptr_t)(base + 0xe));
dword &= 0x0F;
if (!dword)
goto no_codec;
@@ -102,7 +102,7 @@ static int wait_for_ready(u32 base)
int timeout = 50;
while(timeout--) {
- u32 dword=read32(base + HDA_ICII_REG);
+ u32 dword=read32((void *)(uintptr_t)(base + HDA_ICII_REG));
if (!(dword & HDA_ICII_BUSY))
return 0;
udelay(1);
@@ -123,7 +123,7 @@ static int wait_for_valid(u32 base)
int timeout = 50;
while(timeout--) {
- u32 dword = read32(base + HDA_ICII_REG);
+ u32 dword = read32((void *)(uintptr_t)(base + HDA_ICII_REG));
if ((dword & (HDA_ICII_VALID | HDA_ICII_BUSY)) ==
HDA_ICII_VALID)
return 0;
@@ -142,12 +142,12 @@ static void codec_init(u32 base, int addr)
return;
dword = (addr << 28) | 0x000f0000;
- write32(base + 0x60, dword);
+ write32(dword, (void *)(uintptr_t)(base + 0x60));
if (wait_for_valid(base) == -1)
return;
- dword = read32(base + 0x64);
+ dword = read32((void *)(uintptr_t)(base + 0x64));
/* 2 */
printk(BIOS_DEBUG, "%x(th) codec viddid: %08x\n", addr, dword);
diff --git a/src/southbridge/amd/sb700/sata.c b/src/southbridge/amd/sb700/sata.c
index c0e3c0f..5a0c723 100644
--- a/src/southbridge/amd/sb700/sata.c
+++ b/src/southbridge/amd/sb700/sata.c
@@ -202,7 +202,7 @@ static void sata_init(struct device *dev)
/* TODO: port 4,5, which are PATA emulations. What are PATA_BARs? */
for (i = 0; i < 4; i++) {
- byte = read8(sata_bar5 + 0x128 + 0x80 * i);
+ byte = read8((void *)(uintptr_t)(sata_bar5 + 0x128 + 0x80 * i));
printk(BIOS_SPEW, "SATA port %i status = %x\n", i, byte);
byte &= 0xF;
if( byte == 0x1 ) {
@@ -211,24 +211,26 @@ static void sata_init(struct device *dev)
printk(BIOS_SPEW, "SATA device detected but not talking. Trying lower speed.\n");
/* Read in Port-N Serial ATA Control Register */
- byte = read8(sata_bar5 + 0x12C + 0x80 * i);
+ byte = read8((void *)(uintptr_t)(sata_bar5 + 0x12C + 0x80 * i));
/* Set Reset Bit and 1.5g bit */
byte |= 0x11;
- write8((sata_bar5 + 0x12C + 0x80 * i), byte);
+ write8(byte,
+ (void *)(uintptr_t)((sata_bar5 + 0x12C + 0x80 * i)));
/* Wait 1ms */
mdelay(1);
/* Clear Reset Bit */
byte &= ~0x01;
- write8((sata_bar5 + 0x12C + 0x80 * i), byte);
+ write8(byte,
+ (void *)(uintptr_t)((sata_bar5 + 0x12C + 0x80 * i)));
/* Wait 1ms */
mdelay(1);
/* Reread status */
- byte = read8(sata_bar5 + 0x128 + 0x80 * i);
+ byte = read8((void *)(uintptr_t)(sata_bar5 + 0x128 + 0x80 * i));
printk(BIOS_SPEW, "SATA port %i status = %x\n", i, byte);
byte &= 0xF;
}
@@ -252,17 +254,17 @@ static void sata_init(struct device *dev)
/* Below is CIM InitSataLateFar */
/* Enable interrupts from the HBA */
- byte = read8(sata_bar5 + 0x4);
+ byte = read8((void *)(uintptr_t)(sata_bar5 + 0x4));
byte |= 1 << 1;
- write8((sata_bar5 + 0x4), byte);
+ write8(byte, (void *)(uintptr_t)((sata_bar5 + 0x4)));
/* Clear error status */
- write32((sata_bar5 + 0x130), 0xFFFFFFFF);
- write32((sata_bar5 + 0x1b0), 0xFFFFFFFF);
- write32((sata_bar5 + 0x230), 0xFFFFFFFF);
- write32((sata_bar5 + 0x2b0), 0xFFFFFFFF);
- write32((sata_bar5 + 0x330), 0xFFFFFFFF);
- write32((sata_bar5 + 0x3b0), 0xFFFFFFFF);
+ write32(0xFFFFFFFF, (void *)(uintptr_t)((sata_bar5 + 0x130)));
+ write32(0xFFFFFFFF, (void *)(uintptr_t)((sata_bar5 + 0x1b0)));
+ write32(0xFFFFFFFF, (void *)(uintptr_t)((sata_bar5 + 0x230)));
+ write32(0xFFFFFFFF, (void *)(uintptr_t)((sata_bar5 + 0x2b0)));
+ write32(0xFFFFFFFF, (void *)(uintptr_t)((sata_bar5 + 0x330)));
+ write32(0xFFFFFFFF, (void *)(uintptr_t)((sata_bar5 + 0x3b0)));
/* Clear SATA status,Firstly we get the AcpiGpe0BlkAddr */
/* ????? why CIM does not set the AcpiGpe0BlkAddr , but use it??? */
diff --git a/src/southbridge/amd/sb700/usb.c b/src/southbridge/amd/sb700/usb.c
index 77dcf2e..0b20ec5 100644
--- a/src/southbridge/amd/sb700/usb.c
+++ b/src/southbridge/amd/sb700/usb.c
@@ -97,11 +97,11 @@ static void usb_init2(struct device *dev)
/* RPR6.4 Enables the USB PHY auto calibration resister to match 45ohm resistance */
dword = 0x00020F00;
- write32(usb2_bar0 + 0xC0, dword);
+ write32(dword, (void *)(uintptr_t)(usb2_bar0 + 0xC0));
/* RPR6.9 Sets In/OUT FIFO threshold for best performance */
dword = 0x00400040;
- write32(usb2_bar0 + 0xA4, dword);
+ write32(dword, (void *)(uintptr_t)(usb2_bar0 + 0xA4));
/* RPR6.11 Disabling EHCI Advance Asynchronous Enhancement */
dword = pci_read_config32(dev, 0x50);
@@ -137,9 +137,9 @@ static void usb_init2(struct device *dev)
pci_write_config8(dev, 0x50, byte);
/* RPR6.17 Disable the EHCI Dynamic Power Saving feature */
- word = read32(usb2_bar0 + 0xBC);
+ word = read32((void *)(uintptr_t)(usb2_bar0 + 0xBC));
word &= ~(1 << 12);
- write16(usb2_bar0 + 0xBC, word);
+ write16(word, (void *)(uintptr_t)(usb2_bar0 + 0xBC));
/* RPR6.19 USB Controller DMA Read Delay Tolerant. */
if (rev >= REV_SB700_A14) {
diff --git a/src/southbridge/amd/sb800/enable_usbdebug.c b/src/southbridge/amd/sb800/enable_usbdebug.c
index 74e3d33..1923b9a 100644
--- a/src/southbridge/amd/sb800/enable_usbdebug.c
+++ b/src/southbridge/amd/sb800/enable_usbdebug.c
@@ -44,11 +44,12 @@ void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port)
u32 reg32;
/* Write the port number to DEBUGPORT_MISC_CONTROL[31:28]. */
- reg32 = read32(base_regs + DEBUGPORT_MISC_CONTROL);
+ reg32 = read32((void *)(uintptr_t)(base_regs + DEBUGPORT_MISC_CONTROL));
reg32 &= ~(0xf << 28);
reg32 |= (port << 28);
reg32 |= (1 << 27); /* Enable Debug Port port number remapping. */
- write32(base_regs + DEBUGPORT_MISC_CONTROL, reg32);
+ write32(reg32,
+ (void *)(uintptr_t)(base_regs + DEBUGPORT_MISC_CONTROL));
}
diff --git a/src/southbridge/amd/sb800/hda.c b/src/southbridge/amd/sb800/hda.c
index ad8f80f..917ed30 100644
--- a/src/southbridge/amd/sb800/hda.c
+++ b/src/southbridge/amd/sb800/hda.c
@@ -37,10 +37,10 @@ static int set_bits(u32 port, u32 mask, u32 val)
/* Write (val & ~mask) to port */
val &= mask;
- dword = read32(port);
+ dword = read32((void *)(uintptr_t)(port));
dword &= ~mask;
dword |= val;
- write32(port, dword);
+ write32(dword, (void *)(uintptr_t)(port));
/* Wait for readback of register to
* match what was just written to it
@@ -49,7 +49,7 @@ static int set_bits(u32 port, u32 mask, u32 val)
do {
/* Wait 1ms based on BKDG wait time */
mdelay(1);
- dword = read32(port);
+ dword = read32((void *)(uintptr_t)(port));
dword &= mask;
} while ((dword != val) && --count);
@@ -77,7 +77,7 @@ static u32 codec_detect(u32 base)
mdelay(1);
/* Read in Codec location (BAR + 0xe)[3..0]*/
- dword = read32(base + 0xe);
+ dword = read32((void *)(uintptr_t)(base + 0xe));
dword &= 0x0F;
if (!dword)
goto no_codec;
@@ -104,7 +104,7 @@ static int wait_for_ready(u32 base)
int timeout = 50;
while(timeout--) {
- u32 dword=read32(base + HDA_ICII_REG);
+ u32 dword=read32((void *)(uintptr_t)(base + HDA_ICII_REG));
if (!(dword & HDA_ICII_BUSY))
return 0;
udelay(1);
@@ -125,7 +125,7 @@ static int wait_for_valid(u32 base)
int timeout = 50;
while(timeout--) {
- u32 dword = read32(base + HDA_ICII_REG);
+ u32 dword = read32((void *)(uintptr_t)(base + HDA_ICII_REG));
if ((dword & (HDA_ICII_VALID | HDA_ICII_BUSY)) ==
HDA_ICII_VALID)
return 0;
@@ -144,12 +144,12 @@ static void codec_init(u32 base, int addr)
return;
dword = (addr << 28) | 0x000f0000;
- write32(base + 0x60, dword);
+ write32(dword, (void *)(uintptr_t)(base + 0x60));
if (wait_for_valid(base) == -1)
return;
- dword = read32(base + 0x64);
+ dword = read32((void *)(uintptr_t)(base + 0x64));
/* 2 */
printk(BIOS_DEBUG, "%x(th) codec viddid: %08x\n", addr, dword);
diff --git a/src/southbridge/amd/sb800/sata.c b/src/southbridge/amd/sb800/sata.c
index bd35e50..2da42c1 100644
--- a/src/southbridge/amd/sb800/sata.c
+++ b/src/southbridge/amd/sb800/sata.c
@@ -132,16 +132,16 @@ static void sata_init(struct device *dev)
pci_write_config8(dev, 0x34, 0x70); /* 8.11 SATA MSI and D3 Power State Capability */
- dword = read32(sata_bar5 + 0xFC);
+ dword = read32((void *)(uintptr_t)(sata_bar5 + 0xFC));
dword &= ~(1 << 11); /* rpr 8.8. Disabling Aggressive Link Power Management */
dword &= ~(1 << 12); /* rpr 8.9.1 Disabling Port Multiplier support. */
dword &= ~(1 << 10); /* rpr 8.9.2 disabling FIS-based Switching support */
dword &= ~(1 << 19); /* rpr 8.10. Disabling CCC (Command Completion Coalescing) Support */
- write32((sata_bar5 + 0xFC), dword);
+ write32(dword, (void *)(uintptr_t)((sata_bar5 + 0xFC)));
- dword = read32(sata_bar5 + 0xF8);
+ dword = read32((void *)(uintptr_t)(sata_bar5 + 0xF8));
dword &= ~(0x3F << 22); /* rpr 8.9.2 disabling FIS-based Switching support */
- write32(sata_bar5 + 0xF8, dword);
+ write32(dword, (void *)(uintptr_t)(sata_bar5 + 0xF8));
byte = pci_read_config8(dev, 0x40);
byte &= ~(1 << 0);
@@ -178,7 +178,7 @@ static void sata_init(struct device *dev)
/* TODO: port 4,5, which are PATA emulations. What are PATA_BARs? */
for (i = 0; i < 4; i++) {
- byte = read8(sata_bar5 + 0x128 + 0x80 * i);
+ byte = read8((void *)(uintptr_t)(sata_bar5 + 0x128 + 0x80 * i));
printk(BIOS_SPEW, "SATA port %i status = %x\n", i, byte);
byte &= 0xF;
if( byte == 0x1 ) {
@@ -187,24 +187,26 @@ static void sata_init(struct device *dev)
printk(BIOS_SPEW, "SATA device detected but not talking. Trying lower speed.\n");
/* Read in Port-N Serial ATA Control Register */
- byte = read8(sata_bar5 + 0x12C + 0x80 * i);
+ byte = read8((void *)(uintptr_t)(sata_bar5 + 0x12C + 0x80 * i));
/* Set Reset Bit and 1.5g bit */
byte |= 0x11;
- write8((sata_bar5 + 0x12C + 0x80 * i), byte);
+ write8(byte,
+ (void *)(uintptr_t)((sata_bar5 + 0x12C + 0x80 * i)));
/* Wait 1ms */
mdelay(1);
/* Clear Reset Bit */
byte &= ~0x01;
- write8((sata_bar5 + 0x12C + 0x80 * i), byte);
+ write8(byte,
+ (void *)(uintptr_t)((sata_bar5 + 0x12C + 0x80 * i)));
/* Wait 1ms */
mdelay(1);
/* Reread status */
- byte = read8(sata_bar5 + 0x128 + 0x80 * i);
+ byte = read8((void *)(uintptr_t)(sata_bar5 + 0x128 + 0x80 * i));
printk(BIOS_SPEW, "SATA port %i status = %x\n", i, byte);
byte &= 0xF;
}
@@ -228,17 +230,17 @@ static void sata_init(struct device *dev)
/* Below is CIM InitSataLateFar */
/* Enable interrupts from the HBA */
- byte = read8(sata_bar5 + 0x4);
+ byte = read8((void *)(uintptr_t)(sata_bar5 + 0x4));
byte |= 1 << 1;
- write8((sata_bar5 + 0x4), byte);
+ write8(byte, (void *)(uintptr_t)((sata_bar5 + 0x4)));
/* Clear error status */
- write32((sata_bar5 + 0x130), 0xFFFFFFFF);
- write32((sata_bar5 + 0x1b0), 0xFFFFFFFF);
- write32((sata_bar5 + 0x230), 0xFFFFFFFF);
- write32((sata_bar5 + 0x2b0), 0xFFFFFFFF);
- write32((sata_bar5 + 0x330), 0xFFFFFFFF);
- write32((sata_bar5 + 0x3b0), 0xFFFFFFFF);
+ write32(0xFFFFFFFF, (void *)(uintptr_t)((sata_bar5 + 0x130)));
+ write32(0xFFFFFFFF, (void *)(uintptr_t)((sata_bar5 + 0x1b0)));
+ write32(0xFFFFFFFF, (void *)(uintptr_t)((sata_bar5 + 0x230)));
+ write32(0xFFFFFFFF, (void *)(uintptr_t)((sata_bar5 + 0x2b0)));
+ write32(0xFFFFFFFF, (void *)(uintptr_t)((sata_bar5 + 0x330)));
+ write32(0xFFFFFFFF, (void *)(uintptr_t)((sata_bar5 + 0x3b0)));
/* Clear SATA status,Firstly we get the AcpiGpe0BlkAddr */
/* ????? why CIM does not set the AcpiGpe0BlkAddr , but use it??? */
diff --git a/src/southbridge/amd/sb800/usb.c b/src/southbridge/amd/sb800/usb.c
index 9304344..0d2beed 100644
--- a/src/southbridge/amd/sb800/usb.c
+++ b/src/southbridge/amd/sb800/usb.c
@@ -73,11 +73,11 @@ static void usb_init2(struct device *dev)
/* RPR7.3 Enables the USB PHY auto calibration resister to match 45ohm resistence */
dword = 0x00020F00;
- write32(usb2_bar0 + 0xC0, dword);
+ write32(dword, (void *)(uintptr_t)(usb2_bar0 + 0xC0));
/* RPR7.8 Sets In/OUT FIFO threshold for best performance */
dword = 0x00400040;
- write32(usb2_bar0 + 0xA4, dword);
+ write32(dword, (void *)(uintptr_t)(usb2_bar0 + 0xA4));
/* RPR7.10 Disable EHCI MSI support */
dword = pci_read_config32(dev, 0x50);
diff --git a/src/southbridge/broadcom/bcm5785/sata.c b/src/southbridge/broadcom/bcm5785/sata.c
index 62eab45..b57027e 100644
--- a/src/southbridge/broadcom/bcm5785/sata.c
+++ b/src/southbridge/broadcom/bcm5785/sata.c
@@ -45,14 +45,14 @@ static void sata_init(struct device *dev)
mmio_base = res->base;
mmio_base &= 0xfffffffc;
- write32(mmio_base + 0x10f0, 0x40000001);
- write32(mmio_base + 0x8c, 0x00ff2007);
+ write32(0x40000001, (void *)(uintptr_t)(mmio_base + 0x10f0));
+ write32(0x00ff2007, (void *)(uintptr_t)(mmio_base + 0x8c));
mdelay( 10 );
- write32(mmio_base + 0x8c, 0x78592009);
+ write32(0x78592009, (void *)(uintptr_t)(mmio_base + 0x8c));
mdelay( 10 );
- write32(mmio_base + 0x8c, 0x00082004);
+ write32(0x00082004, (void *)(uintptr_t)(mmio_base + 0x8c));
mdelay( 10 );
- write32(mmio_base + 0x8c, 0x00002004);
+ write32(0x00002004, (void *)(uintptr_t)(mmio_base + 0x8c));
mdelay( 10 );
//init PHY
@@ -60,13 +60,15 @@ static void sata_init(struct device *dev)
printk(BIOS_DEBUG, "init PHY...\n");
for(i=0; i<4; i++) {
mmio = res->base + 0x100 * i;
- byte = read8(mmio + 0x40);
+ byte = read8((void *)(uintptr_t)(mmio + 0x40));
printk(BIOS_DEBUG, "port %d PHY status = %02x\n", i, byte);
if(byte & 0x4) {// bit 2 is set
- byte = read8(mmio+0x48);
- write8(mmio + 0x48, byte | 1);
- write8(mmio + 0x48, byte & (~1));
- byte = read8(mmio + 0x40);
+ byte = read8((void *)(uintptr_t)(mmio + 0x48));
+ write8(byte | 1,
+ (void *)(uintptr_t)(mmio + 0x48));
+ write8(byte & (~1),
+ (void *)(uintptr_t)(mmio + 0x48));
+ byte = read8((void *)(uintptr_t)(mmio + 0x40));
printk(BIOS_DEBUG, "after reset port %d PHY status = %02x\n", i, byte);
}
}
diff --git a/src/southbridge/intel/bd82x6x/azalia.c b/src/southbridge/intel/bd82x6x/azalia.c
index bef88ab..b8efa53 100644
--- a/src/southbridge/intel/bd82x6x/azalia.c
+++ b/src/southbridge/intel/bd82x6x/azalia.c
@@ -42,10 +42,10 @@ static int set_bits(u32 port, u32 mask, u32 val)
/* Write (val & mask) to port */
val &= mask;
- reg32 = read32(port);
+ reg32 = read32((void *)(uintptr_t)(port));
reg32 &= ~mask;
reg32 |= val;
- write32(port, reg32);
+ write32(reg32, (void *)(uintptr_t)(port));
/* Wait for readback of register to
* match what was just written to it
@@ -54,7 +54,7 @@ static int set_bits(u32 port, u32 mask, u32 val)
do {
/* Wait 1ms based on BKDG wait time */
mdelay(1);
- reg32 = read32(port);
+ reg32 = read32((void *)(uintptr_t)(port));
reg32 &= mask;
} while ((reg32 != val) && --count);
@@ -73,10 +73,11 @@ static int codec_detect(u32 base)
goto no_codec;
/* Write back the value once reset bit is set. */
- write16(base + 0x0, read16(base + 0x0));
+ write16(read16((void *)(uintptr_t)(base + 0x0)),
+ (void *)(uintptr_t)(base + 0x0));
/* Read in Codec location (BAR + 0xe)[2..0]*/
- reg8 = read8(base + 0xe);
+ reg8 = read8((void *)(uintptr_t)(base + 0xe));
reg8 &= 0x0f;
if (!reg8)
goto no_codec;
@@ -121,7 +122,7 @@ static int wait_for_ready(u32 base)
int timeout = 1000;
while(timeout--) {
- u32 reg32 = read32(base + HDA_ICII_REG);
+ u32 reg32 = read32((void *)(uintptr_t)(base + HDA_ICII_REG));
if (!(reg32 & HDA_ICII_BUSY))
return 0;
udelay(1);
@@ -141,15 +142,15 @@ static int wait_for_valid(u32 base)
u32 reg32;
/* Send the verb to the codec */
- reg32 = read32(base + HDA_ICII_REG);
+ reg32 = read32((void *)(uintptr_t)(base + HDA_ICII_REG));
reg32 |= HDA_ICII_BUSY | HDA_ICII_VALID;
- write32(base + HDA_ICII_REG, reg32);
+ write32(reg32, (void *)(uintptr_t)(base + HDA_ICII_REG));
/* Use a 1msec timeout */
int timeout = 1000;
while(timeout--) {
- reg32 = read32(base + HDA_ICII_REG);
+ reg32 = read32((void *)(uintptr_t)(base + HDA_ICII_REG));
if ((reg32 & (HDA_ICII_VALID | HDA_ICII_BUSY)) ==
HDA_ICII_VALID)
return 0;
@@ -175,14 +176,14 @@ static void codec_init(struct device *dev, u32 base, int addr)
}
reg32 = (addr << 28) | 0x000f0000;
- write32(base + 0x60, reg32);
+ write32(reg32, (void *)(uintptr_t)(base + 0x60));
if (wait_for_valid(base) == -1) {
printk(BIOS_DEBUG, " codec not valid.\n");
return;
}
- reg32 = read32(base + 0x64);
+ reg32 = read32((void *)(uintptr_t)(base + 0x64));
/* 2 */
printk(BIOS_DEBUG, "Azalia: codec viddid: %08x\n", reg32);
@@ -199,7 +200,7 @@ static void codec_init(struct device *dev, u32 base, int addr)
if (wait_for_ready(base) == -1)
return;
- write32(base + 0x60, verb[i]);
+ write32(verb[i], (void *)(uintptr_t)(base + 0x60));
if (wait_for_valid(base) == -1)
return;
@@ -219,7 +220,7 @@ static void codecs_init(struct device *dev, u32 base, u32 codec_mask)
if (wait_for_ready(base) == -1)
return;
- write32(base + 0x60, pc_beep_verbs[i]);
+ write32(pc_beep_verbs[i], (void *)(uintptr_t)(base + 0x60));
if (wait_for_valid(base) == -1)
return;
@@ -305,9 +306,9 @@ static void azalia_init(struct device *dev)
/* Codec Initialization Programming Sequence */
/* Take controller out of reset */
- reg32 = read32(base + 0x08);
+ reg32 = read32((void *)(uintptr_t)(base + 0x08));
reg32 |= (1 << 0);
- write32(base + 0x08, reg32);
+ write32(reg32, (void *)(uintptr_t)(base + 0x08));
/* Wait 1ms */
udelay(1000);
diff --git a/src/southbridge/intel/bd82x6x/early_pch_native.c b/src/southbridge/intel/bd82x6x/early_pch_native.c
index 0863f34..0030a49 100644
--- a/src/southbridge/intel/bd82x6x/early_pch_native.c
+++ b/src/southbridge/intel/bd82x6x/early_pch_native.c
@@ -37,7 +37,7 @@
static void
wait_2338 (void)
{
- while (read8 (DEFAULT_RCBA | 0x2338) & 1);
+ while (read8((void *)(uintptr_t)(DEFAULT_RCBA | 0x2338)) & 1);
}
static u32
@@ -45,13 +45,13 @@ read_2338 (u32 edx)
{
u32 ret;
- write32 (DEFAULT_RCBA | 0x2330, edx);
- write16 (DEFAULT_RCBA | 0x2338, (read16 (DEFAULT_RCBA | 0x2338)
- & 0x1ff) | 0x600);
+ write32(edx, (void *)(uintptr_t)(DEFAULT_RCBA | 0x2330));
+ write16((read16((void *)(uintptr_t)(DEFAULT_RCBA | 0x2338)) & 0x1ff) | 0x600,
+ (void *)(uintptr_t)(DEFAULT_RCBA | 0x2338));
wait_2338 ();
- ret = read32 (DEFAULT_RCBA | 0x2334);
+ ret = read32((void *)(uintptr_t)(DEFAULT_RCBA | 0x2334));
wait_2338 ();
- read8 (DEFAULT_RCBA | 0x2338);
+ read8((void *)(uintptr_t)(DEFAULT_RCBA | 0x2338));
return ret;
}
@@ -59,15 +59,15 @@ static void
write_2338 (u32 edx, u32 val)
{
read_2338 (edx);
- write16 (DEFAULT_RCBA | 0x2338, (read16 (DEFAULT_RCBA | 0x2338)
- & 0x1ff) | 0x600);
+ write16((read16((void *)(uintptr_t)(DEFAULT_RCBA | 0x2338)) & 0x1ff) | 0x600,
+ (void *)(uintptr_t)(DEFAULT_RCBA | 0x2338));
wait_2338 ();
- write32 (DEFAULT_RCBA | 0x2334, val);
+ write32(val, (void *)(uintptr_t)(DEFAULT_RCBA | 0x2334));
wait_2338 ();
- write16 (DEFAULT_RCBA | 0x2338,
- (read16 (DEFAULT_RCBA | 0x2338) & 0x1ff) | 0x600);
- read8 (DEFAULT_RCBA | 0x2338);
+ write16((read16((void *)(uintptr_t)(DEFAULT_RCBA | 0x2338)) & 0x1ff) | 0x600,
+ (void *)(uintptr_t)(DEFAULT_RCBA | 0x2338));
+ read8((void *)(uintptr_t)(DEFAULT_RCBA | 0x2338));
}
@@ -76,214 +76,214 @@ init_dmi (void)
{
int i;
- write32 (DEFAULT_DMIBAR | 0x0914,
- read32 (DEFAULT_DMIBAR | 0x0914) | 0x80000000);
- write32 (DEFAULT_DMIBAR | 0x0934,
- read32 (DEFAULT_DMIBAR | 0x0934) | 0x80000000);
+ write32(read32((void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0914)) | 0x80000000,
+ (void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0914));
+ write32(read32((void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0934)) | 0x80000000,
+ (void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0934));
for (i = 0; i < 4; i++)
{
- write32 (DEFAULT_DMIBAR | 0x0a00 | (i << 4),
- read32 (DEFAULT_DMIBAR | 0x0a00 | (i << 4)) & 0xf3ffffff);
- write32 (DEFAULT_DMIBAR | 0x0a04 | (i << 4),
- read32 (DEFAULT_DMIBAR | 0x0a04 | (i << 4)) | 0x800);
+ write32(read32((void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0a00 | (i << 4))) & 0xf3ffffff,
+ (void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0a00 | (i << 4)));
+ write32(read32((void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0a04 | (i << 4))) | 0x800,
+ (void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0a04 | (i << 4)));
}
- write32 (DEFAULT_DMIBAR | 0x0c30, (read32 (DEFAULT_DMIBAR | 0x0c30)
- & 0xfffffff) | 0x40000000);
+ write32((read32((void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0c30)) & 0xfffffff) | 0x40000000,
+ (void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0c30));
for (i = 0; i < 2; i++)
{
- write32 (DEFAULT_DMIBAR | 0x0904 | (i << 5),
- read32 (DEFAULT_DMIBAR | 0x0904 | (i << 5)) & 0xfe3fffff);
- write32 (DEFAULT_DMIBAR | 0x090c | (i << 5),
- read32 (DEFAULT_DMIBAR | 0x090c | (i << 5)) & 0xfff1ffff);
+ write32(read32((void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0904 | (i << 5))) & 0xfe3fffff,
+ (void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0904 | (i << 5)));
+ write32(read32((void *)(uintptr_t)(DEFAULT_DMIBAR | 0x090c | (i << 5))) & 0xfff1ffff,
+ (void *)(uintptr_t)(DEFAULT_DMIBAR | 0x090c | (i << 5)));
}
- write32 (DEFAULT_DMIBAR | 0x090c,
- read32 (DEFAULT_DMIBAR | 0x090c) & 0xfe1fffff);
- write32 (DEFAULT_DMIBAR | 0x092c,
- read32 (DEFAULT_DMIBAR | 0x092c) & 0xfe1fffff);
- read32 (DEFAULT_DMIBAR | 0x0904); // !!! = 0x7a1842ec
- write32 (DEFAULT_DMIBAR | 0x0904, 0x7a1842ec);
- read32 (DEFAULT_DMIBAR | 0x090c); // !!! = 0x00000208
- write32 (DEFAULT_DMIBAR | 0x090c, 0x00000128);
- read32 (DEFAULT_DMIBAR | 0x0924); // !!! = 0x7a1842ec
- write32 (DEFAULT_DMIBAR | 0x0924, 0x7a1842ec);
- read32 (DEFAULT_DMIBAR | 0x092c); // !!! = 0x00000208
- write32 (DEFAULT_DMIBAR | 0x092c, 0x00000128);
- read32 (DEFAULT_DMIBAR | 0x0700); // !!! = 0x46139008
- write32 (DEFAULT_DMIBAR | 0x0700, 0x46139008);
- read32 (DEFAULT_DMIBAR | 0x0720); // !!! = 0x46139008
- write32 (DEFAULT_DMIBAR | 0x0720, 0x46139008);
- read32 (DEFAULT_DMIBAR | 0x0c04); // !!! = 0x2e680008
- write32 (DEFAULT_DMIBAR | 0x0c04, 0x2e680008);
- read32 (DEFAULT_DMIBAR | 0x0904); // !!! = 0x7a1842ec
- write32 (DEFAULT_DMIBAR | 0x0904, 0x3a1842ec);
- read32 (DEFAULT_DMIBAR | 0x0924); // !!! = 0x7a1842ec
- write32 (DEFAULT_DMIBAR | 0x0924, 0x3a1842ec);
- read32 (DEFAULT_DMIBAR | 0x0910); // !!! = 0x00006300
- write32 (DEFAULT_DMIBAR | 0x0910, 0x00004300);
- read32 (DEFAULT_DMIBAR | 0x0930); // !!! = 0x00006300
- write32 (DEFAULT_DMIBAR | 0x0930, 0x00004300);
- read32 (DEFAULT_DMIBAR | 0x0a00); // !!! = 0x03042010
- write32 (DEFAULT_DMIBAR | 0x0a00, 0x03042018);
- read32 (DEFAULT_DMIBAR | 0x0a10); // !!! = 0x03042010
- write32 (DEFAULT_DMIBAR | 0x0a10, 0x03042018);
- read32 (DEFAULT_DMIBAR | 0x0a20); // !!! = 0x03042010
- write32 (DEFAULT_DMIBAR | 0x0a20, 0x03042018);
- read32 (DEFAULT_DMIBAR | 0x0a30); // !!! = 0x03042010
- write32 (DEFAULT_DMIBAR | 0x0a30, 0x03042018);
- read32 (DEFAULT_DMIBAR | 0x0c00); // !!! = 0x29700c08
- write32 (DEFAULT_DMIBAR | 0x0c00, 0x29700c08);
- read32 (DEFAULT_DMIBAR | 0x0a04); // !!! = 0x0c0708f0
- write32 (DEFAULT_DMIBAR | 0x0a04, 0x0c0718f0);
- read32 (DEFAULT_DMIBAR | 0x0a14); // !!! = 0x0c0708f0
- write32 (DEFAULT_DMIBAR | 0x0a14, 0x0c0718f0);
- read32 (DEFAULT_DMIBAR | 0x0a24); // !!! = 0x0c0708f0
- write32 (DEFAULT_DMIBAR | 0x0a24, 0x0c0718f0);
- read32 (DEFAULT_DMIBAR | 0x0a34); // !!! = 0x0c0708f0
- write32 (DEFAULT_DMIBAR | 0x0a34, 0x0c0718f0);
- read32 (DEFAULT_DMIBAR | 0x0900); // !!! = 0x50000000
- write32 (DEFAULT_DMIBAR | 0x0900, 0x50000000);
- read32 (DEFAULT_DMIBAR | 0x0920); // !!! = 0x50000000
- write32 (DEFAULT_DMIBAR | 0x0920, 0x50000000);
- read32 (DEFAULT_DMIBAR | 0x0908); // !!! = 0x51ffffff
- write32 (DEFAULT_DMIBAR | 0x0908, 0x51ffffff);
- read32 (DEFAULT_DMIBAR | 0x0928); // !!! = 0x51ffffff
- write32 (DEFAULT_DMIBAR | 0x0928, 0x51ffffff);
- read32 (DEFAULT_DMIBAR | 0x0a00); // !!! = 0x03042018
- write32 (DEFAULT_DMIBAR | 0x0a00, 0x03042018);
- read32 (DEFAULT_DMIBAR | 0x0a10); // !!! = 0x03042018
- write32 (DEFAULT_DMIBAR | 0x0a10, 0x03042018);
- read32 (DEFAULT_DMIBAR | 0x0a20); // !!! = 0x03042018
- write32 (DEFAULT_DMIBAR | 0x0a20, 0x03042018);
- read32 (DEFAULT_DMIBAR | 0x0a30); // !!! = 0x03042018
- write32 (DEFAULT_DMIBAR | 0x0a30, 0x03042018);
- read32 (DEFAULT_DMIBAR | 0x0700); // !!! = 0x46139008
- write32 (DEFAULT_DMIBAR | 0x0700, 0x46139008);
- read32 (DEFAULT_DMIBAR | 0x0720); // !!! = 0x46139008
- write32 (DEFAULT_DMIBAR | 0x0720, 0x46139008);
- read32 (DEFAULT_DMIBAR | 0x0904); // !!! = 0x3a1842ec
- write32 (DEFAULT_DMIBAR | 0x0904, 0x3a1846ec);
- read32 (DEFAULT_DMIBAR | 0x0924); // !!! = 0x3a1842ec
- write32 (DEFAULT_DMIBAR | 0x0924, 0x3a1846ec);
- read32 (DEFAULT_DMIBAR | 0x0a00); // !!! = 0x03042018
- write32 (DEFAULT_DMIBAR | 0x0a00, 0x03042018);
- read32 (DEFAULT_DMIBAR | 0x0a10); // !!! = 0x03042018
- write32 (DEFAULT_DMIBAR | 0x0a10, 0x03042018);
- read32 (DEFAULT_DMIBAR | 0x0a20); // !!! = 0x03042018
- write32 (DEFAULT_DMIBAR | 0x0a20, 0x03042018);
- read32 (DEFAULT_DMIBAR | 0x0a30); // !!! = 0x03042018
- write32 (DEFAULT_DMIBAR | 0x0a30, 0x03042018);
- read32 (DEFAULT_DMIBAR | 0x0908); // !!! = 0x51ffffff
- write32 (DEFAULT_DMIBAR | 0x0908, 0x51ffffff);
- read32 (DEFAULT_DMIBAR | 0x0928); // !!! = 0x51ffffff
- write32 (DEFAULT_DMIBAR | 0x0928, 0x51ffffff);
- read32 (DEFAULT_DMIBAR | 0x0c00); // !!! = 0x29700c08
- write32 (DEFAULT_DMIBAR | 0x0c00, 0x29700c08);
- read32 (DEFAULT_DMIBAR | 0x0c0c); // !!! = 0x16063400
- write32 (DEFAULT_DMIBAR | 0x0c0c, 0x00063400);
- read32 (DEFAULT_DMIBAR | 0x0700); // !!! = 0x46139008
- write32 (DEFAULT_DMIBAR | 0x0700, 0x46339008);
- read32 (DEFAULT_DMIBAR | 0x0720); // !!! = 0x46139008
- write32 (DEFAULT_DMIBAR | 0x0720, 0x46339008);
- read32 (DEFAULT_DMIBAR | 0x0700); // !!! = 0x46339008
- write32 (DEFAULT_DMIBAR | 0x0700, 0x45339008);
- read32 (DEFAULT_DMIBAR | 0x0720); // !!! = 0x46339008
- write32 (DEFAULT_DMIBAR | 0x0720, 0x45339008);
- read32 (DEFAULT_DMIBAR | 0x0700); // !!! = 0x45339008
- write32 (DEFAULT_DMIBAR | 0x0700, 0x453b9008);
- read32 (DEFAULT_DMIBAR | 0x0720); // !!! = 0x45339008
- write32 (DEFAULT_DMIBAR | 0x0720, 0x453b9008);
- read32 (DEFAULT_DMIBAR | 0x0700); // !!! = 0x453b9008
- write32 (DEFAULT_DMIBAR | 0x0700, 0x45bb9008);
- read32 (DEFAULT_DMIBAR | 0x0720); // !!! = 0x453b9008
- write32 (DEFAULT_DMIBAR | 0x0720, 0x45bb9008);
- read32 (DEFAULT_DMIBAR | 0x0700); // !!! = 0x45bb9008
- write32 (DEFAULT_DMIBAR | 0x0700, 0x45fb9008);
- read32 (DEFAULT_DMIBAR | 0x0720); // !!! = 0x45bb9008
- write32 (DEFAULT_DMIBAR | 0x0720, 0x45fb9008);
- read32 (DEFAULT_DMIBAR | 0x0914); // !!! = 0x9021a080
- write32 (DEFAULT_DMIBAR | 0x0914, 0x9021a280);
- read32 (DEFAULT_DMIBAR | 0x0934); // !!! = 0x9021a080
- write32 (DEFAULT_DMIBAR | 0x0934, 0x9021a280);
- read32 (DEFAULT_DMIBAR | 0x0914); // !!! = 0x9021a280
- write32 (DEFAULT_DMIBAR | 0x0914, 0x9821a280);
- read32 (DEFAULT_DMIBAR | 0x0934); // !!! = 0x9021a280
- write32 (DEFAULT_DMIBAR | 0x0934, 0x9821a280);
- read32 (DEFAULT_DMIBAR | 0x0a00); // !!! = 0x03042018
- write32 (DEFAULT_DMIBAR | 0x0a00, 0x03242018);
- read32 (DEFAULT_DMIBAR | 0x0a10); // !!! = 0x03042018
- write32 (DEFAULT_DMIBAR | 0x0a10, 0x03242018);
- read32 (DEFAULT_DMIBAR | 0x0a20); // !!! = 0x03042018
- write32 (DEFAULT_DMIBAR | 0x0a20, 0x03242018);
- read32 (DEFAULT_DMIBAR | 0x0a30); // !!! = 0x03042018
- write32 (DEFAULT_DMIBAR | 0x0a30, 0x03242018);
- read32 (DEFAULT_DMIBAR | 0x0258); // !!! = 0x40000600
- write32 (DEFAULT_DMIBAR | 0x0258, 0x60000600);
- read32 (DEFAULT_DMIBAR | 0x0904); // !!! = 0x3a1846ec
- write32 (DEFAULT_DMIBAR | 0x0904, 0x2a1846ec);
- read32 (DEFAULT_DMIBAR | 0x0914); // !!! = 0x9821a280
- write32 (DEFAULT_DMIBAR | 0x0914, 0x98200280);
- read32 (DEFAULT_DMIBAR | 0x0924); // !!! = 0x3a1846ec
- write32 (DEFAULT_DMIBAR | 0x0924, 0x2a1846ec);
- read32 (DEFAULT_DMIBAR | 0x0934); // !!! = 0x9821a280
- write32 (DEFAULT_DMIBAR | 0x0934, 0x98200280);
- read32 (DEFAULT_DMIBAR | 0x022c); // !!! = 0x00c26460
- write32 (DEFAULT_DMIBAR | 0x022c, 0x00c2403c);
- read8 (DEFAULT_RCBA | 0x21a4); // !!! = 0x42
+ write32(read32((void *)(uintptr_t)(DEFAULT_DMIBAR | 0x090c)) & 0xfe1fffff,
+ (void *)(uintptr_t)(DEFAULT_DMIBAR | 0x090c));
+ write32(read32((void *)(uintptr_t)(DEFAULT_DMIBAR | 0x092c)) & 0xfe1fffff,
+ (void *)(uintptr_t)(DEFAULT_DMIBAR | 0x092c));
+ read32((void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0904)); // !!! = 0x7a1842ec
+ write32(0x7a1842ec, (void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0904));
+ read32((void *)(uintptr_t)(DEFAULT_DMIBAR | 0x090c)); // !!! = 0x00000208
+ write32(0x00000128, (void *)(uintptr_t)(DEFAULT_DMIBAR | 0x090c));
+ read32((void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0924)); // !!! = 0x7a1842ec
+ write32(0x7a1842ec, (void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0924));
+ read32((void *)(uintptr_t)(DEFAULT_DMIBAR | 0x092c)); // !!! = 0x00000208
+ write32(0x00000128, (void *)(uintptr_t)(DEFAULT_DMIBAR | 0x092c));
+ read32((void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0700)); // !!! = 0x46139008
+ write32(0x46139008, (void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0700));
+ read32((void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0720)); // !!! = 0x46139008
+ write32(0x46139008, (void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0720));
+ read32((void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0c04)); // !!! = 0x2e680008
+ write32(0x2e680008, (void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0c04));
+ read32((void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0904)); // !!! = 0x7a1842ec
+ write32(0x3a1842ec, (void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0904));
+ read32((void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0924)); // !!! = 0x7a1842ec
+ write32(0x3a1842ec, (void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0924));
+ read32((void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0910)); // !!! = 0x00006300
+ write32(0x00004300, (void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0910));
+ read32((void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0930)); // !!! = 0x00006300
+ write32(0x00004300, (void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0930));
+ read32((void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0a00)); // !!! = 0x03042010
+ write32(0x03042018, (void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0a00));
+ read32((void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0a10)); // !!! = 0x03042010
+ write32(0x03042018, (void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0a10));
+ read32((void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0a20)); // !!! = 0x03042010
+ write32(0x03042018, (void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0a20));
+ read32((void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0a30)); // !!! = 0x03042010
+ write32(0x03042018, (void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0a30));
+ read32((void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0c00)); // !!! = 0x29700c08
+ write32(0x29700c08, (void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0c00));
+ read32((void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0a04)); // !!! = 0x0c0708f0
+ write32(0x0c0718f0, (void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0a04));
+ read32((void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0a14)); // !!! = 0x0c0708f0
+ write32(0x0c0718f0, (void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0a14));
+ read32((void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0a24)); // !!! = 0x0c0708f0
+ write32(0x0c0718f0, (void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0a24));
+ read32((void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0a34)); // !!! = 0x0c0708f0
+ write32(0x0c0718f0, (void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0a34));
+ read32((void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0900)); // !!! = 0x50000000
+ write32(0x50000000, (void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0900));
+ read32((void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0920)); // !!! = 0x50000000
+ write32(0x50000000, (void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0920));
+ read32((void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0908)); // !!! = 0x51ffffff
+ write32(0x51ffffff, (void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0908));
+ read32((void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0928)); // !!! = 0x51ffffff
+ write32(0x51ffffff, (void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0928));
+ read32((void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0a00)); // !!! = 0x03042018
+ write32(0x03042018, (void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0a00));
+ read32((void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0a10)); // !!! = 0x03042018
+ write32(0x03042018, (void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0a10));
+ read32((void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0a20)); // !!! = 0x03042018
+ write32(0x03042018, (void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0a20));
+ read32((void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0a30)); // !!! = 0x03042018
+ write32(0x03042018, (void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0a30));
+ read32((void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0700)); // !!! = 0x46139008
+ write32(0x46139008, (void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0700));
+ read32((void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0720)); // !!! = 0x46139008
+ write32(0x46139008, (void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0720));
+ read32((void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0904)); // !!! = 0x3a1842ec
+ write32(0x3a1846ec, (void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0904));
+ read32((void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0924)); // !!! = 0x3a1842ec
+ write32(0x3a1846ec, (void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0924));
+ read32((void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0a00)); // !!! = 0x03042018
+ write32(0x03042018, (void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0a00));
+ read32((void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0a10)); // !!! = 0x03042018
+ write32(0x03042018, (void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0a10));
+ read32((void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0a20)); // !!! = 0x03042018
+ write32(0x03042018, (void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0a20));
+ read32((void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0a30)); // !!! = 0x03042018
+ write32(0x03042018, (void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0a30));
+ read32((void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0908)); // !!! = 0x51ffffff
+ write32(0x51ffffff, (void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0908));
+ read32((void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0928)); // !!! = 0x51ffffff
+ write32(0x51ffffff, (void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0928));
+ read32((void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0c00)); // !!! = 0x29700c08
+ write32(0x29700c08, (void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0c00));
+ read32((void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0c0c)); // !!! = 0x16063400
+ write32(0x00063400, (void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0c0c));
+ read32((void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0700)); // !!! = 0x46139008
+ write32(0x46339008, (void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0700));
+ read32((void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0720)); // !!! = 0x46139008
+ write32(0x46339008, (void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0720));
+ read32((void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0700)); // !!! = 0x46339008
+ write32(0x45339008, (void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0700));
+ read32((void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0720)); // !!! = 0x46339008
+ write32(0x45339008, (void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0720));
+ read32((void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0700)); // !!! = 0x45339008
+ write32(0x453b9008, (void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0700));
+ read32((void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0720)); // !!! = 0x45339008
+ write32(0x453b9008, (void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0720));
+ read32((void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0700)); // !!! = 0x453b9008
+ write32(0x45bb9008, (void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0700));
+ read32((void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0720)); // !!! = 0x453b9008
+ write32(0x45bb9008, (void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0720));
+ read32((void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0700)); // !!! = 0x45bb9008
+ write32(0x45fb9008, (void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0700));
+ read32((void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0720)); // !!! = 0x45bb9008
+ write32(0x45fb9008, (void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0720));
+ read32((void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0914)); // !!! = 0x9021a080
+ write32(0x9021a280, (void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0914));
+ read32((void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0934)); // !!! = 0x9021a080
+ write32(0x9021a280, (void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0934));
+ read32((void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0914)); // !!! = 0x9021a280
+ write32(0x9821a280, (void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0914));
+ read32((void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0934)); // !!! = 0x9021a280
+ write32(0x9821a280, (void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0934));
+ read32((void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0a00)); // !!! = 0x03042018
+ write32(0x03242018, (void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0a00));
+ read32((void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0a10)); // !!! = 0x03042018
+ write32(0x03242018, (void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0a10));
+ read32((void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0a20)); // !!! = 0x03042018
+ write32(0x03242018, (void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0a20));
+ read32((void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0a30)); // !!! = 0x03042018
+ write32(0x03242018, (void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0a30));
+ read32((void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0258)); // !!! = 0x40000600
+ write32(0x60000600, (void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0258));
+ read32((void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0904)); // !!! = 0x3a1846ec
+ write32(0x2a1846ec, (void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0904));
+ read32((void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0914)); // !!! = 0x9821a280
+ write32(0x98200280, (void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0914));
+ read32((void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0924)); // !!! = 0x3a1846ec
+ write32(0x2a1846ec, (void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0924));
+ read32((void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0934)); // !!! = 0x9821a280
+ write32(0x98200280, (void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0934));
+ read32((void *)(uintptr_t)(DEFAULT_DMIBAR | 0x022c)); // !!! = 0x00c26460
+ write32(0x00c2403c, (void *)(uintptr_t)(DEFAULT_DMIBAR | 0x022c));
+ read8((void *)(uintptr_t)(DEFAULT_RCBA | 0x21a4)); // !!! = 0x42
- read32 (DEFAULT_RCBA | 0x21a4); // !!! = 0x00012c42
- read32 (DEFAULT_RCBA | 0x2340); // !!! = 0x0013001b
- write32 (DEFAULT_RCBA | 0x2340, 0x003a001b);
- read8 (DEFAULT_RCBA | 0x21b0); // !!! = 0x01
- write8 (DEFAULT_RCBA | 0x21b0, 0x02);
- read32 (DEFAULT_DMIBAR | 0x0084); // !!! = 0x0041ac41
- write32 (DEFAULT_DMIBAR | 0x0084, 0x0041ac42);
- read8 (DEFAULT_DMIBAR | 0x0088); // !!! = 0x00
- write8 (DEFAULT_DMIBAR | 0x0088, 0x20);
- read16 (DEFAULT_DMIBAR | 0x008a); // !!! = 0x0041
- read8 (DEFAULT_DMIBAR | 0x0088); // !!! = 0x00
- write8 (DEFAULT_DMIBAR | 0x0088, 0x20);
- read16 (DEFAULT_DMIBAR | 0x008a); // !!! = 0x0042
- read16 (DEFAULT_DMIBAR | 0x008a); // !!! = 0x0042
+ read32((void *)(uintptr_t)(DEFAULT_RCBA | 0x21a4)); // !!! = 0x00012c42
+ read32((void *)(uintptr_t)(DEFAULT_RCBA | 0x2340)); // !!! = 0x0013001b
+ write32(0x003a001b, (void *)(uintptr_t)(DEFAULT_RCBA | 0x2340));
+ read8((void *)(uintptr_t)(DEFAULT_RCBA | 0x21b0)); // !!! = 0x01
+ write8(0x02, (void *)(uintptr_t)(DEFAULT_RCBA | 0x21b0));
+ read32((void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0084)); // !!! = 0x0041ac41
+ write32(0x0041ac42, (void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0084));
+ read8((void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0088)); // !!! = 0x00
+ write8(0x20, (void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0088));
+ read16((void *)(uintptr_t)(DEFAULT_DMIBAR | 0x008a)); // !!! = 0x0041
+ read8((void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0088)); // !!! = 0x00
+ write8(0x20, (void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0088));
+ read16((void *)(uintptr_t)(DEFAULT_DMIBAR | 0x008a)); // !!! = 0x0042
+ read16((void *)(uintptr_t)(DEFAULT_DMIBAR | 0x008a)); // !!! = 0x0042
- read32 (DEFAULT_DMIBAR | 0x0014); // !!! = 0x8000007f
- write32 (DEFAULT_DMIBAR | 0x0014, 0x80000019);
- read32 (DEFAULT_DMIBAR | 0x0020); // !!! = 0x01000000
- write32 (DEFAULT_DMIBAR | 0x0020, 0x81000022);
- read32 (DEFAULT_DMIBAR | 0x002c); // !!! = 0x02000000
- write32 (DEFAULT_DMIBAR | 0x002c, 0x82000044);
- read32 (DEFAULT_DMIBAR | 0x0038); // !!! = 0x07000080
- write32 (DEFAULT_DMIBAR | 0x0038, 0x87000080);
- read8 (DEFAULT_DMIBAR | 0x0004); // !!! = 0x00
- write8 (DEFAULT_DMIBAR | 0x0004, 0x01);
+ read32((void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0014)); // !!! = 0x8000007f
+ write32(0x80000019, (void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0014));
+ read32((void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0020)); // !!! = 0x01000000
+ write32(0x81000022, (void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0020));
+ read32((void *)(uintptr_t)(DEFAULT_DMIBAR | 0x002c)); // !!! = 0x02000000
+ write32(0x82000044, (void *)(uintptr_t)(DEFAULT_DMIBAR | 0x002c));
+ read32((void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0038)); // !!! = 0x07000080
+ write32(0x87000080, (void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0038));
+ read8((void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0004)); // !!! = 0x00
+ write8(0x01, (void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0004));
- read32 (DEFAULT_RCBA | 0x0050); // !!! = 0x01200654
- write32 (DEFAULT_RCBA | 0x0050, 0x01200654);
- read32 (DEFAULT_RCBA | 0x0050); // !!! = 0x01200654
- write32 (DEFAULT_RCBA | 0x0050, 0x012a0654);
- read32 (DEFAULT_RCBA | 0x0050); // !!! = 0x012a0654
- read8 (DEFAULT_RCBA | 0x1114); // !!! = 0x00
- write8 (DEFAULT_RCBA | 0x1114, 0x05);
- read32 (DEFAULT_RCBA | 0x2014); // !!! = 0x80000011
- write32 (DEFAULT_RCBA | 0x2014, 0x80000019);
- read32 (DEFAULT_RCBA | 0x2020); // !!! = 0x00000000
- write32 (DEFAULT_RCBA | 0x2020, 0x81000022);
- read32 (DEFAULT_RCBA | 0x2020); // !!! = 0x81000022
- read32 (DEFAULT_RCBA | 0x2030); // !!! = 0x00000000
- write32 (DEFAULT_RCBA | 0x2030, 0x82000044);
- read32 (DEFAULT_RCBA | 0x2030); // !!! = 0x82000044
- read32 (DEFAULT_RCBA | 0x2040); // !!! = 0x00000000
- write32 (DEFAULT_RCBA | 0x2040, 0x87000080);
- read32 (DEFAULT_RCBA | 0x0050); // !!! = 0x012a0654
- write32 (DEFAULT_RCBA | 0x0050, 0x812a0654);
- read32 (DEFAULT_RCBA | 0x0050); // !!! = 0x812a0654
- read16 (DEFAULT_RCBA | 0x201a); // !!! = 0x0000
- read16 (DEFAULT_RCBA | 0x2026); // !!! = 0x0000
- read16 (DEFAULT_RCBA | 0x2036); // !!! = 0x0000
- read16 (DEFAULT_RCBA | 0x2046); // !!! = 0x0000
- read16 (DEFAULT_DMIBAR | 0x001a); // !!! = 0x0000
- read16 (DEFAULT_DMIBAR | 0x0026); // !!! = 0x0000
- read16 (DEFAULT_DMIBAR | 0x0032); // !!! = 0x0000
- read16 (DEFAULT_DMIBAR | 0x003e); // !!! = 0x0000
+ read32((void *)(uintptr_t)(DEFAULT_RCBA | 0x0050)); // !!! = 0x01200654
+ write32(0x01200654, (void *)(uintptr_t)(DEFAULT_RCBA | 0x0050));
+ read32((void *)(uintptr_t)(DEFAULT_RCBA | 0x0050)); // !!! = 0x01200654
+ write32(0x012a0654, (void *)(uintptr_t)(DEFAULT_RCBA | 0x0050));
+ read32((void *)(uintptr_t)(DEFAULT_RCBA | 0x0050)); // !!! = 0x012a0654
+ read8((void *)(uintptr_t)(DEFAULT_RCBA | 0x1114)); // !!! = 0x00
+ write8(0x05, (void *)(uintptr_t)(DEFAULT_RCBA | 0x1114));
+ read32((void *)(uintptr_t)(DEFAULT_RCBA | 0x2014)); // !!! = 0x80000011
+ write32(0x80000019, (void *)(uintptr_t)(DEFAULT_RCBA | 0x2014));
+ read32((void *)(uintptr_t)(DEFAULT_RCBA | 0x2020)); // !!! = 0x00000000
+ write32(0x81000022, (void *)(uintptr_t)(DEFAULT_RCBA | 0x2020));
+ read32((void *)(uintptr_t)(DEFAULT_RCBA | 0x2020)); // !!! = 0x81000022
+ read32((void *)(uintptr_t)(DEFAULT_RCBA | 0x2030)); // !!! = 0x00000000
+ write32(0x82000044, (void *)(uintptr_t)(DEFAULT_RCBA | 0x2030));
+ read32((void *)(uintptr_t)(DEFAULT_RCBA | 0x2030)); // !!! = 0x82000044
+ read32((void *)(uintptr_t)(DEFAULT_RCBA | 0x2040)); // !!! = 0x00000000
+ write32(0x87000080, (void *)(uintptr_t)(DEFAULT_RCBA | 0x2040));
+ read32((void *)(uintptr_t)(DEFAULT_RCBA | 0x0050)); // !!! = 0x012a0654
+ write32(0x812a0654, (void *)(uintptr_t)(DEFAULT_RCBA | 0x0050));
+ read32((void *)(uintptr_t)(DEFAULT_RCBA | 0x0050)); // !!! = 0x812a0654
+ read16((void *)(uintptr_t)(DEFAULT_RCBA | 0x201a)); // !!! = 0x0000
+ read16((void *)(uintptr_t)(DEFAULT_RCBA | 0x2026)); // !!! = 0x0000
+ read16((void *)(uintptr_t)(DEFAULT_RCBA | 0x2036)); // !!! = 0x0000
+ read16((void *)(uintptr_t)(DEFAULT_RCBA | 0x2046)); // !!! = 0x0000
+ read16((void *)(uintptr_t)(DEFAULT_DMIBAR | 0x001a)); // !!! = 0x0000
+ read16((void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0026)); // !!! = 0x0000
+ read16((void *)(uintptr_t)(DEFAULT_DMIBAR | 0x0032)); // !!! = 0x0000
+ read16((void *)(uintptr_t)(DEFAULT_DMIBAR | 0x003e)); // !!! = 0x0000
}
void
@@ -292,21 +292,21 @@ early_pch_init_native (void)
pcie_write_config8 (SOUTHBRIDGE, 0xa6,
pcie_read_config8 (SOUTHBRIDGE, 0xa6) | 2);
- write32 (DEFAULT_RCBA | 0x2088, 0x00109000);
- read32 (DEFAULT_RCBA | 0x20ac); // !!! = 0x00000000
- write32 (DEFAULT_RCBA | 0x20ac, 0x40000000);
- write32 (DEFAULT_RCBA | 0x100c, 0x01110000);
- write8 (DEFAULT_RCBA | 0x2340, 0x1b);
- read32 (DEFAULT_RCBA | 0x2314); // !!! = 0x0a080000
- write32 (DEFAULT_RCBA | 0x2314, 0x0a280000);
- read32 (DEFAULT_RCBA | 0x2310); // !!! = 0xc809605b
- write32 (DEFAULT_RCBA | 0x2310, 0xa809605b);
- write32 (DEFAULT_RCBA | 0x2324, 0x00854c74);
- read8 (DEFAULT_RCBA | 0x0400); // !!! = 0x00
- read32 (DEFAULT_RCBA | 0x2310); // !!! = 0xa809605b
- write32 (DEFAULT_RCBA | 0x2310, 0xa809605b);
- read32 (DEFAULT_RCBA | 0x2310); // !!! = 0xa809605b
- write32 (DEFAULT_RCBA | 0x2310, 0xa809605b);
+ write32(0x00109000, (void *)(uintptr_t)(DEFAULT_RCBA | 0x2088));
+ read32((void *)(uintptr_t)(DEFAULT_RCBA | 0x20ac)); // !!! = 0x00000000
+ write32(0x40000000, (void *)(uintptr_t)(DEFAULT_RCBA | 0x20ac));
+ write32(0x01110000, (void *)(uintptr_t)(DEFAULT_RCBA | 0x100c));
+ write8(0x1b, (void *)(uintptr_t)(DEFAULT_RCBA | 0x2340));
+ read32((void *)(uintptr_t)(DEFAULT_RCBA | 0x2314)); // !!! = 0x0a080000
+ write32(0x0a280000, (void *)(uintptr_t)(DEFAULT_RCBA | 0x2314));
+ read32((void *)(uintptr_t)(DEFAULT_RCBA | 0x2310)); // !!! = 0xc809605b
+ write32(0xa809605b, (void *)(uintptr_t)(DEFAULT_RCBA | 0x2310));
+ write32(0x00854c74, (void *)(uintptr_t)(DEFAULT_RCBA | 0x2324));
+ read8((void *)(uintptr_t)(DEFAULT_RCBA | 0x0400)); // !!! = 0x00
+ read32((void *)(uintptr_t)(DEFAULT_RCBA | 0x2310)); // !!! = 0xa809605b
+ write32(0xa809605b, (void *)(uintptr_t)(DEFAULT_RCBA | 0x2310));
+ read32((void *)(uintptr_t)(DEFAULT_RCBA | 0x2310)); // !!! = 0xa809605b
+ write32(0xa809605b, (void *)(uintptr_t)(DEFAULT_RCBA | 0x2310));
write_2338 (0xea007f62, 0x00590133);
write_2338 (0xec007f62, 0x00590133);
diff --git a/src/southbridge/intel/bd82x6x/early_thermal.c b/src/southbridge/intel/bd82x6x/early_thermal.c
index 02ec9a7..cdce496 100644
--- a/src/southbridge/intel/bd82x6x/early_thermal.c
+++ b/src/southbridge/intel/bd82x6x/early_thermal.c
@@ -41,30 +41,31 @@ void early_thermal_init(void)
pci_read_config32(dev, 0x40) | 5);
- write16 (0x40000004, 0x3a2b);
- write8 (0x4000000c, 0xff);
- write8 (0x4000000d, 0x00);
- write8 (0x4000000e, 0x40);
- write8 (0x40000082, 0x00);
- write8 (0x40000001, 0xba);
+ write16(0x3a2b, (void *)(uintptr_t)(0x40000004));
+ write8(0xff, (void *)(uintptr_t)(0x4000000c));
+ write8(0x00, (void *)(uintptr_t)(0x4000000d));
+ write8(0x40, (void *)(uintptr_t)(0x4000000e));
+ write8(0x00, (void *)(uintptr_t)(0x40000082));
+ write8(0xba, (void *)(uintptr_t)(0x40000001));
/* Perform init. */
/* Configure TJmax. */
msr = rdmsr(MSR_TEMPERATURE_TARGET);
- write16(0x40000012, ((msr.lo >> 16) & 0xff) << 6);
+ write16(((msr.lo >> 16) & 0xff) << 6, (void *)(uintptr_t)(0x40000012));
/* Northbridge temperature slope and offset. */
- write16(0x40000016, 0x808c);
+ write16(0x808c, (void *)(uintptr_t)(0x40000016));
- write16 (0x40000014, 0xde87);
+ write16(0xde87, (void *)(uintptr_t)(0x40000014));
/* Enable thermal data reporting, processor, PCH and northbridge. */
- write16(0x4000001a, (read16(0x4000001a) & ~0xf) | 0x10f0);
+ write16((read16((void *)(uintptr_t)(0x4000001a)) & ~0xf) | 0x10f0,
+ (void *)(uintptr_t)(0x4000001a));
/* Disable temporary BAR. */
pci_write_config32(dev, 0x40,
pci_read_config32(dev, 0x40) & ~1);
pci_write_config32(dev, 0x40, 0);
- write32 (DEFAULT_RCBA | 0x38b0,
- (read32 (DEFAULT_RCBA | 0x38b0) & 0xffff8003) | 0x403c);
+ write32((read32((void *)(uintptr_t)(DEFAULT_RCBA | 0x38b0)) & 0xffff8003) | 0x403c,
+ (void *)(uintptr_t)(DEFAULT_RCBA | 0x38b0));
}
diff --git a/src/southbridge/intel/bd82x6x/early_usb_native.c b/src/southbridge/intel/bd82x6x/early_usb_native.c
index b1f8447..7f026e1 100644
--- a/src/southbridge/intel/bd82x6x/early_usb_native.c
+++ b/src/southbridge/intel/bd82x6x/early_usb_native.c
@@ -43,32 +43,36 @@ early_usb_init (const struct southbridge_usb_port *portmap)
/* Unlock registers. */
outw (inw (DEFAULT_PMBASE | 0x003c) | 2, DEFAULT_PMBASE | 0x003c);
for (i = 0; i < 14; i++)
- write32 (DEFAULT_RCBABASE | (0x3500 + 4 * i),
- currents[portmap[i].current]);
+ write32(currents[portmap[i].current],
+ (void *)(uintptr_t)(DEFAULT_RCBABASE | (0x3500 + 4 * i)));
for (i = 0; i < 10; i++)
- write32 (DEFAULT_RCBABASE | (0x3538 + 4 * i), 0);
+ write32(0,
+ (void *)(uintptr_t)(DEFAULT_RCBABASE | (0x3538 + 4 * i)));
for (i = 0; i < 8; i++)
- write32 (DEFAULT_RCBABASE | (0x3560 + 4 * i), rcba_dump[i]);
+ write32(rcba_dump[i],
+ (void *)(uintptr_t)(DEFAULT_RCBABASE | (0x3560 + 4 * i)));
for (i = 0; i < 8; i++)
- write32 (DEFAULT_RCBABASE | (0x3580 + 4 * i), 0);
+ write32(0,
+ (void *)(uintptr_t)(DEFAULT_RCBABASE | (0x3580 + 4 * i)));
reg32 = 0;
for (i = 0; i < 14; i++)
if (!portmap[i].enabled)
reg32 |= (1 << i);
- write32 (DEFAULT_RCBABASE | 0x359c, reg32);
+ write32(reg32, (void *)(uintptr_t)(DEFAULT_RCBABASE | 0x359c));
reg32 = 0;
for (i = 0; i < 8; i++)
if (portmap[i].enabled && portmap[i].oc_pin >= 0)
reg32 |= (1 << (i + 8 * portmap[i].oc_pin));
- write32 (DEFAULT_RCBABASE | 0x35a0, reg32);
+ write32(reg32, (void *)(uintptr_t)(DEFAULT_RCBABASE | 0x35a0));
reg32 = 0;
for (i = 8; i < 14; i++)
if (portmap[i].enabled && portmap[i].oc_pin >= 4)
reg32 |= (1 << (i - 8 + 8 * (portmap[i].oc_pin - 4)));
- write32 (DEFAULT_RCBABASE | 0x35a4, reg32);
+ write32(reg32, (void *)(uintptr_t)(DEFAULT_RCBABASE | 0x35a4));
for (i = 0; i < 22; i++)
- write32 (DEFAULT_RCBABASE | (0x35a8 + 4 * i), 0);
+ write32(0,
+ (void *)(uintptr_t)(DEFAULT_RCBABASE | (0x35a8 + 4 * i)));
pcie_write_config32 (PCI_DEV (0, 0x14, 0), 0xe4, 0x00000000);
diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c
index 901e71d..158abef 100644
--- a/src/southbridge/intel/bd82x6x/me.c
+++ b/src/southbridge/intel/bd82x6x/me.c
@@ -106,7 +106,7 @@ static void mei_dump(void *ptr, int dword, int offset, const char *type)
static inline void mei_read_dword_ptr(void *ptr, int offset)
{
- u32 dword = read32(mei_base_address + offset);
+ u32 dword = read32((void *)(uintptr_t)(mei_base_address + offset));
memcpy(ptr, &dword, sizeof(dword));
mei_dump(ptr, dword, offset, "READ");
}
@@ -115,7 +115,7 @@ static inline void mei_write_dword_ptr(void *ptr, int offset)
{
u32 dword = 0;
memcpy(&dword, ptr, sizeof(dword));
- write32(mei_base_address + offset, dword);
+ write32(dword, (void *)(uintptr_t)(mei_base_address + offset));
mei_dump(ptr, dword, offset, "WRITE");
}
@@ -145,13 +145,13 @@ static inline void read_me_csr(struct mei_csr *csr)
static inline void write_cb(u32 dword)
{
- write32(mei_base_address + MEI_H_CB_WW, dword);
+ write32(dword, (void *)(uintptr_t)(mei_base_address + MEI_H_CB_WW));
mei_dump(NULL, dword, MEI_H_CB_WW, "WRITE");
}
static inline u32 read_cb(void)
{
- u32 dword = read32(mei_base_address + MEI_ME_CB_RW);
+ u32 dword = read32((void *)(uintptr_t)(mei_base_address + MEI_ME_CB_RW));
mei_dump(NULL, dword, MEI_ME_CB_RW, "READ");
return dword;
}
diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c
index e25b3b8..7e57ae3 100644
--- a/src/southbridge/intel/bd82x6x/me_8.x.c
+++ b/src/southbridge/intel/bd82x6x/me_8.x.c
@@ -108,7 +108,7 @@ static void mei_dump(void *ptr, int dword, int offset, const char *type)
static inline void mei_read_dword_ptr(void *ptr, int offset)
{
- u32 dword = read32(mei_base_address + offset);
+ u32 dword = read32((void *)(uintptr_t)(mei_base_address + offset));
memcpy(ptr, &dword, sizeof(dword));
mei_dump(ptr, dword, offset, "READ");
}
@@ -117,7 +117,7 @@ static inline void mei_write_dword_ptr(void *ptr, int offset)
{
u32 dword = 0;
memcpy(&dword, ptr, sizeof(dword));
- write32(mei_base_address + offset, dword);
+ write32(dword, (void *)(uintptr_t)(mei_base_address + offset));
mei_dump(ptr, dword, offset, "WRITE");
}
@@ -147,13 +147,13 @@ static inline void read_me_csr(struct mei_csr *csr)
static inline void write_cb(u32 dword)
{
- write32(mei_base_address + MEI_H_CB_WW, dword);
+ write32(dword, (void *)(uintptr_t)(mei_base_address + MEI_H_CB_WW));
mei_dump(NULL, dword, MEI_H_CB_WW, "WRITE");
}
static inline u32 read_cb(void)
{
- u32 dword = read32(mei_base_address + MEI_ME_CB_RW);
+ u32 dword = read32((void *)(uintptr_t)(mei_base_address + MEI_ME_CB_RW));
mei_dump(NULL, dword, MEI_ME_CB_RW, "READ");
return dword;
}
diff --git a/src/southbridge/intel/bd82x6x/sata.c b/src/southbridge/intel/bd82x6x/sata.c
index cb5699e..79b067c 100644
--- a/src/southbridge/intel/bd82x6x/sata.c
+++ b/src/southbridge/intel/bd82x6x/sata.c
@@ -103,7 +103,7 @@ static void sata_init(struct device *dev)
abar = pci_read_config32(dev, PCI_BASE_ADDRESS_5);
printk(BIOS_DEBUG, "ABAR: %08X\n", abar);
/* CAP (HBA Capabilities) : enable power management */
- reg32 = read32(abar + 0x00);
+ reg32 = read32((void *)(uintptr_t)(abar + 0x00));
reg32 |= 0x0c006000; // set PSC+SSC+SALP+SSS
reg32 &= ~0x00020060; // clear SXS+EMS+PMS
/* Set ISS, if available */
@@ -113,19 +113,20 @@ static void sata_init(struct device *dev)
reg32 |= (config->sata_interface_speed_support & 0x03)
<< 20;
}
- write32(abar + 0x00, reg32);
+ write32(reg32, (void *)(uintptr_t)(abar + 0x00));
/* PI (Ports implemented) */
- write32(abar + 0x0c, config->sata_port_map);
- (void) read32(abar + 0x0c); /* Read back 1 */
- (void) read32(abar + 0x0c); /* Read back 2 */
+ write32(config->sata_port_map,
+ (void *)(uintptr_t)(abar + 0x0c));
+ (void) read32((void *)(uintptr_t)(abar + 0x0c)); /* Read back 1 */
+ (void) read32((void *)(uintptr_t)(abar + 0x0c)); /* Read back 2 */
/* CAP2 (HBA Capabilities Extended)*/
- reg32 = read32(abar + 0x24);
+ reg32 = read32((void *)(uintptr_t)(abar + 0x24));
reg32 &= ~0x00000002;
- write32(abar + 0x24, reg32);
+ write32(reg32, (void *)(uintptr_t)(abar + 0x24));
/* VSP (Vendor Specific Register */
- reg32 = read32(abar + 0xa0);
+ reg32 = read32((void *)(uintptr_t)(abar + 0xa0));
reg32 &= ~0x00000005;
- write32(abar + 0xa0, reg32);
+ write32(reg32, (void *)(uintptr_t)(abar + 0xa0));
} else {
/* IDE */
printk(BIOS_DEBUG, "SATA: Controller in plain mode.\n");
diff --git a/src/southbridge/intel/bd82x6x/usb_ehci.c b/src/southbridge/intel/bd82x6x/usb_ehci.c
index 9850fee..2be494c 100644
--- a/src/southbridge/intel/bd82x6x/usb_ehci.c
+++ b/src/southbridge/intel/bd82x6x/usb_ehci.c
@@ -66,8 +66,9 @@ static void usb_ehci_init(struct device *dev)
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
/* Number of ports and companion controllers. */
- reg32 = read32(res->base + 4);
- write32(res->base + 4, (reg32 & 0xfff00000) | 3);
+ reg32 = read32((void *)(uintptr_t)(res->base + 4));
+ write32((reg32 & 0xfff00000) | 3,
+ (void *)(uintptr_t)(res->base + 4));
}
/* Restore protection. */
diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c
index 48c72b7..fb274d4 100644
--- a/src/southbridge/intel/common/spi.c
+++ b/src/southbridge/intel/common/spi.c
@@ -198,7 +198,7 @@ enum {
static u8 readb_(const void *addr)
{
- u8 v = read8((unsigned long)addr);
+ u8 v = read8((void *)(uintptr_t)((unsigned long)addr));
printk(BIOS_DEBUG, "read %2.2x from %4.4x\n",
v, ((unsigned) addr & 0xffff) - 0xf020);
return v;
@@ -206,7 +206,7 @@ static u8 readb_(const void *addr)
static u16 readw_(const void *addr)
{
- u16 v = read16((unsigned long)addr);
+ u16 v = read16((void *)(uintptr_t)((unsigned long)addr));
printk(BIOS_DEBUG, "read %4.4x from %4.4x\n",
v, ((unsigned) addr & 0xffff) - 0xf020);
return v;
@@ -214,7 +214,7 @@ static u16 readw_(const void *addr)
static u32 readl_(const void *addr)
{
- u32 v = read32((unsigned long)addr);
+ u32 v = read32((void *)(uintptr_t)((unsigned long)addr));
printk(BIOS_DEBUG, "read %8.8x from %4.4x\n",
v, ((unsigned) addr & 0xffff) - 0xf020);
return v;
@@ -222,33 +222,33 @@ static u32 readl_(const void *addr)
static void writeb_(u8 b, const void *addr)
{
- write8((unsigned long)addr, b);
+ write8(b, (void *)(uintptr_t)((unsigned long)addr));
printk(BIOS_DEBUG, "wrote %2.2x to %4.4x\n",
b, ((unsigned) addr & 0xffff) - 0xf020);
}
static void writew_(u16 b, const void *addr)
{
- write16((unsigned long)addr, b);
+ write16(b, (void *)(uintptr_t)((unsigned long)addr));
printk(BIOS_DEBUG, "wrote %4.4x to %4.4x\n",
b, ((unsigned) addr & 0xffff) - 0xf020);
}
static void writel_(u32 b, const void *addr)
{
- write32((unsigned long)addr, b);
+ write32(b, (void *)(uintptr_t)((unsigned long)addr));
printk(BIOS_DEBUG, "wrote %8.8x to %4.4x\n",
b, ((unsigned) addr & 0xffff) - 0xf020);
}
#else /* CONFIG_DEBUG_SPI_FLASH ^^^ enabled vvv NOT enabled */
-#define readb_(a) read8((uint32_t)a)
-#define readw_(a) read16((uint32_t)a)
-#define readl_(a) read32((uint32_t)a)
-#define writeb_(val, addr) write8((uint32_t)addr, val)
-#define writew_(val, addr) write16((uint32_t)addr, val)
-#define writel_(val, addr) write32((uint32_t)addr, val)
+#define readb_(a) read8((void *)(uintptr_t)((uint32_t)a))
+#define readw_(a) read16((void *)(uintptr_t)((uint32_t)a))
+#define readl_(a) read32((void *)(uintptr_t)((uint32_t)a))
+#define writeb_(val, addr) write8(val, (void *)(uintptr_t)((uint32_t)addr))
+#define writew_(val, addr) write16(val, (void *)(uintptr_t)((uint32_t)addr))
+#define writel_(val, addr) write32(val, (void *)(uintptr_t)((uint32_t)addr))
#endif /* CONFIG_DEBUG_SPI_FLASH ^^^ NOT enabled */
diff --git a/src/southbridge/intel/fsp_bd82x6x/azalia.c b/src/southbridge/intel/fsp_bd82x6x/azalia.c
index 7a280c5..b09636f 100644
--- a/src/southbridge/intel/fsp_bd82x6x/azalia.c
+++ b/src/southbridge/intel/fsp_bd82x6x/azalia.c
@@ -41,10 +41,10 @@ static int set_bits(u32 port, u32 mask, u32 val)
/* Write (val & mask) to port */
val &= mask;
- reg32 = read32(port);
+ reg32 = read32((void *)(uintptr_t)(port));
reg32 &= ~mask;
reg32 |= val;
- write32(port, reg32);
+ write32(reg32, (void *)(uintptr_t)(port));
/* Wait for readback of register to
* match what was just written to it
@@ -53,7 +53,7 @@ static int set_bits(u32 port, u32 mask, u32 val)
do {
/* Wait 1ms based on BKDG wait time */
mdelay(1);
- reg32 = read32(port);
+ reg32 = read32((void *)(uintptr_t)(port));
reg32 &= mask;
} while ((reg32 != val) && --count);
@@ -72,10 +72,11 @@ static int codec_detect(u32 base)
goto no_codec;
/* Write back the value once reset bit is set. */
- write16(base + 0x0, read16(base + 0x0));
+ write16(read16((void *)(uintptr_t)(base + 0x0)),
+ (void *)(uintptr_t)(base + 0x0));
/* Read in Codec location (BAR + 0xe)[2..0]*/
- reg8 = read8(base + 0xe);
+ reg8 = read8((void *)(uintptr_t)(base + 0xe));
reg8 &= 0x0f;
if (!reg8)
goto no_codec;
@@ -126,7 +127,7 @@ static int wait_for_ready(u32 base)
int timeout = 50;
while(timeout--) {
- u32 reg32 = read32(base + HDA_ICII_REG);
+ u32 reg32 = read32((void *)(uintptr_t)(base + HDA_ICII_REG));
if (!(reg32 & HDA_ICII_BUSY))
return 0;
udelay(1);
@@ -146,16 +147,16 @@ static int wait_for_valid(u32 base)
u32 reg32;
/* Send the verb to the codec */
- reg32 = read32(base + HDA_ICII_REG);
+ reg32 = read32((void *)(uintptr_t)(base + HDA_ICII_REG));
reg32 |= HDA_ICII_BUSY | HDA_ICII_VALID;
- write32(base + HDA_ICII_REG, reg32);
+ write32(reg32, (void *)(uintptr_t)(base + HDA_ICII_REG));
/* Use a 50 usec timeout - the Linux kernel uses the
* same duration */
int timeout = 50;
while(timeout--) {
- reg32 = read32(base + HDA_ICII_REG);
+ reg32 = read32((void *)(uintptr_t)(base + HDA_ICII_REG));
if ((reg32 & (HDA_ICII_VALID | HDA_ICII_BUSY)) ==
HDA_ICII_VALID)
return 0;
@@ -181,14 +182,14 @@ static void codec_init(struct device *dev, u32 base, int addr)
}
reg32 = (addr << 28) | 0x000f0000;
- write32(base + 0x60, reg32);
+ write32(reg32, (void *)(uintptr_t)(base + 0x60));
if (wait_for_valid(base) == -1) {
printk(BIOS_DEBUG, " codec not valid.\n");
return;
}
- reg32 = read32(base + 0x64);
+ reg32 = read32((void *)(uintptr_t)(base + 0x64));
/* 2 */
printk(BIOS_DEBUG, "Azalia: codec viddid: %08x\n", reg32);
@@ -205,7 +206,7 @@ static void codec_init(struct device *dev, u32 base, int addr)
if (wait_for_ready(base) == -1)
return;
- write32(base + 0x60, verb[i]);
+ write32(verb[i], (void *)(uintptr_t)(base + 0x60));
if (wait_for_valid(base) == -1)
return;
@@ -225,7 +226,7 @@ static void codecs_init(struct device *dev, u32 base, u32 codec_mask)
if (wait_for_ready(base) == -1)
return;
- write32(base + 0x60, pc_beep_verbs[i]);
+ write32(pc_beep_verbs[i], (void *)(uintptr_t)(base + 0x60));
if (wait_for_valid(base) == -1)
return;
@@ -314,9 +315,9 @@ static void azalia_init(struct device *dev)
pci_write_config8(dev, 0x3c, 0x0a); // unused?
/* Codec Initialization Programming Sequence */
- reg32 = read32(base + 0x08);
+ reg32 = read32((void *)(uintptr_t)(base + 0x08));
reg32 |= (1 << 0);
- write32(base + 0x08, reg32);
+ write32(reg32, (void *)(uintptr_t)(base + 0x08));
//
reg8 = pci_read_config8(dev, 0x40); // Audio Control
diff --git a/src/southbridge/intel/fsp_bd82x6x/me.c b/src/southbridge/intel/fsp_bd82x6x/me.c
index 5326eb5..34e39b5 100644
--- a/src/southbridge/intel/fsp_bd82x6x/me.c
+++ b/src/southbridge/intel/fsp_bd82x6x/me.c
@@ -105,7 +105,7 @@ static void mei_dump(void *ptr, int dword, int offset, const char *type)
static inline void mei_read_dword_ptr(void *ptr, int offset)
{
- u32 dword = read32(mei_base_address + offset);
+ u32 dword = read32((void *)(uintptr_t)(mei_base_address + offset));
memcpy(ptr, &dword, sizeof(dword));
mei_dump(ptr, dword, offset, "READ");
}
@@ -114,7 +114,7 @@ static inline void mei_write_dword_ptr(void *ptr, int offset)
{
u32 dword = 0;
memcpy(&dword, ptr, sizeof(dword));
- write32(mei_base_address + offset, dword);
+ write32(dword, (void *)(uintptr_t)(mei_base_address + offset));
mei_dump(ptr, dword, offset, "WRITE");
}
@@ -144,13 +144,13 @@ static inline void read_me_csr(struct mei_csr *csr)
static inline void write_cb(u32 dword)
{
- write32(mei_base_address + MEI_H_CB_WW, dword);
+ write32(dword, (void *)(uintptr_t)(mei_base_address + MEI_H_CB_WW));
mei_dump(NULL, dword, MEI_H_CB_WW, "WRITE");
}
static inline u32 read_cb(void)
{
- u32 dword = read32(mei_base_address + MEI_ME_CB_RW);
+ u32 dword = read32((void *)(uintptr_t)(mei_base_address + MEI_ME_CB_RW));
mei_dump(NULL, dword, MEI_ME_CB_RW, "READ");
return dword;
}
diff --git a/src/southbridge/intel/fsp_bd82x6x/me_8.x.c b/src/southbridge/intel/fsp_bd82x6x/me_8.x.c
index d673ac7..30416c3 100644
--- a/src/southbridge/intel/fsp_bd82x6x/me_8.x.c
+++ b/src/southbridge/intel/fsp_bd82x6x/me_8.x.c
@@ -106,7 +106,7 @@ static void mei_dump(void *ptr, int dword, int offset, const char *type)
static inline void mei_read_dword_ptr(void *ptr, int offset)
{
- u32 dword = read32(mei_base_address + offset);
+ u32 dword = read32((void *)(uintptr_t)(mei_base_address + offset));
memcpy(ptr, &dword, sizeof(dword));
mei_dump(ptr, dword, offset, "READ");
}
@@ -115,7 +115,7 @@ static inline void mei_write_dword_ptr(void *ptr, int offset)
{
u32 dword = 0;
memcpy(&dword, ptr, sizeof(dword));
- write32(mei_base_address + offset, dword);
+ write32(dword, (void *)(uintptr_t)(mei_base_address + offset));
mei_dump(ptr, dword, offset, "WRITE");
}
@@ -145,13 +145,13 @@ static inline void read_me_csr(struct mei_csr *csr)
static inline void write_cb(u32 dword)
{
- write32(mei_base_address + MEI_H_CB_WW, dword);
+ write32(dword, (void *)(uintptr_t)(mei_base_address + MEI_H_CB_WW));
mei_dump(NULL, dword, MEI_H_CB_WW, "WRITE");
}
static inline u32 read_cb(void)
{
- u32 dword = read32(mei_base_address + MEI_ME_CB_RW);
+ u32 dword = read32((void *)(uintptr_t)(mei_base_address + MEI_ME_CB_RW));
mei_dump(NULL, dword, MEI_ME_CB_RW, "READ");
return dword;
}
diff --git a/src/southbridge/intel/fsp_bd82x6x/sata.c b/src/southbridge/intel/fsp_bd82x6x/sata.c
index 591bdbc..eebbef6 100644
--- a/src/southbridge/intel/fsp_bd82x6x/sata.c
+++ b/src/southbridge/intel/fsp_bd82x6x/sata.c
@@ -69,9 +69,9 @@ static void sata_init(struct device *dev)
abar = pci_read_config32(dev, PCI_BASE_ADDRESS_5);
printk(BIOS_DEBUG, "ABAR: %08X\n", abar);
/* Enable AHCI Mode */
- reg32 = read32(abar + 0x04);
+ reg32 = read32((void *)(uintptr_t)(abar + 0x04));
reg32 |= (1 << 31);
- write32(abar + 0x04, reg32);
+ write32(reg32, (void *)(uintptr_t)(abar + 0x04));
} else {
printk(BIOS_DEBUG, "SATA: Controller in plain mode.\n");
diff --git a/src/southbridge/intel/fsp_rangeley/early_init.c b/src/southbridge/intel/fsp_rangeley/early_init.c
index 844f4b8..d73eed7 100644
--- a/src/southbridge/intel/fsp_rangeley/early_init.c
+++ b/src/southbridge/intel/fsp_rangeley/early_init.c
@@ -41,8 +41,8 @@ static void rangeley_setup_bars(void)
printk(BIOS_DEBUG, "Disabling Watchdog timer...");
/* Disable the watchdog reboot and turn off the watchdog timer */
- write8(DEFAULT_PBASE + PMC_CFG, read8(DEFAULT_PBASE + PMC_CFG) |
- NO_REBOOT); // disable reboot on timer trigger
+ write8(read8((void *)(uintptr_t)(DEFAULT_PBASE + PMC_CFG)) | NO_REBOOT,
+ (void *)(uintptr_t)(DEFAULT_PBASE + PMC_CFG)); // disable reboot on timer trigger
outw(DEFAULT_ABASE + TCO1_CNT, inw(DEFAULT_ABASE + TCO1_CNT) |
TCO_TMR_HALT); // disable watchdog timer
@@ -54,7 +54,7 @@ static void reset_rtc(void)
{
uint32_t pbase = pci_read_config32(LPC_BDF, PBASE) &
0xfffffff0;
- uint32_t gen_pmcon1 = read32(pbase + GEN_PMCON1);
+ uint32_t gen_pmcon1 = read32((void *)(uintptr_t)(pbase + GEN_PMCON1));
int rtc_failed = !!(gen_pmcon1 & RPS);
if (rtc_failed) {
@@ -63,7 +63,8 @@ static void reset_rtc(void)
coreboot_dmi_date);
/* Clear the power failure flag */
- write32(DEFAULT_PBASE + GEN_PMCON1, gen_pmcon1 & ~RPS);
+ write32(gen_pmcon1 & ~RPS,
+ (void *)(uintptr_t)(DEFAULT_PBASE + GEN_PMCON1));
}
cmos_init(rtc_failed);
diff --git a/src/southbridge/intel/fsp_rangeley/gpio.c b/src/southbridge/intel/fsp_rangeley/gpio.c
index 8569b96..0556a79 100644
--- a/src/southbridge/intel/fsp_rangeley/gpio.c
+++ b/src/southbridge/intel/fsp_rangeley/gpio.c
@@ -67,30 +67,42 @@ void setup_soc_gpios(const struct soc_gpio_map *gpio)
/* GPIO PAD settings */
/* CFIO Core Well Set 1 */
if ((gpio->core.cfio_init != NULL) || (gpio->core.cfio_entrynum != 0)) {
- write32(cfiobase + 0x0700, (u32)0x01001002);
+ write32((u32)0x01001002,
+ (void *)(uintptr_t)(cfiobase + 0x0700));
for(cfio_cnt = 0; cfio_cnt < gpio->core.cfio_entrynum; cfio_cnt++) {
if (!((u32)gpio->core.cfio_init[cfio_cnt].pad_conf_0))
continue;
- write32(cfiobase + CFIO_PAD_CONF0 + (16*cfio_cnt), (u32)gpio->core.cfio_init[cfio_cnt].pad_conf_0);
- write32(cfiobase + CFIO_PAD_CONF1 + (16*cfio_cnt), (u32)gpio->core.cfio_init[cfio_cnt].pad_conf_1);
- write32(cfiobase + CFIO_PAD_VAL + (16*cfio_cnt), (u32)gpio->core.cfio_init[cfio_cnt].pad_val);
- write32(cfiobase + CFIO_PAD_DFT + (16*cfio_cnt), (u32)gpio->core.cfio_init[cfio_cnt].pad_dft);
+ write32((u32)gpio->core.cfio_init[cfio_cnt].pad_conf_0,
+ (void *)(uintptr_t)(cfiobase + CFIO_PAD_CONF0 + (16 * cfio_cnt)));
+ write32((u32)gpio->core.cfio_init[cfio_cnt].pad_conf_1,
+ (void *)(uintptr_t)(cfiobase + CFIO_PAD_CONF1 + (16 * cfio_cnt)));
+ write32((u32)gpio->core.cfio_init[cfio_cnt].pad_val,
+ (void *)(uintptr_t)(cfiobase + CFIO_PAD_VAL + (16 * cfio_cnt)));
+ write32((u32)gpio->core.cfio_init[cfio_cnt].pad_dft,
+ (void *)(uintptr_t)(cfiobase + CFIO_PAD_DFT + (16 * cfio_cnt)));
}
- write32(cfiobase + 0x0700, (u32)0x01041002);
+ write32((u32)0x01041002,
+ (void *)(uintptr_t)(cfiobase + 0x0700));
}
/* CFIO SUS Well Set 1 */
if ((gpio->sus.cfio_init != NULL) || (gpio->sus.cfio_entrynum != 0)) {
- write32(cfiobase + 0x1700, (u32)0x01001002);
+ write32((u32)0x01001002,
+ (void *)(uintptr_t)(cfiobase + 0x1700));
for(cfio_cnt = 0; cfio_cnt < gpio->sus.cfio_entrynum; cfio_cnt++) {
if (!((u32)gpio->sus.cfio_init[cfio_cnt].pad_conf_0))
continue;
- write32(cfiobase + CFIO_PAD_CONF0 + 0x1000 + (16*cfio_cnt), (u32)gpio->sus.cfio_init[cfio_cnt].pad_conf_0);
- write32(cfiobase + CFIO_PAD_CONF1 + 0x1000 + (16*cfio_cnt), (u32)gpio->sus.cfio_init[cfio_cnt].pad_conf_1);
- write32(cfiobase + CFIO_PAD_VAL + 0x1000 + (16*cfio_cnt), (u32)gpio->sus.cfio_init[cfio_cnt].pad_val);
- write32(cfiobase + CFIO_PAD_DFT + 0x1000 + (16*cfio_cnt), (u32)gpio->sus.cfio_init[cfio_cnt].pad_dft);
+ write32((u32)gpio->sus.cfio_init[cfio_cnt].pad_conf_0,
+ (void *)(uintptr_t)(cfiobase + CFIO_PAD_CONF0 + 0x1000 + (16 * cfio_cnt)));
+ write32((u32)gpio->sus.cfio_init[cfio_cnt].pad_conf_1,
+ (void *)(uintptr_t)(cfiobase + CFIO_PAD_CONF1 + 0x1000 + (16 * cfio_cnt)));
+ write32((u32)gpio->sus.cfio_init[cfio_cnt].pad_val,
+ (void *)(uintptr_t)(cfiobase + CFIO_PAD_VAL + 0x1000 + (16 * cfio_cnt)));
+ write32((u32)gpio->sus.cfio_init[cfio_cnt].pad_dft,
+ (void *)(uintptr_t)(cfiobase + CFIO_PAD_DFT + 0x1000 + (16 * cfio_cnt)));
}
- write32(cfiobase + 0x1700, (u32)0x01041002);
+ write32((u32)0x01041002,
+ (void *)(uintptr_t)(cfiobase + 0x1700));
}
}
diff --git a/src/southbridge/intel/fsp_rangeley/lpc.c b/src/southbridge/intel/fsp_rangeley/lpc.c
index 9644067..ceb3959 100644
--- a/src/southbridge/intel/fsp_rangeley/lpc.c
+++ b/src/southbridge/intel/fsp_rangeley/lpc.c
@@ -58,9 +58,9 @@ static void soc_enable_apic(struct device *dev)
* Enable ACPI I/O and power management.
* Set SCI IRQ to IRQ9
*/
- write32(ilb_base + ILB_OIC, 0x100); /* AEN */
- reg32 = read32(ilb_base + ILB_OIC); /* Read back per BWG */
- write32(ilb_base + ILB_ACTL, 0); /* ACTL bit 2:0 SCIS IRQ9 */
+ write32(0x100, (void *)(uintptr_t)(ilb_base + ILB_OIC)); /* AEN */
+ reg32 = read32((void *)(uintptr_t)(ilb_base + ILB_OIC)); /* Read back per BWG */
+ write32(0, (void *)(uintptr_t)(ilb_base + ILB_ACTL)); /* ACTL bit 2:0 SCIS IRQ9 */
*ioapic_index = 0;
*ioapic_data = (1 << 25);
@@ -96,10 +96,10 @@ static void soc_enable_serial_irqs(struct device *dev)
ibase = pci_read_config32(dev, IBASE) & ~0xF;
/* Set packet length and toggle silent mode bit for one frame. */
- write8(ibase + ILB_SERIRQ_CNTL, (1 << 7));
+ write8((1 << 7), (void *)(uintptr_t)(ibase + ILB_SERIRQ_CNTL));
#if !CONFIG_SERIRQ_CONTINUOUS_MODE
- write8(ibase + ILB_SERIRQ_CNTL, 0);
+ write8(0, (void *)(uintptr_t)(ibase + ILB_SERIRQ_CNTL));
#endif
}
@@ -217,7 +217,8 @@ static void soc_pirq_init(device_t dev)
"PIRQ\tA \tB \tC \tD \tE \tF \tG \tH\n"
"IRQ ");
for (i = 0; i < NUM_PIRQS; i++) {
- write8(pr_base + i*sizeof(ir->pic[i]), ir->pic[i]);
+ write8(ir->pic[i],
+ (void *)(uintptr_t)(pr_base + i * sizeof(ir->pic[i])));
printk(BIOS_SPEW, "\t%d", ir->pic[i]);
}
printk(BIOS_SPEW, "\n\n");
@@ -226,7 +227,8 @@ static void soc_pirq_init(device_t dev)
printk(BIOS_SPEW, "\t\t\tPIRQ[A-H] routed to each INT_PIN[A-D]\n"
"Dev\tINTA (IRQ)\tINTB (IRQ)\tINTC (IRQ)\tINTD (IRQ)\n");
for (i = 0; i < NUM_OF_PCI_DEVS; i++) {
- write16(ir_base + i*sizeof(ir->pcidev[i]), ir->pcidev[i]);
+ write16(ir->pcidev[i],
+ (void *)(uintptr_t)(ir_base + i * sizeof(ir->pcidev[i])));
/* If the entry is more than just 0, print it out */
if(ir->pcidev[i]) {
@@ -240,7 +242,8 @@ static void soc_pirq_init(device_t dev)
}
/* Route SCI to IRQ9 */
- write32(actl, (read32(actl) & ~SCIS_MASK) | SCIS_IRQ9);
+ write32((read32((void *)(uintptr_t)(actl)) & ~SCIS_MASK) | SCIS_IRQ9,
+ (void *)(uintptr_t)(actl));
printk(BIOS_SPEW, "Finished writing IRQ assignments\n");
/* Write IRQ assignments to PCI config space */
@@ -293,10 +296,10 @@ static void soc_power_options(device_t dev)
/* Disable the HPET, Clear the counter, and re-enable it. */
static void enable_hpet(void)
{
- write8(HPET_GCFG, 0x00);
- write32(HPET_MCV, 0x00000000);
- write32(HPET_MCV + 0x04, 0x00000000);
- write8(HPET_GCFG, 0x01);
+ write8(0x00, (void *)(uintptr_t)(HPET_GCFG));
+ write32(0x00000000, (void *)(uintptr_t)(HPET_MCV));
+ write32(0x00000000, (void *)(uintptr_t)(HPET_MCV + 0x04));
+ write8(0x01, (void *)(uintptr_t)(HPET_GCFG));
}
static void soc_disable_smm_only_flashing(struct device *dev)
diff --git a/src/southbridge/intel/fsp_rangeley/romstage.c b/src/southbridge/intel/fsp_rangeley/romstage.c
index fd8b3b2..6242063 100644
--- a/src/southbridge/intel/fsp_rangeley/romstage.c
+++ b/src/southbridge/intel/fsp_rangeley/romstage.c
@@ -70,9 +70,10 @@ void main(FSP_INFO_HEADER *fsp_info_header)
get_func_disables(&fd_mask);
if (fd_mask != 0) {
- write32(func_dis, read32(func_dis) | fd_mask);
+ write32(read32((void *)(uintptr_t)(func_dis)) | fd_mask,
+ (void *)(uintptr_t)(func_dis));
/* Ensure posted write hits. */
- read32(func_dis);
+ read32((void *)(uintptr_t)(func_dis));
}
/*
diff --git a/src/southbridge/intel/fsp_rangeley/sata.c b/src/southbridge/intel/fsp_rangeley/sata.c
index f672e4c..b1a34c0 100644
--- a/src/southbridge/intel/fsp_rangeley/sata.c
+++ b/src/southbridge/intel/fsp_rangeley/sata.c
@@ -78,9 +78,9 @@ static void sata_init(struct device *dev)
printk(BIOS_DEBUG, "ABAR: %08X\n", abar);
/* Enable AHCI Mode */
- reg32 = read32(abar + 0x04);
+ reg32 = read32((void *)(uintptr_t)(abar + 0x04));
reg32 |= (1 << 31);
- write32(abar + 0x04, reg32);
+ write32(reg32, (void *)(uintptr_t)(abar + 0x04));
} else {
printk(BIOS_DEBUG, "SATA: Controller in plain mode.\n");
}
diff --git a/src/southbridge/intel/fsp_rangeley/spi.c b/src/southbridge/intel/fsp_rangeley/spi.c
index ee22019..291d953 100644
--- a/src/southbridge/intel/fsp_rangeley/spi.c
+++ b/src/southbridge/intel/fsp_rangeley/spi.c
@@ -231,7 +231,7 @@ enum {
static u8 readb_(const void *addr)
{
- u8 v = read8((unsigned long)addr);
+ u8 v = read8((void *)(uintptr_t)((unsigned long)addr));
printk(BIOS_DEBUG, "read %2.2x from %4.4x\n",
v, ((unsigned) addr & 0xffff) - 0xf020);
return v;
@@ -239,7 +239,7 @@ static u8 readb_(const void *addr)
static u16 readw_(const void *addr)
{
- u16 v = read16((unsigned long)addr);
+ u16 v = read16((void *)(uintptr_t)((unsigned long)addr));
printk(BIOS_DEBUG, "read %4.4x from %4.4x\n",
v, ((unsigned) addr & 0xffff) - 0xf020);
return v;
@@ -247,7 +247,7 @@ static u16 readw_(const void *addr)
static u32 readl_(const void *addr)
{
- u32 v = read32((unsigned long)addr);
+ u32 v = read32((void *)(uintptr_t)((unsigned long)addr));
printk(BIOS_DEBUG, "read %8.8x from %4.4x\n",
v, ((unsigned) addr & 0xffff) - 0xf020);
return v;
@@ -255,33 +255,33 @@ static u32 readl_(const void *addr)
static void writeb_(u8 b, const void *addr)
{
- write8((unsigned long)addr, b);
+ write8(b, (void *)(uintptr_t)((unsigned long)addr));
printk(BIOS_DEBUG, "wrote %2.2x to %4.4x\n",
b, ((unsigned) addr & 0xffff) - 0xf020);
}
static void writew_(u16 b, const void *addr)
{
- write16((unsigned long)addr, b);
+ write16(b, (void *)(uintptr_t)((unsigned long)addr));
printk(BIOS_DEBUG, "wrote %4.4x to %4.4x\n",
b, ((unsigned) addr & 0xffff) - 0xf020);
}
static void writel_(u32 b, const void *addr)
{
- write32((unsigned long)addr, b);
+ write32(b, (void *)(uintptr_t)((unsigned long)addr));
printk(BIOS_DEBUG, "wrote %8.8x to %4.4x\n",
b, ((unsigned) addr & 0xffff) - 0xf020);
}
#else /* CONFIG_DEBUG_SPI_FLASH ^^^ enabled vvv NOT enabled */
-#define readb_(a) read8((uint32_t)a)
-#define readw_(a) read16((uint32_t)a)
-#define readl_(a) read32((uint32_t)a)
-#define writeb_(val, addr) write8((uint32_t)addr, val)
-#define writew_(val, addr) write16((uint32_t)addr, val)
-#define writel_(val, addr) write32((uint32_t)addr, val)
+#define readb_(a) read8((void *)(uintptr_t)((uint32_t)a))
+#define readw_(a) read16((void *)(uintptr_t)((uint32_t)a))
+#define readl_(a) read32((void *)(uintptr_t)((uint32_t)a))
+#define writeb_(val, addr) write8(val, (void *)(uintptr_t)((uint32_t)addr))
+#define writew_(val, addr) write16(val, (void *)(uintptr_t)((uint32_t)addr))
+#define writel_(val, addr) write32(val, (void *)(uintptr_t)((uint32_t)addr))
#endif /* CONFIG_DEBUG_SPI_FLASH ^^^ NOT enabled */
diff --git a/src/southbridge/intel/i82801gx/azalia.c b/src/southbridge/intel/i82801gx/azalia.c
index f6628e7..81d2bfc 100644
--- a/src/southbridge/intel/i82801gx/azalia.c
+++ b/src/southbridge/intel/i82801gx/azalia.c
@@ -41,10 +41,10 @@ static int set_bits(u32 port, u32 mask, u32 val)
/* Write (val & mask) to port */
val &= mask;
- reg32 = read32(port);
+ reg32 = read32((void *)(uintptr_t)(port));
reg32 &= ~mask;
reg32 |= val;
- write32(port, reg32);
+ write32(reg32, (void *)(uintptr_t)(port));
/* Wait for readback of register to
* match what was just written to it
@@ -53,7 +53,7 @@ static int set_bits(u32 port, u32 mask, u32 val)
do {
/* Wait 1ms based on BKDG wait time */
mdelay(1);
- reg32 = read32(port);
+ reg32 = read32((void *)(uintptr_t)(port));
reg32 &= mask;
} while ((reg32 != val) && --count);
@@ -76,7 +76,7 @@ static int codec_detect(u32 base)
goto no_codec;
/* Read in Codec location (BAR + 0xe)[2..0]*/
- reg32 = read32(base + 0xe);
+ reg32 = read32((void *)(uintptr_t)(base + 0xe));
reg32 &= 0x0f;
if (!reg32)
goto no_codec;
@@ -122,7 +122,7 @@ static int wait_for_ready(u32 base)
int timeout = 50;
while(timeout--) {
- u32 reg32 = read32(base + HDA_ICII_REG);
+ u32 reg32 = read32((void *)(uintptr_t)(base + HDA_ICII_REG));
if (!(reg32 & HDA_ICII_BUSY))
return 0;
udelay(1);
@@ -142,16 +142,16 @@ static int wait_for_valid(u32 base)
u32 reg32;
/* Send the verb to the codec */
- reg32 = read32(base + 0x68);
+ reg32 = read32((void *)(uintptr_t)(base + 0x68));
reg32 |= (1 << 0) | (1 << 1);
- write32(base + 0x68, reg32);
+ write32(reg32, (void *)(uintptr_t)(base + 0x68));
/* Use a 50 usec timeout - the Linux kernel uses the
* same duration */
int timeout = 50;
while(timeout--) {
- reg32 = read32(base + HDA_ICII_REG);
+ reg32 = read32((void *)(uintptr_t)(base + HDA_ICII_REG));
if ((reg32 & (HDA_ICII_VALID | HDA_ICII_BUSY)) ==
HDA_ICII_VALID)
return 0;
@@ -175,12 +175,12 @@ static void codec_init(struct device *dev, u32 base, int addr)
return;
reg32 = (addr << 28) | 0x000f0000;
- write32(base + 0x60, reg32);
+ write32(reg32, (void *)(uintptr_t)(base + 0x60));
if (wait_for_valid(base) == -1)
return;
- reg32 = read32(base + 0x64);
+ reg32 = read32((void *)(uintptr_t)(base + 0x64));
/* 2 */
printk(BIOS_DEBUG, "Azalia: codec viddid: %08x\n", reg32);
@@ -197,7 +197,7 @@ static void codec_init(struct device *dev, u32 base, int addr)
if (wait_for_ready(base) == -1)
return;
- write32(base + 0x60, verb[i]);
+ write32(verb[i], (void *)(uintptr_t)(base + 0x60));
if (wait_for_valid(base) == -1)
return;
diff --git a/src/southbridge/intel/i82801gx/usb_ehci.c b/src/southbridge/intel/i82801gx/usb_ehci.c
index bb176c7..ac6c03e 100644
--- a/src/southbridge/intel/i82801gx/usb_ehci.c
+++ b/src/southbridge/intel/i82801gx/usb_ehci.c
@@ -51,8 +51,8 @@ static void usb_ehci_init(struct device *dev)
/* Clear any pending port changes */
res = find_resource(dev, 0x10);
base = res->base;
- reg32 = read32(base + 0x24) | (1 << 2);
- write32(base + 0x24, reg32);
+ reg32 = read32((void *)(uintptr_t)(base + 0x24)) | (1 << 2);
+ write32(reg32, (void *)(uintptr_t)(base + 0x24));
/* workaround */
reg8 = pci_read_config8(dev, 0x84);
diff --git a/src/southbridge/intel/i82801ix/hdaudio.c b/src/southbridge/intel/i82801ix/hdaudio.c
index dd817b9..3ad670d 100644
--- a/src/southbridge/intel/i82801ix/hdaudio.c
+++ b/src/southbridge/intel/i82801ix/hdaudio.c
@@ -42,10 +42,10 @@ static int set_bits(u32 port, u32 mask, u32 val)
/* Write (val & mask) to port */
val &= mask;
- reg32 = read32(port);
+ reg32 = read32((void *)(uintptr_t)(port));
reg32 &= ~mask;
reg32 |= val;
- write32(port, reg32);
+ write32(reg32, (void *)(uintptr_t)(port));
/* Wait for readback of register to
* match what was just written to it
@@ -54,7 +54,7 @@ static int set_bits(u32 port, u32 mask, u32 val)
do {
/* Wait 1ms based on BKDG wait time */
mdelay(1);
- reg32 = read32(port);
+ reg32 = read32((void *)(uintptr_t)(port));
reg32 &= mask;
} while ((reg32 != val) && --count);
@@ -77,7 +77,7 @@ static int codec_detect(u32 base)
goto no_codec;
/* Read in Codec location (BAR + 0xe)[2..0]*/
- reg32 = read32(base + 0xe);
+ reg32 = read32((void *)(uintptr_t)(base + 0xe));
reg32 &= 0x0f;
if (!reg32)
goto no_codec;
@@ -123,7 +123,7 @@ static int wait_for_ready(u32 base)
int timeout = 50;
while(timeout--) {
- u32 reg32 = read32(base + HDA_ICII_REG);
+ u32 reg32 = read32((void *)(uintptr_t)(base + HDA_ICII_REG));
if (!(reg32 & HDA_ICII_BUSY))
return 0;
udelay(1);
@@ -143,16 +143,16 @@ static int wait_for_valid(u32 base)
u32 reg32;
/* Send the verb to the codec */
- reg32 = read32(base + 0x68);
+ reg32 = read32((void *)(uintptr_t)(base + 0x68));
reg32 |= (1 << 0) | (1 << 1);
- write32(base + 0x68, reg32);
+ write32(reg32, (void *)(uintptr_t)(base + 0x68));
/* Use a 50 usec timeout - the Linux kernel uses the
* same duration */
int timeout = 50;
while(timeout--) {
- reg32 = read32(base + HDA_ICII_REG);
+ reg32 = read32((void *)(uintptr_t)(base + HDA_ICII_REG));
if ((reg32 & (HDA_ICII_VALID | HDA_ICII_BUSY)) ==
HDA_ICII_VALID)
return 0;
@@ -176,12 +176,12 @@ static void codec_init(struct device *dev, u32 base, int addr)
return;
reg32 = (addr << 28) | 0x000f0000;
- write32(base + 0x60, reg32);
+ write32(reg32, (void *)(uintptr_t)(base + 0x60));
if (wait_for_valid(base) == -1)
return;
- reg32 = read32(base + 0x64);
+ reg32 = read32((void *)(uintptr_t)(base + 0x64));
/* 2 */
printk(BIOS_DEBUG, "Azalia: codec viddid: %08x\n", reg32);
@@ -198,7 +198,7 @@ static void codec_init(struct device *dev, u32 base, int addr)
if (wait_for_ready(base) == -1)
return;
- write32(base + 0x60, verb[i]);
+ write32(verb[i], (void *)(uintptr_t)(base + 0x60));
if (wait_for_valid(base) == -1)
return;
@@ -218,7 +218,7 @@ static void codecs_init(struct device *dev, u32 base, u32 codec_mask)
if (wait_for_ready(base) == -1)
return;
- write32(base + 0x60, pc_beep_verbs[i]);
+ write32(pc_beep_verbs[i], (void *)(uintptr_t)(base + 0x60));
if (wait_for_valid(base) == -1)
return;
diff --git a/src/southbridge/intel/i82801ix/sata.c b/src/southbridge/intel/i82801ix/sata.c
index 10c8a2b..ed3d168 100644
--- a/src/southbridge/intel/i82801ix/sata.c
+++ b/src/southbridge/intel/i82801ix/sata.c
@@ -41,34 +41,35 @@ static void sata_enable_ahci_mmap(struct device *const dev, const u8 port_map,
/* Set AHCI access mode.
No other ABAR registers should be accessed before this. */
- reg32 = read32(abar + 0x04);
+ reg32 = read32((void *)(uintptr_t)(abar + 0x04));
reg32 |= 1 << 31;
- write32(abar + 0x04, reg32);
+ write32(reg32, (void *)(uintptr_t)(abar + 0x04));
/* CAP (HBA Capabilities) : enable power management */
- reg32 = read32(abar + 0x00);
+ reg32 = read32((void *)(uintptr_t)(abar + 0x00));
/* CCCS must be set. */
reg32 |= 0x0c006080; /* set CCCS+PSC+SSC+SALP+SSS */
reg32 &= ~0x00020060; /* clear SXS+EMS+PMS */
- write32(abar + 0x00, reg32);
+ write32(reg32, (void *)(uintptr_t)(abar + 0x00));
/* PI (Ports implemented) */
- write32(abar + 0x0c, port_map);
+ write32(port_map, (void *)(uintptr_t)(abar + 0x0c));
/* PCH code reads back twice, do we need it, too? */
- (void) read32(abar + 0x0c); /* Read back 1 */
- (void) read32(abar + 0x0c); /* Read back 2 */
+ (void) read32((void *)(uintptr_t)(abar + 0x0c)); /* Read back 1 */
+ (void) read32((void *)(uintptr_t)(abar + 0x0c)); /* Read back 2 */
/* VSP (Vendor Specific Register) */
- reg32 = read32(abar + 0xa0);
+ reg32 = read32((void *)(uintptr_t)(abar + 0xa0));
reg32 &= ~0x00000001; /* clear SLPD */
- write32(abar + 0xa0, reg32);
+ write32(reg32, (void *)(uintptr_t)(abar + 0xa0));
/* Lock R/WO bits in Port command registers. */
for (i = 0; i < 6; ++i) {
if (((i == 2) || (i == 3)) && is_mobile)
continue;
const u32 addr = abar + 0x118 + (i * 0x80);
- write32(addr, read32(addr));
+ write32(read32((void *)(uintptr_t)(addr)),
+ (void *)(uintptr_t)(addr));
}
}
diff --git a/src/southbridge/intel/i82801ix/thermal.c b/src/southbridge/intel/i82801ix/thermal.c
index 3245a27..f98c958 100644
--- a/src/southbridge/intel/i82801ix/thermal.c
+++ b/src/southbridge/intel/i82801ix/thermal.c
@@ -38,16 +38,16 @@ static void thermal_init(struct device *dev)
reg32 = pci_read_config32(dev, 0x04);
pci_write_config32(dev, 0x04, reg32 | (1 << 1));
- write32(DEFAULT_TBAR + 0x04, 0); /* Clear thermal trip points. */
- write32(DEFAULT_TBAR + 0x44, 0);
+ write32(0, (void *)(uintptr_t)(DEFAULT_TBAR + 0x04)); /* Clear thermal trip points. */
+ write32(0, (void *)(uintptr_t)(DEFAULT_TBAR + 0x44));
- write8(DEFAULT_TBAR + 0x01, 0xba); /* Enable sensor 0 + 1. */
- write8(DEFAULT_TBAR + 0x41, 0xba);
+ write8(0xba, (void *)(uintptr_t)(DEFAULT_TBAR + 0x01)); /* Enable sensor 0 + 1. */
+ write8(0xba, (void *)(uintptr_t)(DEFAULT_TBAR + 0x41));
- reg8 = read8(DEFAULT_TBAR + 0x08); /* Lock thermal registers. */
- write8(DEFAULT_TBAR + 0x08, reg8 | (1 << 7));
- reg8 = read8(DEFAULT_TBAR + 0x48);
- write8(DEFAULT_TBAR + 0x48, reg8 | (1 << 7));
+ reg8 = read8((void *)(uintptr_t)(DEFAULT_TBAR + 0x08)); /* Lock thermal registers. */
+ write8(reg8 | (1 << 7), (void *)(uintptr_t)(DEFAULT_TBAR + 0x08));
+ reg8 = read8((void *)(uintptr_t)(DEFAULT_TBAR + 0x48));
+ write8(reg8 | (1 << 7), (void *)(uintptr_t)(DEFAULT_TBAR + 0x48));
reg32 = pci_read_config32(dev, 0x04);
pci_write_config32(dev, 0x04, reg32 & ~(1 << 1));
diff --git a/src/southbridge/intel/ibexpeak/azalia.c b/src/southbridge/intel/ibexpeak/azalia.c
index 314a1b1..608c554 100644
--- a/src/southbridge/intel/ibexpeak/azalia.c
+++ b/src/southbridge/intel/ibexpeak/azalia.c
@@ -40,10 +40,10 @@ static int set_bits(u32 port, u32 mask, u32 val)
/* Write (val & mask) to port */
val &= mask;
- reg32 = read32(port);
+ reg32 = read32((void *)(uintptr_t)(port));
reg32 &= ~mask;
reg32 |= val;
- write32(port, reg32);
+ write32(reg32, (void *)(uintptr_t)(port));
/* Wait for readback of register to
* match what was just written to it
@@ -52,7 +52,7 @@ static int set_bits(u32 port, u32 mask, u32 val)
do {
/* Wait 1ms based on BKDG wait time */
mdelay(1);
- reg32 = read32(port);
+ reg32 = read32((void *)(uintptr_t)(port));
reg32 &= mask;
} while ((reg32 != val) && --count);
@@ -71,10 +71,11 @@ static int codec_detect(u32 base)
goto no_codec;
/* Write back the value once reset bit is set. */
- write16(base + 0x0, read16(base + 0x0));
+ write16(read16((void *)(uintptr_t)(base + 0x0)),
+ (void *)(uintptr_t)(base + 0x0));
/* Read in Codec location (BAR + 0xe)[2..0]*/
- reg8 = read8(base + 0xe);
+ reg8 = read8((void *)(uintptr_t)(base + 0xe));
reg8 &= 0x0f;
if (!reg8)
goto no_codec;
@@ -119,7 +120,7 @@ static int wait_for_ready(u32 base)
int timeout = 1000;
while(timeout--) {
- u32 reg32 = read32(base + HDA_ICII_REG);
+ u32 reg32 = read32((void *)(uintptr_t)(base + HDA_ICII_REG));
if (!(reg32 & HDA_ICII_BUSY))
return 0;
udelay(1);
@@ -139,15 +140,15 @@ static int wait_for_valid(u32 base)
u32 reg32;
/* Send the verb to the codec */
- reg32 = read32(base + HDA_ICII_REG);
+ reg32 = read32((void *)(uintptr_t)(base + HDA_ICII_REG));
reg32 |= HDA_ICII_BUSY | HDA_ICII_VALID;
- write32(base + HDA_ICII_REG, reg32);
+ write32(reg32, (void *)(uintptr_t)(base + HDA_ICII_REG));
/* Use a 1msec timeout */
int timeout = 1000;
while(timeout--) {
- reg32 = read32(base + HDA_ICII_REG);
+ reg32 = read32((void *)(uintptr_t)(base + HDA_ICII_REG));
if ((reg32 & (HDA_ICII_VALID | HDA_ICII_BUSY)) ==
HDA_ICII_VALID)
return 0;
@@ -173,14 +174,14 @@ static void codec_init(struct device *dev, u32 base, int addr)
}
reg32 = (addr << 28) | 0x000f0000;
- write32(base + 0x60, reg32);
+ write32(reg32, (void *)(uintptr_t)(base + 0x60));
if (wait_for_valid(base) == -1) {
printk(BIOS_DEBUG, " codec not valid.\n");
return;
}
- reg32 = read32(base + 0x64);
+ reg32 = read32((void *)(uintptr_t)(base + 0x64));
/* 2 */
printk(BIOS_DEBUG, "Azalia: codec viddid: %08x\n", reg32);
@@ -197,7 +198,7 @@ static void codec_init(struct device *dev, u32 base, int addr)
if (wait_for_ready(base) == -1)
return;
- write32(base + 0x60, verb[i]);
+ write32(verb[i], (void *)(uintptr_t)(base + 0x60));
if (wait_for_valid(base) == -1)
return;
@@ -217,7 +218,7 @@ static void codecs_init(struct device *dev, u32 base, u32 codec_mask)
if (wait_for_ready(base) == -1)
return;
- write32(base + 0x60, pc_beep_verbs[i]);
+ write32(pc_beep_verbs[i], (void *)(uintptr_t)(base + 0x60));
if (wait_for_valid(base) == -1)
return;
@@ -287,9 +288,9 @@ static void azalia_init(struct device *dev)
/* Codec Initialization Programming Sequence */
/* Take controller out of reset */
- reg32 = read32(base + 0x08);
+ reg32 = read32((void *)(uintptr_t)(base + 0x08));
reg32 |= (1 << 0);
- write32(base + 0x08, reg32);
+ write32(reg32, (void *)(uintptr_t)(base + 0x08));
/* Wait 1ms */
udelay(1000);
diff --git a/src/southbridge/intel/ibexpeak/early_thermal.c b/src/southbridge/intel/ibexpeak/early_thermal.c
index d23749e..8334a6f 100644
--- a/src/southbridge/intel/ibexpeak/early_thermal.c
+++ b/src/southbridge/intel/ibexpeak/early_thermal.c
@@ -43,11 +43,12 @@ void early_thermal_init(void)
/* Perform init. */
/* Configure TJmax. */
msr = rdmsr(MSR_TEMPERATURE_TARGET);
- write16(0x40000012, ((msr.lo >> 16) & 0xff) << 6);
+ write16(((msr.lo >> 16) & 0xff) << 6, (void *)(uintptr_t)(0x40000012));
/* Northbridge temperature slope and offset. */
- write16(0x40000016, 0x7746);
+ write16(0x7746, (void *)(uintptr_t)(0x40000016));
/* Enable thermal data reporting, processor, PCH and northbridge. */
- write16(0x4000001a, (read16(0x4000001a) & ~0xf) | 0x10f0);
+ write16((read16((void *)(uintptr_t)(0x4000001a)) & ~0xf) | 0x10f0,
+ (void *)(uintptr_t)(0x4000001a));
/* Disable temporary BAR. */
pci_write_config32(dev, 0x40,
diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c
index 2124711..148ff24 100644
--- a/src/southbridge/intel/ibexpeak/lpc.c
+++ b/src/southbridge/intel/ibexpeak/lpc.c
@@ -394,7 +394,8 @@ static void enable_hpet(void)
reg32 &= ~(3 << 0);
RCBA32(HPTC) = reg32;
- write32(0xfed00010, read32(0xfed00010) | 1);
+ write32(read32((void *)(uintptr_t)(0xfed00010)) | 1,
+ (void *)(uintptr_t)(0xfed00010));
}
static void enable_clock_gating(device_t dev)
diff --git a/src/southbridge/intel/ibexpeak/me.c b/src/southbridge/intel/ibexpeak/me.c
index f94b17f..766d559 100644
--- a/src/southbridge/intel/ibexpeak/me.c
+++ b/src/southbridge/intel/ibexpeak/me.c
@@ -105,7 +105,7 @@ static void mei_dump(void *ptr, int dword, int offset, const char *type)
static inline void mei_read_dword_ptr(void *ptr, int offset)
{
- u32 dword = read32(mei_base_address + offset);
+ u32 dword = read32((void *)(uintptr_t)(mei_base_address + offset));
memcpy(ptr, &dword, sizeof(dword));
mei_dump(ptr, dword, offset, "READ");
}
@@ -114,7 +114,7 @@ static inline void mei_write_dword_ptr(void *ptr, int offset)
{
u32 dword = 0;
memcpy(&dword, ptr, sizeof(dword));
- write32(mei_base_address + offset, dword);
+ write32(dword, (void *)(uintptr_t)(mei_base_address + offset));
mei_dump(ptr, dword, offset, "WRITE");
}
@@ -145,13 +145,13 @@ static inline void read_me_csr(struct mei_csr *csr)
static inline void write_cb(u32 dword)
{
- write32(mei_base_address + MEI_H_CB_WW, dword);
+ write32(dword, (void *)(uintptr_t)(mei_base_address + MEI_H_CB_WW));
mei_dump(NULL, dword, MEI_H_CB_WW, "WRITE");
}
static inline u32 read_cb(void)
{
- u32 dword = read32(mei_base_address + MEI_ME_CB_RW);
+ u32 dword = read32((void *)(uintptr_t)(mei_base_address + MEI_ME_CB_RW));
mei_dump(NULL, dword, MEI_ME_CB_RW, "READ");
return dword;
}
diff --git a/src/southbridge/intel/ibexpeak/sata.c b/src/southbridge/intel/ibexpeak/sata.c
index 5f3c4d3..207c80f 100644
--- a/src/southbridge/intel/ibexpeak/sata.c
+++ b/src/southbridge/intel/ibexpeak/sata.c
@@ -106,7 +106,7 @@ static void sata_init(struct device *dev)
abar = pci_read_config32(dev, PCI_BASE_ADDRESS_5);
printk(BIOS_DEBUG, "ABAR: %08X\n", abar);
/* CAP (HBA Capabilities) : enable power management */
- reg32 = read32(abar + 0x00);
+ reg32 = read32((void *)(uintptr_t)(abar + 0x00));
reg32 |= 0x0c006000; // set PSC+SSC+SALP+SSS
reg32 &= ~0x00020060; // clear SXS+EMS+PMS
/* Set ISS, if available */
@@ -115,19 +115,20 @@ static void sata_init(struct device *dev)
reg32 |= (config->sata_interface_speed_support & 0x03)
<< 20;
}
- write32(abar + 0x00, reg32);
+ write32(reg32, (void *)(uintptr_t)(abar + 0x00));
/* PI (Ports implemented) */
- write32(abar + 0x0c, config->sata_port_map);
- (void)read32(abar + 0x0c); /* Read back 1 */
- (void)read32(abar + 0x0c); /* Read back 2 */
+ write32(config->sata_port_map,
+ (void *)(uintptr_t)(abar + 0x0c));
+ (void)read32((void *)(uintptr_t)(abar + 0x0c)); /* Read back 1 */
+ (void)read32((void *)(uintptr_t)(abar + 0x0c)); /* Read back 2 */
/* CAP2 (HBA Capabilities Extended) */
- reg32 = read32(abar + 0x24);
+ reg32 = read32((void *)(uintptr_t)(abar + 0x24));
reg32 &= ~0x00000002;
- write32(abar + 0x24, reg32);
+ write32(reg32, (void *)(uintptr_t)(abar + 0x24));
/* VSP (Vendor Specific Register */
- reg32 = read32(abar + 0xa0);
+ reg32 = read32((void *)(uintptr_t)(abar + 0xa0));
reg32 &= ~0x00000005;
- write32(abar + 0xa0, reg32);
+ write32(reg32, (void *)(uintptr_t)(abar + 0xa0));
} else {
/* IDE */
printk(BIOS_DEBUG, "SATA: Controller in plain mode.\n");
diff --git a/src/southbridge/intel/ibexpeak/thermal.c b/src/southbridge/intel/ibexpeak/thermal.c
index fa39626..024d84a 100644
--- a/src/southbridge/intel/ibexpeak/thermal.c
+++ b/src/southbridge/intel/ibexpeak/thermal.c
@@ -35,14 +35,14 @@ static void thermal_init(struct device *dev)
if (!res)
return;
- write32(res->base + 4, 0x3a2b);
- write8(res->base + 0xe, 0x40);
- write16(res->base + 0x56, 0xffff);
- write16(res->base + 0x64, 0xffff);
- write16(res->base + 0x66, 0xffff);
- write16(res->base + 0x68, 0xfa);
+ write32(0x3a2b, (void *)(uintptr_t)(res->base + 4));
+ write8(0x40, (void *)(uintptr_t)(res->base + 0xe));
+ write16(0xffff, (void *)(uintptr_t)(res->base + 0x56));
+ write16(0xffff, (void *)(uintptr_t)(res->base + 0x64));
+ write16(0xffff, (void *)(uintptr_t)(res->base + 0x66));
+ write16(0xfa, (void *)(uintptr_t)(res->base + 0x68));
- write8(res->base + 1, 0xb8);
+ write8(0xb8, (void *)(uintptr_t)(res->base + 1));
printk(BIOS_DEBUG, "Thermal init done.\n");
}
diff --git a/src/southbridge/intel/ibexpeak/usb_ehci.c b/src/southbridge/intel/ibexpeak/usb_ehci.c
index 868a068..a38d313 100644
--- a/src/southbridge/intel/ibexpeak/usb_ehci.c
+++ b/src/southbridge/intel/ibexpeak/usb_ehci.c
@@ -60,8 +60,9 @@ static void usb_ehci_init(struct device *dev)
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
/* Number of ports and companion controllers. */
- reg32 = read32(res->base + 4);
- write32(res->base + 4, (reg32 & 0xfff00000) | 2);
+ reg32 = read32((void *)(uintptr_t)(res->base + 4));
+ write32((reg32 & 0xfff00000) | 2,
+ (void *)(uintptr_t)(res->base + 4));
}
/* Restore protection. */
diff --git a/src/southbridge/intel/lynxpoint/azalia.c b/src/southbridge/intel/lynxpoint/azalia.c
index be056be..5181b21 100644
--- a/src/southbridge/intel/lynxpoint/azalia.c
+++ b/src/southbridge/intel/lynxpoint/azalia.c
@@ -118,9 +118,9 @@ static void azalia_pch_init(struct device *dev, u32 base)
pci_write_config8(dev, 0x4d, reg8);
if (pch_is_lp()) {
- reg16 = read32(base + 0x0012);
+ reg16 = read32((void *)(uintptr_t)(base + 0x0012));
reg16 |= (1 << 0);
- write32(base + 0x0012, reg16);
+ write32(reg16, (void *)(uintptr_t)(base + 0x0012));
/* disable Auto Voltage Detector */
reg8 = pci_read_config8(dev, 0x42);
diff --git a/src/southbridge/intel/lynxpoint/hda_verb.c b/src/southbridge/intel/lynxpoint/hda_verb.c
index 234a1ab..59b2bb6 100644
--- a/src/southbridge/intel/lynxpoint/hda_verb.c
+++ b/src/southbridge/intel/lynxpoint/hda_verb.c
@@ -35,10 +35,10 @@ static int set_bits(u32 port, u32 mask, u32 val)
/* Write (val & mask) to port */
val &= mask;
- reg32 = read32(port);
+ reg32 = read32((void *)(uintptr_t)(port));
reg32 &= ~mask;
reg32 |= val;
- write32(port, reg32);
+ write32(reg32, (void *)(uintptr_t)(port));
/* Wait for readback of register to
* match what was just written to it
@@ -47,7 +47,7 @@ static int set_bits(u32 port, u32 mask, u32 val)
do {
/* Wait 1ms based on BKDG wait time */
mdelay(1);
- reg32 = read32(port);
+ reg32 = read32((void *)(uintptr_t)(port));
reg32 &= mask;
} while ((reg32 != val) && --count);
@@ -69,10 +69,11 @@ int hda_codec_detect(u32 base)
goto no_codec;
/* Write back the value once reset bit is set. */
- write16(base + HDA_GCAP_REG, read16(base + HDA_GCAP_REG));
+ write16(read16((void *)(uintptr_t)(base + HDA_GCAP_REG)),
+ (void *)(uintptr_t)(base + HDA_GCAP_REG));
/* Read in Codec location (BAR + 0xe)[2..0]*/
- reg8 = read8(base + HDA_STATESTS_REG);
+ reg8 = read8((void *)(uintptr_t)(base + HDA_STATESTS_REG));
reg8 &= 0x0f;
if (!reg8)
goto no_codec;
@@ -99,7 +100,7 @@ static int hda_wait_for_ready(u32 base)
int timeout = 50;
while(timeout--) {
- u32 reg32 = read32(base + HDA_ICII_REG);
+ u32 reg32 = read32((void *)(uintptr_t)(base + HDA_ICII_REG));
if (!(reg32 & HDA_ICII_BUSY))
return 0;
udelay(1);
@@ -118,16 +119,16 @@ static int hda_wait_for_valid(u32 base)
u32 reg32;
/* Send the verb to the codec */
- reg32 = read32(base + HDA_ICII_REG);
+ reg32 = read32((void *)(uintptr_t)(base + HDA_ICII_REG));
reg32 |= HDA_ICII_BUSY | HDA_ICII_VALID;
- write32(base + HDA_ICII_REG, reg32);
+ write32(reg32, (void *)(uintptr_t)(base + HDA_ICII_REG));
/* Use a 50 usec timeout - the Linux kernel uses the
* same duration */
int timeout = 50;
while(timeout--) {
- reg32 = read32(base + HDA_ICII_REG);
+ reg32 = read32((void *)(uintptr_t)(base + HDA_ICII_REG));
if ((reg32 & (HDA_ICII_VALID | HDA_ICII_BUSY)) ==
HDA_ICII_VALID)
return 0;
@@ -193,7 +194,7 @@ int hda_codec_write(u32 base, u32 size, const u32 *data)
if (hda_wait_for_ready(base) < 0)
return -1;
- write32(base + HDA_IC_REG, data[i]);
+ write32(data[i], (void *)(uintptr_t)(base + HDA_IC_REG));
if (hda_wait_for_valid(base) < 0)
return -1;
@@ -225,7 +226,7 @@ int hda_codec_init(u32 base, int addr, int verb_size, const u32 *verb_data)
}
reg32 = (addr << 28) | 0x000f0000;
- write32(base + HDA_IC_REG, reg32);
+ write32(reg32, (void *)(uintptr_t)(base + HDA_IC_REG));
if (hda_wait_for_valid(base) < 0) {
printk(BIOS_DEBUG, " codec not valid.\n");
@@ -233,7 +234,7 @@ int hda_codec_init(u32 base, int addr, int verb_size, const u32 *verb_data)
}
/* 2 */
- reg32 = read32(base + HDA_IR_REG);
+ reg32 = read32((void *)(uintptr_t)(base + HDA_IR_REG));
printk(BIOS_DEBUG, "HDA: codec viddid: %08x\n", reg32);
size = hda_find_verb(verb_size, verb_data, reg32, &verb);
diff --git a/src/southbridge/intel/lynxpoint/me_9.x.c b/src/southbridge/intel/lynxpoint/me_9.x.c
index dfed6de..befeeda 100644
--- a/src/southbridge/intel/lynxpoint/me_9.x.c
+++ b/src/southbridge/intel/lynxpoint/me_9.x.c
@@ -104,7 +104,7 @@ static void mei_dump(void *ptr, int dword, int offset, const char *type)
static inline void mei_read_dword_ptr(void *ptr, int offset)
{
- u32 dword = read32(mei_base_address + offset);
+ u32 dword = read32((void *)(uintptr_t)(mei_base_address + offset));
memcpy(ptr, &dword, sizeof(dword));
mei_dump(ptr, dword, offset, "READ");
}
@@ -113,7 +113,7 @@ static inline void mei_write_dword_ptr(void *ptr, int offset)
{
u32 dword = 0;
memcpy(&dword, ptr, sizeof(dword));
- write32(mei_base_address + offset, dword);
+ write32(dword, (void *)(uintptr_t)(mei_base_address + offset));
mei_dump(ptr, dword, offset, "WRITE");
}
@@ -141,13 +141,13 @@ static inline void read_me_csr(struct mei_csr *csr)
static inline void write_cb(u32 dword)
{
- write32(mei_base_address + MEI_H_CB_WW, dword);
+ write32(dword, (void *)(uintptr_t)(mei_base_address + MEI_H_CB_WW));
mei_dump(NULL, dword, MEI_H_CB_WW, "WRITE");
}
static inline u32 read_cb(void)
{
- u32 dword = read32(mei_base_address + MEI_ME_CB_RW);
+ u32 dword = read32((void *)(uintptr_t)(mei_base_address + MEI_ME_CB_RW));
mei_dump(NULL, dword, MEI_ME_CB_RW, "READ");
return dword;
}
diff --git a/src/southbridge/intel/lynxpoint/sata.c b/src/southbridge/intel/lynxpoint/sata.c
index 43a99c8..e1e7213 100644
--- a/src/southbridge/intel/lynxpoint/sata.c
+++ b/src/southbridge/intel/lynxpoint/sata.c
@@ -159,18 +159,19 @@ static void sata_init(struct device *dev)
abar = pci_read_config32(dev, PCI_BASE_ADDRESS_5);
printk(BIOS_DEBUG, "ABAR: %08X\n", abar);
/* CAP (HBA Capabilities) : enable power management */
- reg32 = read32(abar + 0x00);
+ reg32 = read32((void *)(uintptr_t)(abar + 0x00));
reg32 |= 0x0c006000; // set PSC+SSC+SALP+SSS
reg32 &= ~0x00020060; // clear SXS+EMS+PMS
if (pch_is_lp())
reg32 |= (1 << 18); // SAM: SATA AHCI MODE ONLY
- write32(abar + 0x00, reg32);
+ write32(reg32, (void *)(uintptr_t)(abar + 0x00));
/* PI (Ports implemented) */
- write32(abar + 0x0c, config->sata_port_map);
- (void) read32(abar + 0x0c); /* Read back 1 */
- (void) read32(abar + 0x0c); /* Read back 2 */
+ write32(config->sata_port_map,
+ (void *)(uintptr_t)(abar + 0x0c));
+ (void) read32((void *)(uintptr_t)(abar + 0x0c)); /* Read back 1 */
+ (void) read32((void *)(uintptr_t)(abar + 0x0c)); /* Read back 2 */
/* CAP2 (HBA Capabilities Extended)*/
- reg32 = read32(abar + 0x24);
+ reg32 = read32((void *)(uintptr_t)(abar + 0x24));
/* Enable DEVSLP */
if (pch_is_lp()) {
if (config->sata_devslp_disable)
@@ -180,7 +181,7 @@ static void sata_init(struct device *dev)
} else {
reg32 &= ~0x00000002;
}
- write32(abar + 0x24, reg32);
+ write32(reg32, (void *)(uintptr_t)(abar + 0x24));
} else {
printk(BIOS_DEBUG, "SATA: Controller in plain mode.\n");
diff --git a/src/southbridge/intel/lynxpoint/serialio.c b/src/southbridge/intel/lynxpoint/serialio.c
index 75edf5c..531be94 100644
--- a/src/southbridge/intel/lynxpoint/serialio.c
+++ b/src/southbridge/intel/lynxpoint/serialio.c
@@ -32,9 +32,9 @@
/* Enable clock in PCI mode */
static void serialio_enable_clock(struct resource *bar0)
{
- u32 reg32 = read32(bar0->base + SIO_REG_PPR_CLOCK);
+ u32 reg32 = read32((void *)(uintptr_t)(bar0->base + SIO_REG_PPR_CLOCK));
reg32 |= SIO_REG_PPR_CLOCK_EN;
- write32(bar0->base + SIO_REG_PPR_CLOCK, reg32);
+ write32(reg32, (void *)(uintptr_t)(bar0->base + SIO_REG_PPR_CLOCK));
}
/* Put Serial IO D21:F0-F6 device into desired mode. */
@@ -85,22 +85,22 @@ static void serialio_d21_ltr(struct resource *bar0)
u32 reg;
/* 1. Program BAR0 + 808h[2] = 0b */
- reg = read32(bar0->base + SIO_REG_PPR_GEN);
+ reg = read32((void *)(uintptr_t)(bar0->base + SIO_REG_PPR_GEN));
reg &= ~SIO_REG_PPR_GEN_LTR_MODE_MASK;
- write32(bar0->base + SIO_REG_PPR_GEN, reg);
+ write32(reg, (void *)(uintptr_t)(bar0->base + SIO_REG_PPR_GEN));
/* 2. Program BAR0 + 804h[1:0] = 00b */
- reg = read32(bar0->base + SIO_REG_PPR_RST);
+ reg = read32((void *)(uintptr_t)(bar0->base + SIO_REG_PPR_RST));
reg &= ~SIO_REG_PPR_RST_ASSERT;
- write32(bar0->base + SIO_REG_PPR_RST, reg);
+ write32(reg, (void *)(uintptr_t)(bar0->base + SIO_REG_PPR_RST));
/* 3. Program BAR0 + 804h[1:0] = 11b */
- reg = read32(bar0->base + SIO_REG_PPR_RST);
+ reg = read32((void *)(uintptr_t)(bar0->base + SIO_REG_PPR_RST));
reg |= SIO_REG_PPR_RST_ASSERT;
- write32(bar0->base + SIO_REG_PPR_RST, reg);
+ write32(reg, (void *)(uintptr_t)(bar0->base + SIO_REG_PPR_RST));
/* 4. Program BAR0 + 814h[31:0] = 00000000h */
- write32(bar0->base + SIO_REG_AUTO_LTR, 0);
+ write32(0, (void *)(uintptr_t)(bar0->base + SIO_REG_AUTO_LTR));
}
/* Enable LTR Auto Mode for D23:F0. */
@@ -109,26 +109,26 @@ static void serialio_d23_ltr(struct resource *bar0)
u32 reg;
/* Program BAR0 + 1008h[2] = 1b */
- reg = read32(bar0->base + SIO_REG_SDIO_PPR_GEN);
+ reg = read32((void *)(uintptr_t)(bar0->base + SIO_REG_SDIO_PPR_GEN));
reg |= SIO_REG_PPR_GEN_LTR_MODE_MASK;
- write32(bar0->base + SIO_REG_SDIO_PPR_GEN, reg);
+ write32(reg, (void *)(uintptr_t)(bar0->base + SIO_REG_SDIO_PPR_GEN));
/* Program BAR0 + 1010h = 0x00000000 */
- write32(bar0->base + SIO_REG_SDIO_PPR_SW_LTR, 0);
+ write32(0, (void *)(uintptr_t)(bar0->base + SIO_REG_SDIO_PPR_SW_LTR));
/* Program BAR0 + 3Ch[30] = 1b */
- reg = read32(bar0->base + SIO_REG_SDIO_PPR_CMD12);
+ reg = read32((void *)(uintptr_t)(bar0->base + SIO_REG_SDIO_PPR_CMD12));
reg |= SIO_REG_SDIO_PPR_CMD12_B30;
- write32(bar0->base + SIO_REG_SDIO_PPR_CMD12, reg);
+ write32(reg, (void *)(uintptr_t)(bar0->base + SIO_REG_SDIO_PPR_CMD12));
}
/* Select I2C voltage of 1.8V or 3.3V. */
static void serialio_i2c_voltage_sel(struct resource *bar0, u8 voltage)
{
- u32 reg32 = read32(bar0->base + SIO_REG_PPR_GEN);
+ u32 reg32 = read32((void *)(uintptr_t)(bar0->base + SIO_REG_PPR_GEN));
reg32 &= ~SIO_REG_PPR_GEN_VOLTAGE_MASK;
reg32 |= SIO_REG_PPR_GEN_VOLTAGE(voltage);
- write32(bar0->base + SIO_REG_PPR_GEN, reg32);
+ write32(reg32, (void *)(uintptr_t)(bar0->base + SIO_REG_PPR_GEN));
}
/* Init sequence to be run once, done as part of D21:F0 (SDMA) init. */
diff --git a/src/southbridge/intel/lynxpoint/usb_ehci.c b/src/southbridge/intel/lynxpoint/usb_ehci.c
index 845129f..94398a9 100644
--- a/src/southbridge/intel/lynxpoint/usb_ehci.c
+++ b/src/southbridge/intel/lynxpoint/usb_ehci.c
@@ -99,29 +99,32 @@ void usb_ehci_sleep_prepare(device_t dev, u8 slp_typ)
* - Clear Periodic Schedule Enable (bit4) and
* - Set Run/Stop (bit0)
*/
- reg32 = read32(bar0_base + EHCI_USB_CMD);
+ reg32 = read32((void *)(uintptr_t)(bar0_base + EHCI_USB_CMD));
if (reg32 & EHCI_USB_CMD_RUN) {
reg32 &= ~(EHCI_USB_CMD_PSE | EHCI_USB_CMD_ASE);
reg32 |= EHCI_USB_CMD_RUN;
- write32(bar0_base + EHCI_USB_CMD, reg32);
+ write32(reg32,
+ (void *)(uintptr_t)(bar0_base + EHCI_USB_CMD));
}
/* Check for Port Enabled in PORTSC(0) (RMH) */
- reg32 = read32(bar0_base + EHCI_PORTSC(0));
+ reg32 = read32((void *)(uintptr_t)(bar0_base + EHCI_PORTSC(0)));
if (reg32 & EHCI_PORTSC_ENABLED) {
/* Set suspend bit in PORTSC if not already set */
if (!(reg32 & EHCI_PORTSC_SUSPEND)) {
reg32 |= EHCI_PORTSC_SUSPEND;
- write32(bar0_base + EHCI_PORTSC(0), reg32);
+ write32(reg32,
+ (void *)(uintptr_t)(bar0_base + EHCI_PORTSC(0)));
}
/* Delay 25ms !! */
udelay(25 * 1000);
/* Clear Run/Stop bit */
- reg32 = read32(bar0_base + EHCI_USB_CMD);
+ reg32 = read32((void *)(uintptr_t)(bar0_base + EHCI_USB_CMD));
reg32 &= EHCI_USB_CMD_RUN;
- write32(bar0_base + EHCI_USB_CMD, reg32);
+ write32(reg32,
+ (void *)(uintptr_t)(bar0_base + EHCI_USB_CMD));
}
/* Restore state to D3 if that is what it was at the start */
diff --git a/src/southbridge/intel/lynxpoint/usb_xhci.c b/src/southbridge/intel/lynxpoint/usb_xhci.c
index 6c7bf04..13718b7 100644
--- a/src/southbridge/intel/lynxpoint/usb_xhci.c
+++ b/src/southbridge/intel/lynxpoint/usb_xhci.c
@@ -47,7 +47,7 @@ static int usb_xhci_port_count_usb3(device_t dev)
} else {
/* LynxPoint-H can have 0, 2, 4, or 6 SS ports */
u32 mem_base = usb_xhci_mem_base(dev);
- u32 fus = read32(mem_base + XHCI_USB3FUS);
+ u32 fus = read32((void *)(uintptr_t)(mem_base + XHCI_USB3FUS));
fus >>= XHCI_USB3FUS_SS_SHIFT;
fus &= XHCI_USB3FUS_SS_MASK;
switch (fus) {
@@ -63,18 +63,19 @@ static int usb_xhci_port_count_usb3(device_t dev)
static void usb_xhci_reset_status_usb3(u32 mem_base, int port)
{
u32 portsc = mem_base + XHCI_USB3_PORTSC(port);
- u32 status = read32(portsc);
+ u32 status = read32((void *)(uintptr_t)(portsc));
/* Do not set Port Enabled/Disabled field */
status &= ~XHCI_USB3_PORTSC_PED;
/* Clear all change status bits */
status |= XHCI_USB3_PORTSC_CHST;
- write32(portsc, status);
+ write32(status, (void *)(uintptr_t)(portsc));
}
static void usb_xhci_reset_port_usb3(u32 mem_base, int port)
{
u32 portsc = mem_base + XHCI_USB3_PORTSC(port);
- write32(portsc, read32(portsc) | XHCI_USB3_PORTSC_WPR);
+ write32(read32((void *)(uintptr_t)(portsc)) | XHCI_USB3_PORTSC_WPR,
+ (void *)(uintptr_t)(portsc));
}
#define XHCI_RESET_DELAY_US 1000 /* 1ms */
@@ -108,7 +109,7 @@ static void usb_xhci_reset_usb3(device_t dev, int all)
if (port_disabled & (1 << port))
continue;
/* Read port link status field */
- status = read32(mem_base + XHCI_USB3_PORTSC(port));
+ status = read32((void *)(uintptr_t)(mem_base + XHCI_USB3_PORTSC(port)));
status &= XHCI_USB3_PORTSC_PLS;
if (status == XHCI_PLSR_POLLING)
complete = 0;
@@ -125,7 +126,7 @@ static void usb_xhci_reset_usb3(device_t dev, int all)
/* Skip disabled ports */
if (port_disabled & (1 << port))
continue;
- status = read32(portsc) & XHCI_USB3_PORTSC_PLS;
+ status = read32((void *)(uintptr_t)(portsc)) & XHCI_USB3_PORTSC_PLS;
/* Reset all or only disconnected ports */
if (all || (status == XHCI_PLSR_RXDETECT ||
status == XHCI_PLSR_POLLING))
@@ -142,7 +143,7 @@ static void usb_xhci_reset_usb3(device_t dev, int all)
if (port_disabled & (1 << port))
continue;
/* Check if warm reset is complete */
- status = read32(mem_base + XHCI_USB3_PORTSC(port));
+ status = read32((void *)(uintptr_t)(mem_base + XHCI_USB3_PORTSC(port)));
if (!(status & XHCI_USB3_PORTSC_WRC))
complete = 0;
}
@@ -182,17 +183,17 @@ void usb_xhci_sleep_prepare(device_t dev, u8 slp_typ)
pci_write_config32(dev, 0xb0, reg32);
/* Clear MMIO 0x816c[14,2] */
- reg32 = read32(mem_base + 0x816c);
+ reg32 = read32((void *)(uintptr_t)(mem_base + 0x816c));
reg32 &= ~((1 << 14) | (1 << 2));
- write32(mem_base + 0x816c, reg32);
+ write32(reg32, (void *)(uintptr_t)(mem_base + 0x816c));
/* Reset disconnected USB3 ports */
usb_xhci_reset_usb3(dev, 0);
/* Set MMIO 0x80e0[15] */
- reg32 = read32(mem_base + 0x80e0);
+ reg32 = read32((void *)(uintptr_t)(mem_base + 0x80e0));
reg32 |= (1 << 15);
- write32(mem_base + 0x80e0, reg32);
+ write32(reg32, (void *)(uintptr_t)(mem_base + 0x80e0));
}
/* Set D3Hot state and enable PME */
@@ -307,7 +308,7 @@ static void usb_xhci_init(device_t dev)
/* Enable clock gating first */
usb_xhci_clock_gating(dev);
- reg32 = read32(mem_base + 0x8144);
+ reg32 = read32((void *)(uintptr_t)(mem_base + 0x8144));
if (pch_is_lp()) {
/* XHCIBAR + 8144h[8,7,6] = 111b */
reg32 |= (1 << 8) | (1 << 7) | (1 << 6);
@@ -316,14 +317,14 @@ static void usb_xhci_init(device_t dev)
reg32 &= ~((1 << 7) | (1 << 6));
reg32 |= (1 << 8);
}
- write32(mem_base + 0x8144, reg32);
+ write32(reg32, (void *)(uintptr_t)(mem_base + 0x8144));
if (pch_is_lp()) {
/* XHCIBAR + 816Ch[19:0] = 000e0038h */
- reg32 = read32(mem_base + 0x816c);
+ reg32 = read32((void *)(uintptr_t)(mem_base + 0x816c));
reg32 &= ~0x000fffff;
reg32 |= 0x000e0038;
- write32(mem_base + 0x816c, reg32);
+ write32(reg32, (void *)(uintptr_t)(mem_base + 0x816c));
/* D20:F0:B0h[17,14,13] = 100b */
reg32 = pci_read_config32(dev, 0xb0);
diff --git a/src/southbridge/intel/sch/audio.c b/src/southbridge/intel/sch/audio.c
index 9c77937..78ebecb 100644
--- a/src/southbridge/intel/sch/audio.c
+++ b/src/southbridge/intel/sch/audio.c
@@ -39,10 +39,10 @@ static int set_bits(u32 port, u32 mask, u32 val)
/* Write (val & mask) to port */
val &= mask;
- reg32 = read32(port);
+ reg32 = read32((void *)(uintptr_t)(port));
reg32 &= ~mask;
reg32 |= val;
- write32(port, reg32);
+ write32(reg32, (void *)(uintptr_t)(port));
/* Wait for readback of register to
* match what was just written to it
@@ -51,7 +51,7 @@ static int set_bits(u32 port, u32 mask, u32 val)
do {
/* Wait 1ms based on BKDG wait time */
mdelay(1);
- reg32 = read32(port);
+ reg32 = read32((void *)(uintptr_t)(port));
reg32 &= mask;
} while ((reg32 != val) && --count);
@@ -71,9 +71,9 @@ static int codec_detect(u32 base)
goto no_codec;
/* clear STATESTS bits (BAR + 0xE)[2:0] */
- reg32 = read32(base + 0x0E);
+ reg32 = read32((void *)(uintptr_t)(base + 0x0E));
reg32 |= 7;
- write32(base + 0x0E, reg32);
+ write32(reg32, (void *)(uintptr_t)(base + 0x0E));
/* Wait for readback of register to
* match what was just written to it
@@ -82,7 +82,7 @@ static int codec_detect(u32 base)
do {
/* Wait 1ms based on BKDG wait time */
mdelay(1);
- reg32 = read32(base + 0x0E);
+ reg32 = read32((void *)(uintptr_t)(base + 0x0E));
} while ((reg32 != 0) && --count);
/* Timeout occured */
if (!count)
@@ -97,7 +97,7 @@ static int codec_detect(u32 base)
goto no_codec;
/* Read in Codec location (BAR + 0xe)[2..0] */
- reg32 = read32(base + 0xe);
+ reg32 = read32((void *)(uintptr_t)(base + 0xe));
reg32 &= 0x0f;
if (!reg32)
goto no_codec;
@@ -150,7 +150,7 @@ static int wait_for_ready(u32 base)
int timeout = 50;
while (timeout--) {
- u32 reg32 = read32(base + HDA_ICII_REG);
+ u32 reg32 = read32((void *)(uintptr_t)(base + HDA_ICII_REG));
if (!(reg32 & HDA_ICII_BUSY))
return 0;
udelay(1);
@@ -172,16 +172,16 @@ static int wait_for_valid(u32 base)
int timeout = 25;
- write32(base + 0x68, 1);
+ write32(1, (void *)(uintptr_t)(base + 0x68));
while (timeout--) {
udelay(1);
}
timeout = 50;
while (timeout--) {
- u32 reg32 = read32(base + 0x68);
+ u32 reg32 = read32((void *)(uintptr_t)(base + 0x68));
if ((reg32 & ((1 << 1) | (1 << 0))) == (1 << 1)) {
- write32(base + 0x68, 2);
+ write32(2, (void *)(uintptr_t)(base + 0x68));
return 0;
}
udelay(1);
@@ -204,20 +204,20 @@ static void codec_init(struct device *dev, u32 base, int addr)
return;
reg32 = (addr << 28) | 0x000f0000;
- write32(base + 0x60, reg32);
+ write32(reg32, (void *)(uintptr_t)(base + 0x60));
if (wait_for_valid(base) == -1)
return;
- reg32 = read32(base + 0x0);
+ reg32 = read32((void *)(uintptr_t)(base + 0x0));
printk(BIOS_DEBUG, "sch_audio: GCAP: %08x\n", reg32);
- reg32 = read32(base + 0x4);
+ reg32 = read32((void *)(uintptr_t)(base + 0x4));
printk(BIOS_DEBUG, "sch_audio: OUTPAY: %08x\n", reg32);
- reg32 = read32(base + 0x6);
+ reg32 = read32((void *)(uintptr_t)(base + 0x6));
printk(BIOS_DEBUG, "sch_audio: INPAY: %08x\n", reg32);
- reg32 = read32(base + 0x64);
+ reg32 = read32((void *)(uintptr_t)(base + 0x64));
/* 2 */
printk(BIOS_DEBUG, "sch_audio: codec viddid: %08x\n", reg32);
@@ -234,7 +234,7 @@ static void codec_init(struct device *dev, u32 base, int addr)
if (wait_for_ready(base) == -1)
return;
- write32(base + 0x60, verb[i]);
+ write32(verb[i], (void *)(uintptr_t)(base + 0x60));
if (wait_for_valid(base) == -1)
return;
diff --git a/src/southbridge/nvidia/ck804/nic.c b/src/southbridge/nvidia/ck804/nic.c
index e285644..a9111b2 100644
--- a/src/southbridge/nvidia/ck804/nic.c
+++ b/src/southbridge/nvidia/ck804/nic.c
@@ -42,7 +42,7 @@ static void nic_init(struct device *dev)
#define NvRegPhyInterface 0xC0
#define PHY_RGMII 0x10000000
- write32(base + NvRegPhyInterface, PHY_RGMII);
+ write32(PHY_RGMII, (void *)(uintptr_t)(base + NvRegPhyInterface));
old = dword = pci_read_config32(dev, 0x30);
dword &= ~(0xf);
@@ -91,15 +91,15 @@ static void nic_init(struct device *dev)
if (!eeprom_valid) {
unsigned long mac_pos;
mac_pos = 0xffffffd0; /* See romstrap.inc and romstrap.lds. */
- mac_l = read32(mac_pos) + nic_index;
- mac_h = read32(mac_pos + 4);
+ mac_l = read32((void *)(uintptr_t)(mac_pos)) + nic_index;
+ mac_h = read32((void *)(uintptr_t)(mac_pos + 4));
}
#if 1
/* Set that into NIC MMIO. */
#define NvRegMacAddrA 0xA8
#define NvRegMacAddrB 0xAC
- write32(base + NvRegMacAddrA, mac_l);
- write32(base + NvRegMacAddrB, mac_h);
+ write32(mac_l, (void *)(uintptr_t)(base + NvRegMacAddrA));
+ write32(mac_h, (void *)(uintptr_t)(base + NvRegMacAddrB));
#else
/* Set that into NIC. */
pci_write_config32(dev, 0xa8, mac_l);
diff --git a/src/southbridge/nvidia/mcp55/azalia.c b/src/southbridge/nvidia/mcp55/azalia.c
index 67433d3..1edcb22 100644
--- a/src/southbridge/nvidia/mcp55/azalia.c
+++ b/src/southbridge/nvidia/mcp55/azalia.c
@@ -38,17 +38,17 @@ static int set_bits(u32 port, u32 mask, u32 val)
/* Write (val & mask) to port. */
val &= mask;
- reg32 = read32(port);
+ reg32 = read32((void *)(uintptr_t)(port));
reg32 &= ~mask;
reg32 |= val;
- write32(port, reg32);
+ write32(reg32, (void *)(uintptr_t)(port));
/* Wait for readback of register to match what was written to it. */
count = 50;
do {
/* Wait 1ms based on BKDG wait time. */
mdelay(1);
- reg32 = read32(port);
+ reg32 = read32((void *)(uintptr_t)(port));
reg32 &= mask;
} while ((reg32 != val) && --count);
@@ -71,7 +71,7 @@ static int codec_detect(u32 base)
goto no_codec;
/* Read in codec location (BAR + 0xe)[2..0]. */
- reg32 = read32(base + 0xe);
+ reg32 = read32((void *)(uintptr_t)(base + 0xe));
reg32 &= 0x0f;
if (!reg32)
goto no_codec;
@@ -117,7 +117,7 @@ static int wait_for_ready(u32 base)
int timeout = 50;
while (timeout--) {
- u32 reg32 = read32(base + HDA_ICII_REG);
+ u32 reg32 = read32((void *)(uintptr_t)(base + HDA_ICII_REG));
if (!(reg32 & HDA_ICII_BUSY))
return 0;
udelay(1);
@@ -135,14 +135,14 @@ static int wait_for_valid(u32 base)
u32 reg32;
/* Send the verb to the codec. */
- reg32 = read32(base + 0x68);
+ reg32 = read32((void *)(uintptr_t)(base + 0x68));
reg32 |= (1 << 0) | (1 << 1);
- write32(base + 0x68, reg32);
+ write32(reg32, (void *)(uintptr_t)(base + 0x68));
/* Use a 50 usec timeout - the Linux kernel uses the same duration. */
int timeout = 50;
while (timeout--) {
- reg32 = read32(base + HDA_ICII_REG);
+ reg32 = read32((void *)(uintptr_t)(base + HDA_ICII_REG));
if ((reg32 & (HDA_ICII_VALID | HDA_ICII_BUSY)) ==
HDA_ICII_VALID)
return 0;
@@ -165,12 +165,12 @@ static void codec_init(struct device *dev, u32 base, int addr)
return;
reg32 = (addr << 28) | 0x000f0000;
- write32(base + 0x60, reg32);
+ write32(reg32, (void *)(uintptr_t)(base + 0x60));
if (wait_for_valid(base) == -1)
return;
- reg32 = read32(base + 0x64);
+ reg32 = read32((void *)(uintptr_t)(base + 0x64));
/* 2 */
printk(BIOS_DEBUG, "Azalia: codec viddid: %08x\n", reg32);
@@ -187,7 +187,7 @@ static void codec_init(struct device *dev, u32 base, int addr)
if (wait_for_ready(base) == -1)
return;
- write32(base + 0x60, verb[i]);
+ write32(verb[i], (void *)(uintptr_t)(base + 0x60));
if (wait_for_valid(base) == -1)
return;
diff --git a/src/southbridge/nvidia/mcp55/nic.c b/src/southbridge/nvidia/mcp55/nic.c
index fd736e6..506a6ec 100644
--- a/src/southbridge/nvidia/mcp55/nic.c
+++ b/src/southbridge/nvidia/mcp55/nic.c
@@ -36,25 +36,26 @@ static int phy_read(u32 base, unsigned phy_addr, unsigned phy_reg)
u32 dword;
unsigned loop = 0x100;
- write32(base + 0x190, 0x8000); /* Clear MDIO lock bit. */
+ write32(0x8000, (void *)(uintptr_t)(base + 0x190)); /* Clear MDIO lock bit. */
mdelay(1);
- dword = read32(base + 0x190);
+ dword = read32((void *)(uintptr_t)(base + 0x190));
if (dword & (1 << 15))
return -1;
- write32(base + 0x180, 1);
- write32(base + 0x190, (phy_addr << 5) | (phy_reg));
+ write32(1, (void *)(uintptr_t)(base + 0x180));
+ write32((phy_addr << 5) | (phy_reg),
+ (void *)(uintptr_t)(base + 0x190));
do {
- dword = read32(base + 0x190);
+ dword = read32((void *)(uintptr_t)(base + 0x190));
if (--loop==0)
return -4;
} while ((dword & (1 << 15)));
- dword = read32(base + 0x180);
+ dword = read32((void *)(uintptr_t)(base + 0x180));
if (dword & 1)
return -3;
- dword = read32(base + 0x194);
+ dword = read32((void *)(uintptr_t)(base + 0x194));
return dword;
}
@@ -65,9 +66,9 @@ static void phy_detect(u32 base)
int i, val;
unsigned id;
- dword = read32(base + 0x188);
+ dword = read32((void *)(uintptr_t)(base + 0x188));
dword &= ~(1 << 20);
- write32(base + 0x188, dword);
+ write32(dword, (void *)(uintptr_t)(base + 0x188));
phy_read(base, 0, 1);
@@ -121,7 +122,7 @@ static void nic_init(struct device *dev)
#define NvRegPhyInterface 0xC0
#define PHY_RGMII 0x10000000
- write32(base + NvRegPhyInterface, PHY_RGMII);
+ write32(PHY_RGMII, (void *)(uintptr_t)(base + NvRegPhyInterface));
conf = dev->chip_info;
@@ -162,16 +163,16 @@ static void nic_init(struct device *dev)
if(!eeprom_valid) {
unsigned long mac_pos;
mac_pos = 0xffffffd0; // refer to romstrap.inc and romstrap.lds
- mac_l = read32(mac_pos) + nic_index; // overflow?
- mac_h = read32(mac_pos + 4);
+ mac_l = read32((void *)(uintptr_t)(mac_pos)) + nic_index; // overflow?
+ mac_h = read32((void *)(uintptr_t)(mac_pos + 4));
}
#if 1
// set that into NIC MMIO
#define NvRegMacAddrA 0xA8
#define NvRegMacAddrB 0xAC
- write32(base + NvRegMacAddrA, mac_l);
- write32(base + NvRegMacAddrB, mac_h);
+ write32(mac_l, (void *)(uintptr_t)(base + NvRegMacAddrA));
+ write32(mac_h, (void *)(uintptr_t)(base + NvRegMacAddrB));
#else
// set that into NIC
pci_write_config32(dev, 0xa8, mac_l);
diff --git a/src/southbridge/sis/sis966/aza.c b/src/southbridge/sis/sis966/aza.c
index 7e148cf..43abf0a 100644
--- a/src/southbridge/sis/sis966/aza.c
+++ b/src/southbridge/sis/sis966/aza.c
@@ -48,14 +48,14 @@ static int set_bits(u32 port, u32 mask, u32 val)
int count;
val &= mask;
- dword = read32(port);
+ dword = read32((void *)(uintptr_t)(port));
dword &= ~mask;
dword |= val;
- write32(port, dword);
+ write32(dword, (void *)(uintptr_t)(port));
count = 50;
do {
- dword = read32(port);
+ dword = read32((void *)(uintptr_t)(port));
dword &= mask;
udelay(100);
} while ((dword != val) && --count);
@@ -71,23 +71,23 @@ static u32 send_verb(u32 base, u32 verb)
{
u32 dword;
- dword = read32(base + 0x68);
+ dword = read32((void *)(uintptr_t)(base + 0x68));
dword=dword|(unsigned long)0x0002;
- write32(base + 0x68, dword);
+ write32(dword, (void *)(uintptr_t)(base + 0x68));
do {
- dword = read32(base + 0x68);
+ dword = read32((void *)(uintptr_t)(base + 0x68));
} while ((dword & 1)!=0);
- write32(base + 0x60, verb);
+ write32(verb, (void *)(uintptr_t)(base + 0x60));
udelay(500);
- dword = read32(base + 0x68);
+ dword = read32((void *)(uintptr_t)(base + 0x68));
dword =(dword |0x1);
- write32(base + 0x68, dword);
+ write32(dword, (void *)(uintptr_t)(base + 0x68));
do {
udelay(100);
- dword = read32(base + 0x68);
+ dword = read32((void *)(uintptr_t)(base + 0x68));
} while ((dword & 3) != 2);
- dword = read32(base + 0x64);
+ dword = read32((void *)(uintptr_t)(base + 0x64));
return dword;
}
@@ -103,7 +103,7 @@ static int codec_detect(u32 base)
set_bits(base + 0x08, 1, 1);
do{
- dword = read32(base + 0x08)&0x1;
+ dword = read32((void *)(uintptr_t)(base + 0x08))&0x1;
if(idx++>1000) { printk(BIOS_DEBUG, "controller reset fail !!! \n"); break;}
} while (dword !=1);
@@ -203,17 +203,17 @@ static void codec_init(u32 base, int addr)
/* 1 */
do {
- dword = read32(base + 0x68);
+ dword = read32((void *)(uintptr_t)(base + 0x68));
} while (dword & 1);
dword = (addr<<28) | 0x000f0000;
- write32(base + 0x60, dword);
+ write32(dword, (void *)(uintptr_t)(base + 0x60));
do {
- dword = read32(base + 0x68);
+ dword = read32((void *)(uintptr_t)(base + 0x68));
} while ((dword & 3)!=2);
- dword = read32(base + 0x64);
+ dword = read32((void *)(uintptr_t)(base + 0x64));
/* 2 */
printk(BIOS_DEBUG, "codec viddid: %08x\n", dword);
diff --git a/src/southbridge/sis/sis966/nic.c b/src/southbridge/sis/sis966/nic.c
index 18ed75e..108e04d 100644
--- a/src/southbridge/sis/sis966/nic.c
+++ b/src/southbridge/sis/sis966/nic.c
@@ -142,13 +142,13 @@ static unsigned long ReadEEprom( struct device *dev, u32 base, u32 Reg)
ulValue = (0x80 | (0x2 << 8) | (Reg << 10)); //BIT_7
- write32(base+0x3c, ulValue);
+ write32(ulValue, (void *)(uintptr_t)(base + 0x3c));
mdelay(10);
for(i=0 ; i <= LoopNum; i++)
{
- ulValue=read32(base+0x3c);
+ ulValue=read32((void *)(uintptr_t)(base + 0x3c));
if(!(ulValue & 0x0080)) //BIT_7
break;
@@ -160,7 +160,7 @@ static unsigned long ReadEEprom( struct device *dev, u32 base, u32 Reg)
if(i==LoopNum) data=0x10000;
else{
- ulValue=read32(base+0x3c);
+ ulValue=read32((void *)(uintptr_t)(base + 0x3c));
data = ((ulValue & 0xffff0000) >> 16);
}
@@ -181,14 +181,14 @@ static int phy_read(u32 base, unsigned phy_addr, unsigned phy_reg)
SMI_REQUEST);
// SmiMgtInterface Reg is the SMI management interface register(offset 44h) of MAC
- write32(base+0x44, Read_Cmd);
+ write32(Read_Cmd, (void *)(uintptr_t)(base + 0x44));
// Polling SMI_REQ bit to be deasserted indicated read command completed
do
{
// Wait 20 usec before checking status
mdelay(20);
- ulValue = read32(base+0x44);
+ ulValue = read32((void *)(uintptr_t)(base + 0x44));
} while((ulValue & SMI_REQUEST) != 0);
//printk(BIOS_DEBUG, "base %x cmd %lx ret val %lx\n", tmp,Read_Cmd,ulValue);
usData=(ulValue>>16);
@@ -278,7 +278,7 @@ static void nic_init(struct device *dev)
return;
}
- ulValue=read32(base + 0x38L); // check EEPROM existing
+ ulValue=read32((void *)(uintptr_t)(base + 0x38L)); // check EEPROM existing
if((ulValue & 0x0002))
{
@@ -299,9 +299,9 @@ static void nic_init(struct device *dev)
}else{
// read MAC address from firmware
printk(BIOS_DEBUG, "EEPROM invalid!!\nReg 0x38h=%.8lx \n",ulValue);
- MacAddr[0]=read16(0xffffffc0); // mac address store at here
- MacAddr[1]=read16(0xffffffc2);
- MacAddr[2]=read16(0xffffffc4);
+ MacAddr[0]=read16((void *)(uintptr_t)(0xffffffc0)); // mac address store at here
+ MacAddr[1]=read16((void *)(uintptr_t)(0xffffffc2));
+ MacAddr[2]=read16((void *)(uintptr_t)(0xffffffc4));
}
set_apc(dev);
diff --git a/src/southbridge/sis/sis966/usb2.c b/src/southbridge/sis/sis966/usb2.c
index e2112eb..fe60555 100644
--- a/src/southbridge/sis/sis966/usb2.c
+++ b/src/southbridge/sis/sis966/usb2.c
@@ -91,7 +91,7 @@ static void usb2_init(struct device *dev)
base = res->base;
printk(BIOS_DEBUG, "base = 0x%08x\n", base);
- write32(base+0x20, 0x2);
+ write32(0x2, (void *)(uintptr_t)(base + 0x20));
//-------------------------------------------------------------
#if DEBUG_USB2
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